pciconf.c revision 1.39
1 /* $NetBSD: pciconf.c,v 1.39 2019/03/01 05:41:56 msaitoh Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.39 2019/03/01 05:41:56 msaitoh Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 #include <sys/kmem.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pciconf.h> 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pccbbreg.h> 83 84 int pci_conf_debug = 0; 85 86 #if !defined(MIN) 87 #define MIN(a,b) (((a)<(b))?(a):(b)) 88 #define MAX(a,b) (((a)>(b))?(a):(b)) 89 #endif 90 91 /* per-bus constants. */ 92 #define MAX_CONF_DEV 32 /* Arbitrary */ 93 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 94 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 95 96 struct _s_pciconf_bus_t; /* Forward declaration */ 97 98 typedef struct _s_pciconf_dev_t { 99 int ipin; 100 int iline; 101 int min_gnt; 102 int max_lat; 103 int enable; 104 pcitag_t tag; 105 pci_chipset_tag_t pc; 106 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 107 } pciconf_dev_t; 108 109 typedef struct _s_pciconf_win_t { 110 pciconf_dev_t *dev; 111 int reg; /* 0 for busses */ 112 int align; 113 int prefetch; 114 uint64_t size; 115 uint64_t address; 116 } pciconf_win_t; 117 118 typedef struct _s_pciconf_bus_t { 119 int busno; 120 int next_busno; 121 int last_busno; 122 int max_mingnt; 123 int min_maxlat; 124 int cacheline_size; 125 int prefetch; 126 int fast_b2b; 127 int freq_66; 128 int def_ltim; 129 int max_ltim; 130 int bandwidth_used; 131 int swiz; 132 int io_32bit; 133 int pmem_64bit; 134 int io_align; 135 int mem_align; 136 int pmem_align; 137 138 int ndevs; 139 pciconf_dev_t device[MAX_CONF_DEV]; 140 141 /* These should be sorted in order of decreasing size */ 142 int nmemwin; 143 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 144 int niowin; 145 pciconf_win_t pciiowin[MAX_CONF_IO]; 146 147 bus_size_t io_total; 148 bus_size_t mem_total; 149 bus_size_t pmem_total; 150 151 struct extent *ioext; 152 struct extent *memext; 153 struct extent *pmemext; 154 155 pci_chipset_tag_t pc; 156 struct _s_pciconf_bus_t *parent_bus; 157 } pciconf_bus_t; 158 159 static int probe_bus(pciconf_bus_t *); 160 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 161 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 162 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 163 static int setup_iowins(pciconf_bus_t *); 164 static int setup_memwins(pciconf_bus_t *); 165 static int configure_bridge(pciconf_dev_t *); 166 static int configure_bus(pciconf_bus_t *); 167 static uint64_t pci_allocate_range(struct extent *, uint64_t, int); 168 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 169 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 170 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 171 172 static void print_tag(pci_chipset_tag_t, pcitag_t); 173 174 static void 175 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 176 { 177 int bus, dev, func; 178 179 pci_decompose_tag(pc, tag, &bus, &dev, &func); 180 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 181 } 182 183 /************************************************************************/ 184 /************************************************************************/ 185 /*********************** Bus probing routines ***********************/ 186 /************************************************************************/ 187 /************************************************************************/ 188 static pciconf_win_t * 189 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 190 { 191 int i, n; 192 193 n = pb->niowin; 194 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 195 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 196 return &pb->pciiowin[i]; 197 } 198 199 static pciconf_win_t * 200 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 201 { 202 int i, n; 203 204 n = pb->nmemwin; 205 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 206 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 207 return &pb->pcimemwin[i]; 208 } 209 210 /* 211 * Set up bus common stuff, then loop over devices & functions. 212 * If we find something, call pci_do_device_query()). 213 */ 214 static int 215 probe_bus(pciconf_bus_t *pb) 216 { 217 int device; 218 uint8_t devs[32]; 219 int i, n; 220 221 pb->ndevs = 0; 222 pb->niowin = 0; 223 pb->nmemwin = 0; 224 pb->freq_66 = 1; 225 #ifdef PCICONF_NO_FAST_B2B 226 pb->fast_b2b = 0; 227 #else 228 pb->fast_b2b = 1; 229 #endif 230 pb->prefetch = 1; 231 pb->max_mingnt = 0; /* we are looking for the maximum */ 232 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 233 pb->bandwidth_used = 0; 234 235 n = pci_bus_devorder(pb->pc, pb->busno, devs, __arraycount(devs)); 236 for (i = 0; i < n; i++) { 237 pcitag_t tag; 238 pcireg_t id, bhlcr; 239 int function, nfunction; 240 int confmode; 241 242 device = devs[i]; 243 244 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 245 if (pci_conf_debug) { 246 print_tag(pb->pc, tag); 247 } 248 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 249 250 if (pci_conf_debug) { 251 printf("id=%x: Vendor=%x, Product=%x\n", 252 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 253 } 254 /* Invalid vendor ID value? */ 255 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 256 continue; 257 258 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 259 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 260 for (function = 0 ; function < nfunction ; function++) { 261 tag = pci_make_tag(pb->pc, pb->busno, device, function); 262 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 263 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 264 continue; 265 if (pb->ndevs+1 < MAX_CONF_DEV) { 266 if (pci_conf_debug) { 267 print_tag(pb->pc, tag); 268 printf("Found dev 0x%04x 0x%04x -- " 269 "really probing.\n", 270 PCI_VENDOR(id), PCI_PRODUCT(id)); 271 } 272 #ifdef __HAVE_PCI_CONF_HOOK 273 confmode = pci_conf_hook(pb->pc, pb->busno, 274 device, function, id); 275 if (confmode == 0) 276 continue; 277 #else 278 /* 279 * Don't enable expansion ROMS -- some cards 280 * share address decoders between the EXPROM 281 * and PCI memory space, and enabling the ROM 282 * when not needed will cause all sorts of 283 * lossage. 284 */ 285 confmode = PCI_CONF_DEFAULT; 286 #endif 287 if (pci_do_device_query(pb, tag, device, 288 function, confmode)) 289 return -1; 290 pb->ndevs++; 291 } 292 } 293 } 294 return 0; 295 } 296 297 static void 298 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 299 { 300 pb->busno = parent->next_busno; 301 pb->next_busno = pb->busno + 1; 302 } 303 304 static void 305 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 306 { 307 pcireg_t busreg; 308 309 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 310 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 311 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 312 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 313 } 314 315 static pciconf_bus_t * 316 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 317 { 318 pciconf_bus_t *pb; 319 pcireg_t io, pmem; 320 pciconf_win_t *pi, *pm; 321 322 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 323 if (!pb) 324 panic("Unable to allocate memory for PCI configuration."); 325 326 pb->cacheline_size = parent->cacheline_size; 327 pb->parent_bus = parent; 328 alloc_busno(parent, pb); 329 330 pb->mem_align = 0x100000; /* 1M alignment */ 331 pb->pmem_align = 0x100000; /* 1M alignment */ 332 pb->io_align = 0x1000; /* 4K alignment */ 333 334 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 335 336 pb->swiz = parent->swiz + dev; 337 338 pb->ioext = NULL; 339 pb->memext = NULL; 340 pb->pmemext = NULL; 341 pb->pc = parent->pc; 342 pb->io_total = pb->mem_total = pb->pmem_total = 0; 343 344 pb->io_32bit = 0; 345 if (parent->io_32bit) { 346 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 347 if (PCI_BRIDGE_IO_32BITS(io)) { 348 pb->io_32bit = 1; 349 } 350 } 351 352 pb->pmem_64bit = 0; 353 if (parent->pmem_64bit) { 354 pmem = pci_conf_read(parent->pc, pd->tag, 355 PCI_BRIDGE_PREFETCHMEM_REG); 356 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 357 pb->pmem_64bit = 1; 358 } 359 } 360 361 if (probe_bus(pb)) { 362 printf("Failed to probe bus %d\n", pb->busno); 363 goto err; 364 } 365 366 /* We have found all subordinate busses now, reprogram busreg. */ 367 pb->last_busno = pb->next_busno-1; 368 parent->next_busno = pb->next_busno; 369 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 370 pb->last_busno); 371 if (pci_conf_debug) 372 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 373 parent->busno, pb->busno, pb->last_busno); 374 375 if (pb->io_total > 0) { 376 if (parent->niowin >= MAX_CONF_IO) { 377 printf("pciconf: too many (%d) I/O windows\n", 378 parent->niowin); 379 goto err; 380 } 381 pb->io_total |= pb->io_align - 1; /* Round up */ 382 pi = get_io_desc(parent, pb->io_total); 383 pi->dev = pd; 384 pi->reg = 0; 385 pi->size = pb->io_total; 386 pi->align = pb->io_align; /* 4K min alignment */ 387 if (parent->io_align < pb->io_align) 388 parent->io_align = pb->io_align; 389 pi->prefetch = 0; 390 parent->niowin++; 391 parent->io_total += pb->io_total; 392 } 393 394 if (pb->mem_total > 0) { 395 if (parent->nmemwin >= MAX_CONF_MEM) { 396 printf("pciconf: too many (%d) MEM windows\n", 397 parent->nmemwin); 398 goto err; 399 } 400 pb->mem_total |= pb->mem_align-1; /* Round up */ 401 pm = get_mem_desc(parent, pb->mem_total); 402 pm->dev = pd; 403 pm->reg = 0; 404 pm->size = pb->mem_total; 405 pm->align = pb->mem_align; /* 1M min alignment */ 406 if (parent->mem_align < pb->mem_align) 407 parent->mem_align = pb->mem_align; 408 pm->prefetch = 0; 409 parent->nmemwin++; 410 parent->mem_total += pb->mem_total; 411 } 412 413 if (pb->pmem_total > 0) { 414 if (parent->nmemwin >= MAX_CONF_MEM) { 415 printf("pciconf: too many MEM windows\n"); 416 goto err; 417 } 418 pb->pmem_total |= pb->pmem_align-1; /* Round up */ 419 pm = get_mem_desc(parent, pb->pmem_total); 420 pm->dev = pd; 421 pm->reg = 0; 422 pm->size = pb->pmem_total; 423 pm->align = pb->pmem_align; /* 1M alignment */ 424 if (parent->pmem_align < pb->pmem_align) 425 parent->pmem_align = pb->pmem_align; 426 pm->prefetch = 1; 427 parent->nmemwin++; 428 parent->pmem_total += pb->pmem_total; 429 } 430 431 return pb; 432 err: 433 kmem_free(pb, sizeof(*pb)); 434 return NULL; 435 } 436 437 static int 438 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, 439 int mode) 440 { 441 pciconf_dev_t *pd; 442 pciconf_win_t *pi, *pm; 443 pcireg_t classreg, cmd, icr, bhlc, bar, mask, bar64, mask64, 444 busreg; 445 uint64_t size; 446 int br, width, reg_start, reg_end; 447 448 pd = &pb->device[pb->ndevs]; 449 pd->pc = pb->pc; 450 pd->tag = tag; 451 pd->ppb = NULL; 452 pd->enable = mode; 453 454 classreg = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 455 456 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 457 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 458 459 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE 460 && PCI_HDRTYPE_TYPE(bhlc) != PCI_HDRTYPE_PPB) { 461 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 462 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 463 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 464 } else if (pci_conf_debug) { 465 print_tag(pb->pc, tag); 466 printf("device is a bridge; not clearing enables\n"); 467 } 468 469 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 470 pb->fast_b2b = 0; 471 472 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 473 pb->freq_66 = 0; 474 475 switch (PCI_HDRTYPE_TYPE(bhlc)) { 476 case PCI_HDRTYPE_DEVICE: 477 reg_start = PCI_MAPREG_START; 478 reg_end = PCI_MAPREG_END; 479 break; 480 case PCI_HDRTYPE_PPB: 481 pd->ppb = query_bus(pb, pd, dev); 482 if (pd->ppb == NULL) 483 return -1; 484 return 0; 485 case PCI_HDRTYPE_PCB: 486 reg_start = PCI_MAPREG_START; 487 reg_end = PCI_MAPREG_PCB_END; 488 489 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 490 busreg = (busreg & 0xff000000) | 491 pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT | 492 pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT | 493 pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 494 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 495 496 pb->next_busno++; 497 break; 498 default: 499 return -1; 500 } 501 502 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 503 pd->ipin = PCI_INTERRUPT_PIN(icr); 504 pd->iline = PCI_INTERRUPT_LINE(icr); 505 pd->min_gnt = PCI_MIN_GNT(icr); 506 pd->max_lat = PCI_MAX_LAT(icr); 507 if (pd->iline || pd->ipin) { 508 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 509 &pd->iline); 510 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 511 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 512 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 513 } 514 515 if (pd->min_gnt != 0 || pd->max_lat != 0) { 516 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 517 pb->max_mingnt = pd->min_gnt; 518 519 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 520 pb->min_maxlat = pd->max_lat; 521 522 pb->bandwidth_used += pd->min_gnt * 4000000 / 523 (pd->min_gnt + pd->max_lat); 524 } 525 526 width = 4; 527 for (br = reg_start; br < reg_end; br += width) { 528 #if 0 529 /* XXX Should only ignore if IDE not in legacy mode? */ 530 if (PCI_CLASS(classreg) == PCI_CLASS_MASS_STORAGE && 531 PCI_SUBCLASS(classreg) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 532 break; 533 } 534 #endif 535 bar = pci_conf_read(pb->pc, tag, br); 536 pci_conf_write(pb->pc, tag, br, 0xffffffff); 537 mask = pci_conf_read(pb->pc, tag, br); 538 pci_conf_write(pb->pc, tag, br, bar); 539 width = 4; 540 541 if ( (mode & PCI_CONF_MAP_IO) 542 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 543 /* 544 * Upper 16 bits must be one. Devices may hardwire 545 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 546 */ 547 mask |= 0xffff0000; 548 549 size = PCI_MAPREG_IO_SIZE(mask); 550 if (size == 0) { 551 if (pci_conf_debug) { 552 print_tag(pb->pc, tag); 553 printf("I/O BAR 0x%x is void\n", br); 554 } 555 continue; 556 } 557 558 if (pb->niowin >= MAX_CONF_IO) { 559 printf("pciconf: too many I/O windows\n"); 560 return -1; 561 } 562 563 pi = get_io_desc(pb, size); 564 pi->dev = pd; 565 pi->reg = br; 566 pi->size = (uint64_t) size; 567 pi->align = 4; 568 if (pb->io_align < pi->size) 569 pb->io_align = pi->size; 570 pi->prefetch = 0; 571 if (pci_conf_debug) { 572 print_tag(pb->pc, tag); 573 printf("Register 0x%x, I/O size %" PRIu64 "\n", 574 br, pi->size); 575 } 576 pb->niowin++; 577 pb->io_total += size; 578 } else if ((mode & PCI_CONF_MAP_MEM) 579 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 580 switch (PCI_MAPREG_MEM_TYPE(mask)) { 581 case PCI_MAPREG_MEM_TYPE_32BIT: 582 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 583 size = (uint64_t) PCI_MAPREG_MEM_SIZE(mask); 584 break; 585 case PCI_MAPREG_MEM_TYPE_64BIT: 586 bar64 = pci_conf_read(pb->pc, tag, br + 4); 587 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 588 mask64 = pci_conf_read(pb->pc, tag, br + 4); 589 pci_conf_write(pb->pc, tag, br + 4, bar64); 590 size = (uint64_t) PCI_MAPREG_MEM64_SIZE( 591 (((uint64_t) mask64) << 32) | mask); 592 width = 8; 593 break; 594 default: 595 print_tag(pb->pc, tag); 596 printf("reserved mapping type 0x%x\n", 597 PCI_MAPREG_MEM_TYPE(mask)); 598 continue; 599 } 600 601 if (size == 0) { 602 if (pci_conf_debug) { 603 print_tag(pb->pc, tag); 604 printf("MEM%d BAR 0x%x is void\n", 605 PCI_MAPREG_MEM_TYPE(mask) == 606 PCI_MAPREG_MEM_TYPE_64BIT ? 607 64 : 32, br); 608 } 609 continue; 610 } else { 611 if (pci_conf_debug) { 612 print_tag(pb->pc, tag); 613 printf("MEM%d BAR 0x%x has size %#lx\n", 614 PCI_MAPREG_MEM_TYPE(mask) == 615 PCI_MAPREG_MEM_TYPE_64BIT ? 616 64 : 32, br, (unsigned long)size); 617 } 618 } 619 620 if (pb->nmemwin >= MAX_CONF_MEM) { 621 printf("pciconf: too many memory windows\n"); 622 return -1; 623 } 624 625 pm = get_mem_desc(pb, size); 626 pm->dev = pd; 627 pm->reg = br; 628 pm->size = size; 629 pm->align = 4; 630 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 631 if (pci_conf_debug) { 632 print_tag(pb->pc, tag); 633 printf("Register 0x%x, memory size %" 634 PRIu64 "\n", br, pm->size); 635 } 636 pb->nmemwin++; 637 if (pm->prefetch) { 638 pb->pmem_total += size; 639 if (pb->pmem_align < pm->size) 640 pb->pmem_align = pm->size; 641 } else { 642 pb->mem_total += size; 643 if (pb->mem_align < pm->size) 644 pb->mem_align = pm->size; 645 } 646 } 647 } 648 649 if (mode & PCI_CONF_MAP_ROM) { 650 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 651 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 652 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 653 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 654 655 if (mask != 0 && mask != 0xffffffff) { 656 if (pb->nmemwin >= MAX_CONF_MEM) { 657 printf("pciconf: too many memory windows\n"); 658 return -1; 659 } 660 size = (uint64_t) PCI_MAPREG_MEM_SIZE(mask); 661 662 pm = get_mem_desc(pb, size); 663 pm->dev = pd; 664 pm->reg = PCI_MAPREG_ROM; 665 pm->size = size; 666 pm->align = 4; 667 pm->prefetch = 1; 668 if (pci_conf_debug) { 669 print_tag(pb->pc, tag); 670 printf("Expansion ROM memory size %" 671 PRIu64 "\n", pm->size); 672 } 673 pb->nmemwin++; 674 pb->pmem_total += size; 675 } 676 } else { 677 /* Don't enable ROMs if we aren't going to map them. */ 678 mode &= ~PCI_CONF_ENABLE_ROM; 679 pd->enable &= ~PCI_CONF_ENABLE_ROM; 680 } 681 682 if (!(mode & PCI_CONF_ENABLE_ROM)) { 683 /* Ensure ROM is disabled */ 684 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 685 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 686 bar & ~PCI_MAPREG_ROM_ENABLE); 687 } 688 689 return 0; 690 } 691 692 /************************************************************************/ 693 /************************************************************************/ 694 /******************** Bus configuration routines ********************/ 695 /************************************************************************/ 696 /************************************************************************/ 697 static uint64_t 698 pci_allocate_range(struct extent *ex, uint64_t amt, int align) 699 { 700 int r; 701 u_long addr; 702 703 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 704 if (r) { 705 printf("extent_alloc(%p, %#" PRIx64 ", %#x) returned %d\n", 706 ex, amt, align, r); 707 extent_print(ex); 708 return ~0ULL; 709 } 710 return addr; 711 } 712 713 static int 714 setup_iowins(pciconf_bus_t *pb) 715 { 716 pciconf_win_t *pi; 717 pciconf_dev_t *pd; 718 719 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 720 if (pi->size == 0) 721 continue; 722 723 pd = pi->dev; 724 pi->address = pci_allocate_range(pb->ioext, pi->size, 725 pi->align); 726 if (~pi->address == 0) { 727 print_tag(pd->pc, pd->tag); 728 printf("Failed to allocate PCI I/O space (%" 729 PRIu64 " req)\n", pi->size); 730 return -1; 731 } 732 if (pd->ppb && pi->reg == 0) { 733 pd->ppb->ioext = extent_create("pciconf", pi->address, 734 pi->address + pi->size, NULL, 0, 735 EX_NOWAIT); 736 if (pd->ppb->ioext == NULL) { 737 print_tag(pd->pc, pd->tag); 738 printf("Failed to alloc I/O ext. for bus %d\n", 739 pd->ppb->busno); 740 return -1; 741 } 742 continue; 743 } 744 if (!pb->io_32bit && pi->address > 0xFFFF) { 745 pi->address = 0; 746 pd->enable &= ~PCI_CONF_ENABLE_IO; 747 } else { 748 pd->enable |= PCI_CONF_ENABLE_IO; 749 } 750 if (pci_conf_debug) { 751 print_tag(pd->pc, pd->tag); 752 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 753 " (reg %x)\n", pi->size, pi->address, pi->reg); 754 } 755 pci_conf_write(pd->pc, pd->tag, pi->reg, 756 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 757 } 758 return 0; 759 } 760 761 static int 762 setup_memwins(pciconf_bus_t *pb) 763 { 764 pciconf_win_t *pm; 765 pciconf_dev_t *pd; 766 pcireg_t base; 767 struct extent *ex; 768 769 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 770 if (pm->size == 0) 771 continue; 772 773 pd = pm->dev; 774 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 775 pm->address = pci_allocate_range(ex, pm->size, pm->align); 776 if (~pm->address == 0) { 777 print_tag(pd->pc, pd->tag); 778 printf( 779 "Failed to allocate PCI memory space (%" PRIu64 780 " req)\n", pm->size); 781 return -1; 782 } 783 if (pd->ppb && pm->reg == 0) { 784 ex = extent_create("pciconf", pm->address, 785 pm->address + pm->size, NULL, 0, EX_NOWAIT); 786 if (ex == NULL) { 787 print_tag(pd->pc, pd->tag); 788 printf("Failed to alloc MEM ext. for bus %d\n", 789 pd->ppb->busno); 790 return -1; 791 } 792 if (pm->prefetch) 793 pd->ppb->pmemext = ex; 794 else 795 pd->ppb->memext = ex; 796 797 continue; 798 } 799 if (pm->prefetch && !pb->pmem_64bit && 800 pm->address > 0xFFFFFFFFULL) { 801 pm->address = 0; 802 pd->enable &= ~PCI_CONF_ENABLE_MEM; 803 } else 804 pd->enable |= PCI_CONF_ENABLE_MEM; 805 806 if (pm->reg != PCI_MAPREG_ROM) { 807 if (pci_conf_debug) { 808 print_tag(pd->pc, pd->tag); 809 printf( 810 "Putting %" PRIu64 " MEM bytes @ %#" 811 PRIx64 " (reg %x)\n", pm->size, 812 pm->address, pm->reg); 813 } 814 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 815 base = PCI_MAPREG_MEM_ADDR(pm->address) | 816 PCI_MAPREG_MEM_TYPE(base); 817 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 818 if (PCI_MAPREG_MEM_TYPE(base) == 819 PCI_MAPREG_MEM_TYPE_64BIT) { 820 base = (pcireg_t) 821 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 822 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 823 base); 824 } 825 } 826 } 827 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 828 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 829 pd = pm->dev; 830 if (!(pd->enable & PCI_CONF_MAP_ROM)) 831 continue; 832 if (pci_conf_debug) { 833 print_tag(pd->pc, pd->tag); 834 printf( 835 "Putting %" PRIu64 " ROM bytes @ %#" 836 PRIx64 " (reg %x)\n", pm->size, 837 pm->address, pm->reg); 838 } 839 base = (pcireg_t) pm->address; 840 if (pd->enable & PCI_CONF_ENABLE_ROM) 841 base |= PCI_MAPREG_ROM_ENABLE; 842 843 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 844 } 845 } 846 return 0; 847 } 848 849 /* 850 * Configure I/O, memory, and prefetcable memory spaces, then make 851 * a call to configure_bus(). 852 */ 853 static int 854 configure_bridge(pciconf_dev_t *pd) 855 { 856 unsigned long io_base, io_limit, mem_base, mem_limit; 857 pciconf_bus_t *pb; 858 pcireg_t io, iohigh, mem, cmd; 859 int rv; 860 bool isprefetchmem64; 861 862 pb = pd->ppb; 863 /* Configure I/O base & limit*/ 864 if (pb->ioext) { 865 io_base = pb->ioext->ex_start; 866 io_limit = pb->ioext->ex_end; 867 } else { 868 io_base = 0x1000; /* 4K */ 869 io_limit = 0x0000; 870 } 871 if (pb->io_32bit) { 872 iohigh = 873 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 874 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 875 } else { 876 if (io_limit > 0xFFFF) { 877 printf("Bus %d bridge does not support 32-bit I/O. ", 878 pb->busno); 879 printf("Disabling I/O accesses\n"); 880 io_base = 0x1000; /* 4K */ 881 io_limit = 0x0000; 882 } 883 iohigh = 0; 884 } 885 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 886 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 887 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 888 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 889 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 890 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 891 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 892 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 893 894 /* Configure mem base & limit */ 895 if (pb->memext) { 896 mem_base = pb->memext->ex_start; 897 mem_limit = pb->memext->ex_end; 898 } else { 899 mem_base = 0x100000; /* 1M */ 900 mem_limit = 0x000000; 901 } 902 #if ULONG_MAX > 0xffffffff 903 if (mem_limit > 0xFFFFFFFFULL) { 904 printf("Bus %d bridge MEM range out of range. ", pb->busno); 905 printf("Disabling MEM accesses\n"); 906 mem_base = 0x100000; /* 1M */ 907 mem_limit = 0x000000; 908 } 909 #endif 910 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 911 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 912 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 913 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 914 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 915 916 /* Configure prefetchable mem base & limit */ 917 if (pb->pmemext) { 918 mem_base = pb->pmemext->ex_start; 919 mem_limit = pb->pmemext->ex_end; 920 } else { 921 mem_base = 0x100000; /* 1M */ 922 mem_limit = 0x000000; 923 } 924 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 925 isprefetchmem64 = PCI_BRIDGE_PREFETCHMEM_64BITS(mem); 926 #if ULONG_MAX > 0xffffffff 927 if (!isprefetchmem64 && mem_limit > 0xFFFFFFFFULL) { 928 printf("Bus %d bridge does not support 64-bit PMEM. ", 929 pb->busno); 930 printf("Disabling prefetchable-MEM accesses\n"); 931 mem_base = 0x100000; /* 1M */ 932 mem_limit = 0x000000; 933 } 934 #endif 935 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 936 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 937 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 938 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 939 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 940 /* 941 * XXX -- 64-bit systems need a lot more than just this... 942 */ 943 if (isprefetchmem64) { 944 mem_base = (uint64_t)mem_base >> 32; 945 mem_limit = (uint64_t)mem_limit >> 32; 946 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 947 mem_base & 0xffffffff); 948 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 949 mem_limit & 0xffffffff); 950 } 951 952 rv = configure_bus(pb); 953 954 if (pb->ioext) 955 extent_destroy(pb->ioext); 956 if (pb->memext) 957 extent_destroy(pb->memext); 958 if (pb->pmemext) 959 extent_destroy(pb->pmemext); 960 if (rv == 0) { 961 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 962 cmd &= PCI_BRIDGE_CONTROL_MASK; 963 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 964 << PCI_BRIDGE_CONTROL_SHIFT; 965 if (pb->fast_b2b) { 966 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 967 << PCI_BRIDGE_CONTROL_SHIFT; 968 } 969 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 970 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 971 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 972 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 973 } 974 975 return rv; 976 } 977 978 /* 979 * Calculate latency values, allocate I/O and MEM segments, then set them 980 * up. If a PCI-PCI bridge is found, configure the bridge separately, 981 * which will cause a recursive call back here. 982 */ 983 static int 984 configure_bus(pciconf_bus_t *pb) 985 { 986 pciconf_dev_t *pd; 987 int def_ltim, max_ltim, band, bus_mhz; 988 989 if (pb->ndevs == 0) { 990 if (pci_conf_debug) 991 printf("PCI bus %d - no devices\n", pb->busno); 992 return 1; 993 } 994 bus_mhz = pb->freq_66 ? 66 : 33; 995 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 996 band = 4000000; /* 0.25us cycles/sec */ 997 if (band < pb->bandwidth_used) { 998 printf("PCI bus %d: Warning: Total bandwidth exceeded!? (%d)\n", 999 pb->busno, pb->bandwidth_used); 1000 def_ltim = -1; 1001 } else { 1002 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 1003 if (def_ltim > pb->min_maxlat) 1004 def_ltim = pb->min_maxlat; 1005 def_ltim = def_ltim * bus_mhz / 4; 1006 } 1007 def_ltim = (def_ltim + 7) & ~7; 1008 max_ltim = (max_ltim + 7) & ~7; 1009 1010 pb->def_ltim = MIN( def_ltim, 255 ); 1011 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 1012 1013 /* 1014 * Now we have what we need to initialize the devices. 1015 * It would probably be better if we could allocate all of these 1016 * for all busses at once, but "not right now". First, get a list 1017 * of free memory ranges from the m.d. system. 1018 */ 1019 if (setup_iowins(pb) || setup_memwins(pb)) { 1020 printf("PCI bus configuration failed: " 1021 "unable to assign all I/O and memory ranges.\n"); 1022 return -1; 1023 } 1024 1025 /* 1026 * Configure the latency for the devices, and enable them. 1027 */ 1028 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 1029 pcireg_t cmd, classreg, misc; 1030 int ltim; 1031 1032 if (pci_conf_debug) { 1033 print_tag(pd->pc, pd->tag); 1034 printf("Configuring device.\n"); 1035 } 1036 classreg = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1037 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1038 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1039 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1040 cmd |= PCI_COMMAND_PARITY_ENABLE; 1041 if (pd->enable & PCI_CONF_ENABLE_SERR) 1042 cmd |= PCI_COMMAND_SERR_ENABLE; 1043 if (pb->fast_b2b) 1044 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1045 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE || 1046 PCI_SUBCLASS(classreg) != PCI_SUBCLASS_BRIDGE_PCI) { 1047 if (pd->enable & PCI_CONF_ENABLE_IO) 1048 cmd |= PCI_COMMAND_IO_ENABLE; 1049 if (pd->enable & PCI_CONF_ENABLE_MEM) 1050 cmd |= PCI_COMMAND_MEM_ENABLE; 1051 if (pd->enable & PCI_CONF_ENABLE_BM) 1052 cmd |= PCI_COMMAND_MASTER_ENABLE; 1053 ltim = pd->min_gnt * bus_mhz / 4; 1054 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1055 } else { 1056 cmd |= PCI_COMMAND_MASTER_ENABLE; 1057 ltim = MIN (pb->def_ltim, pb->max_ltim); 1058 } 1059 if ((pd->enable & 1060 (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) { 1061 print_tag(pd->pc, pd->tag); 1062 printf("Disabled due to lack of resources.\n"); 1063 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1064 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1065 } 1066 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1067 1068 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1069 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1070 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1071 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1072 PCI_CACHELINE_SHIFT; 1073 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1074 1075 if (pd->ppb) { 1076 if (configure_bridge(pd) < 0) 1077 return -1; 1078 continue; 1079 } 1080 } 1081 1082 if (pci_conf_debug) 1083 printf("PCI bus %d configured\n", pb->busno); 1084 1085 return 0; 1086 } 1087 1088 /* 1089 * Let's configure the PCI bus. 1090 * This consists of basically scanning for all existing devices, 1091 * identifying their needs, and then making another pass over them 1092 * to set: 1093 * 1. I/O addresses 1094 * 2. Memory addresses (Prefetchable and not) 1095 * 3. PCI command register 1096 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1097 * Header type, Latency timer, Cache line size) register 1098 * 1099 * The command register is set to enable fast back-to-back transactions 1100 * if the host bridge says it can handle it. We also configure 1101 * Master Enable, SERR enable, parity enable, and (if this is not a 1102 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1103 * will not report some I/O space. 1104 * 1105 * The latency is computed to be a "fair share" of the bus bandwidth. 1106 * The bus bandwidth variable is initialized to the number of PCI cycles 1107 * in one second. The number of cycles taken for one transaction by each 1108 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1109 * Care is taken to ensure that the latency timer won't be set such that 1110 * it would exceed the critical time for any device. 1111 * 1112 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1113 * bridges are probed and configured recursively. 1114 */ 1115 int 1116 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1117 struct extent *memext, struct extent *pmemext, int firstbus, 1118 int cacheline_size) 1119 { 1120 pciconf_bus_t *pb; 1121 int rv; 1122 1123 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 1124 pb->busno = firstbus; 1125 pb->next_busno = pb->busno + 1; 1126 pb->last_busno = 255; 1127 pb->cacheline_size = cacheline_size; 1128 pb->parent_bus = NULL; 1129 pb->swiz = 0; 1130 pb->io_32bit = 1; 1131 pb->pmem_64bit = 0; 1132 pb->ioext = ioext; 1133 pb->memext = memext; 1134 if (pmemext == NULL) 1135 pb->pmemext = memext; 1136 else 1137 pb->pmemext = pmemext; 1138 1139 pb->pc = pc; 1140 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1141 1142 rv = probe_bus(pb); 1143 pb->last_busno = pb->next_busno-1; 1144 if (rv == 0) 1145 rv = configure_bus(pb); 1146 1147 /* 1148 * All done! 1149 */ 1150 kmem_free(pb, sizeof(*pb)); 1151 return rv; 1152 } 1153
Indexes created Mon Sep 29 03:10:08 GMT 2025