pciconf.c revision 1.4
1 /* $NetBSD: pciconf.c,v 1.4 2001/06/13 06:01:45 simonb Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 44 * information around & be able to reconfigure on the fly. 45 * - Deal with segments (See IA64 System Abstraction Layer) 46 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 47 * - Deal with ISA/VGA/VGA palette snooping 48 * - Deal with device capabilities on bridges 49 * - Worry about changing a bridge to/from transparency. 50 */ 51 52 #include "opt_pci.h" 53 54 #include <sys/param.h> 55 #include <sys/extent.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pciconf.h> 62 #include <dev/pci/pcidevs.h> 63 64 int pci_conf_debug = 0; 65 66 #if !defined(MIN) 67 #define MIN(a,b) (((a)<(b))?(a):(b)) 68 #define MAX(a,b) (((a)>(b))?(a):(b)) 69 #endif 70 71 /* per-bus constants. */ 72 #define MAX_CONF_DEV 8 /* Arbitrary */ 73 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 74 #define MAX_CONF_IO (1 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 75 76 #define PCI_BUSNO_SPACING (1 << 5) 77 78 struct _s_pciconf_bus_t; /* Forward declaration */ 79 80 typedef struct _s_pciconf_dev_t { 81 int ipin; 82 int iline; 83 int min_gnt; 84 int max_lat; 85 int enable; 86 pcitag_t tag; 87 pci_chipset_tag_t pc; 88 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 89 } pciconf_dev_t; 90 91 typedef struct _s_pciconf_win_t { 92 pciconf_dev_t *dev; 93 int reg; /* 0 for busses */ 94 int align; 95 int prefetch; 96 u_int64_t size; 97 u_int64_t address; 98 } pciconf_win_t; 99 100 typedef struct _s_pciconf_bus_t { 101 int busno; 102 int next_busno; 103 int last_busno; 104 int busno_spacing; 105 int max_mingnt; 106 int min_maxlat; 107 int prefetch; 108 int fast_b2b; 109 int freq_66; 110 int def_ltim; 111 int max_ltim; 112 int bandwidth_used; 113 int swiz; 114 int io_32bit; 115 int pmem_64bit; 116 117 int ndevs; 118 pciconf_dev_t device[MAX_CONF_DEV]; 119 120 /* These should be sorted in order of decreasing size */ 121 int nmemwin; 122 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 123 int niowin; 124 pciconf_win_t pciiowin[MAX_CONF_IO]; 125 126 bus_size_t io_total; 127 bus_size_t mem_total; 128 bus_size_t pmem_total; 129 130 struct extent *ioext; 131 struct extent *memext; 132 struct extent *pmemext; 133 134 pci_chipset_tag_t pc; 135 struct _s_pciconf_bus_t *parent_bus; 136 } pciconf_bus_t; 137 138 static int probe_bus(pciconf_bus_t *); 139 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 140 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 141 static int setup_iowins(pciconf_bus_t *); 142 static int setup_memwins(pciconf_bus_t *); 143 static int configure_bridge(pciconf_dev_t *); 144 static int configure_bus(pciconf_bus_t *); 145 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 146 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 147 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 148 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 149 150 static void print_tag(pci_chipset_tag_t, pcitag_t); 151 152 static void 153 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 154 { 155 int bus, dev, func; 156 157 pci_decompose_tag(pc, tag, &bus, &dev, &func); 158 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 159 } 160 161 /************************************************************************/ 162 /************************************************************************/ 163 /*********************** Bus probing routines ***********************/ 164 /************************************************************************/ 165 /************************************************************************/ 166 static pciconf_win_t * 167 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 168 { 169 int i, n; 170 171 n = pb->niowin; 172 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 173 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 174 return &pb->pciiowin[i]; 175 } 176 177 static pciconf_win_t * 178 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 179 { 180 int i, n; 181 182 n = pb->nmemwin; 183 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 184 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 185 return &pb->pcimemwin[i]; 186 } 187 188 /* 189 * Set up bus common stuff, then loop over devices & functions. 190 * If we find something, call pci_do_device_query()). 191 */ 192 static int 193 probe_bus(pciconf_bus_t *pb) 194 { 195 int device, maxdevs; 196 197 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 198 pb->ndevs = 0; 199 pb->niowin = 0; 200 pb->nmemwin = 0; 201 pb->freq_66 = 1; 202 pb->fast_b2b = 1; 203 pb->prefetch = 1; 204 pb->max_mingnt = 0; /* we are looking for the maximum */ 205 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 206 pb->bandwidth_used = 0; 207 208 for (device=0; device < maxdevs; device++) { 209 pcitag_t tag; 210 pcireg_t id, bhlcr; 211 int function, nfunction; 212 int confmode; 213 214 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 215 if (pci_conf_debug) { 216 print_tag(pb->pc, tag); 217 printf("probing with tag %x.\n", tag); 218 } 219 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 220 221 if (pci_conf_debug) { 222 printf("id=%x: Vendor=%x, Product=%x\n", 223 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 224 } 225 /* Invalid vendor ID value? */ 226 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 227 continue; 228 229 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 230 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 231 for (function = 0 ; function < nfunction ; function++) { 232 tag = pci_make_tag(pb->pc, pb->busno, device, function); 233 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 234 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 235 continue; 236 if (pb->ndevs+1 < MAX_CONF_DEV) { 237 if (pci_conf_debug) { 238 print_tag(pb->pc, tag); 239 printf("Found dev 0x%04x 0x%04x -- " 240 "really probing.\n", 241 PCI_VENDOR(id), PCI_PRODUCT(id)); 242 } 243 #ifdef __HAVE_PCI_CONF_HOOK 244 confmode = pci_conf_hook(pb->pc, pb->busno, 245 device, function, id); 246 if (confmode == 0) 247 continue; 248 #else 249 confmode = PCI_CONF_ALL; 250 #endif 251 if (pci_do_device_query(pb, tag, device, 252 function, confmode)) 253 return -1; 254 pb->ndevs++; 255 } 256 } 257 } 258 return 0; 259 } 260 261 static void 262 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 263 { 264 pb->busno = parent->next_busno; 265 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 266 panic("Too many PCI busses on bus %d", parent->busno); 267 parent->next_busno = parent->next_busno + parent->busno_spacing; 268 pb->next_busno = pb->busno+1; 269 pb->busno_spacing = parent->busno_spacing >> 1; 270 if (!pb->busno_spacing) 271 panic("PCI busses nested too deep."); 272 pb->last_busno = parent->next_busno - 1; 273 } 274 275 static pciconf_bus_t * 276 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 277 { 278 pciconf_bus_t *pb; 279 pcireg_t busreg, io, pmem; 280 pciconf_win_t *pi, *pm; 281 282 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 283 if (!pb) 284 panic("Unable to allocate memory for PCI configuration."); 285 286 pb->parent_bus = parent; 287 alloc_busno(parent, pb); 288 if (pci_conf_debug) 289 printf("PCI bus bridge covers busses %d-%d\n", 290 pb->busno, pb->last_busno); 291 292 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 293 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 294 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 295 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 296 297 pb->swiz = parent->swiz + dev; 298 299 pb->ioext = NULL; 300 pb->memext = NULL; 301 pb->pmemext = NULL; 302 pb->pc = parent->pc; 303 pb->io_total = pb->mem_total = pb->pmem_total = 0; 304 305 pb->io_32bit = 0; 306 if (parent->io_32bit) { 307 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 308 if (PCI_BRIDGE_IO_32BITS(io)) { 309 pb->io_32bit = 1; 310 } 311 } 312 313 pb->pmem_64bit = 0; 314 if (parent->pmem_64bit) { 315 pmem = pci_conf_read(pb->pc, pd->tag, 316 PCI_BRIDGE_PREFETCHMEM_REG); 317 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 318 pb->pmem_64bit = 1; 319 } 320 } 321 322 if (probe_bus(pb)) { 323 printf("Failed to probe bus %d\n", pb->busno); 324 goto err; 325 } 326 327 if (pb->io_total > 0) { 328 if (parent->niowin >= MAX_CONF_IO) { 329 printf("pciconf: too many I/O windows"); 330 goto err; 331 } 332 pb->io_total |= 0xfff; /* Round up */ 333 pi = get_io_desc(parent, pb->io_total); 334 pi->dev = pd; 335 pi->reg = 0; 336 pi->size = pb->io_total; 337 pi->align = 0x1000; /* 4K alignment */ 338 pi->prefetch = 0; 339 parent->niowin++; 340 parent->io_total += pb->io_total; 341 } 342 343 if (pb->mem_total > 0) { 344 if (parent->nmemwin >= MAX_CONF_MEM) { 345 printf("pciconf: too many MEM windows"); 346 goto err; 347 } 348 pb->mem_total |= 0xfffff; /* Round up */ 349 pm = get_mem_desc(parent, pb->mem_total); 350 pm->dev = pd; 351 pm->reg = 0; 352 pm->size = pb->mem_total; 353 pm->align = 0x100000; /* 1M alignment */ 354 pm->prefetch = 0; 355 parent->nmemwin++; 356 parent->mem_total += pb->mem_total; 357 } 358 359 if (pb->pmem_total > 0) { 360 if (parent->nmemwin >= MAX_CONF_MEM) { 361 printf("pciconf: too many MEM windows"); 362 goto err; 363 } 364 pb->pmem_total |= 0xfffff; /* Round up */ 365 pm = get_mem_desc(parent, pb->pmem_total); 366 pm->dev = pd; 367 pm->reg = 0; 368 pm->size = pb->pmem_total; 369 pm->align = 0x100000; /* 1M alignment */ 370 pm->prefetch = 1; 371 parent->nmemwin++; 372 parent->pmem_total += pb->pmem_total; 373 } 374 375 return pb; 376 err: 377 free(pb, M_DEVBUF); 378 return NULL; 379 } 380 381 static int 382 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 383 { 384 pciconf_dev_t *pd; 385 pciconf_win_t *pi, *pm; 386 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 387 u_int64_t size; 388 int br, width; 389 390 pd = &pb->device[pb->ndevs]; 391 pd->pc = pb->pc; 392 pd->tag = tag; 393 pd->ppb = NULL; 394 pd->enable = mode; 395 396 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 397 398 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 399 400 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 401 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 402 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 403 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 404 } else if (pci_conf_debug) { 405 print_tag(pb->pc, tag); 406 printf("device is a bridge; not clearing enables\n"); 407 } 408 409 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 410 pb->fast_b2b = 0; 411 412 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 413 pb->freq_66 = 0; 414 415 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 416 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 417 pd->ppb = query_bus(pb, pd, dev); 418 if (pd->ppb == NULL) 419 return -1; 420 return 0; 421 } 422 423 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 424 pd->ipin = PCI_INTERRUPT_PIN(icr); 425 pd->iline = PCI_INTERRUPT_LINE(icr); 426 pd->min_gnt = PCI_MIN_GNT(icr); 427 pd->max_lat = PCI_MAX_LAT(icr); 428 if (pd->iline || pd->ipin) { 429 pci_conf_interrupt(pb->pc, pb->busno, dev, func, pb->swiz, 430 &pd->iline); 431 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 432 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 433 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 434 } 435 436 if (pd->min_gnt != 0 || pd->max_lat != 0) { 437 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 438 pb->max_mingnt = pd->min_gnt; 439 440 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 441 pb->min_maxlat = pd->max_lat; 442 443 pb->bandwidth_used += pd->min_gnt * 4000000 / 444 (pd->min_gnt + pd->max_lat); 445 } 446 447 width = 4; 448 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 449 #if 0 450 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 451 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 452 break; 453 } 454 #endif 455 bar = pci_conf_read(pb->pc, tag, br); 456 pci_conf_write(pb->pc, tag, br, 0xffffffff); 457 mask = pci_conf_read(pb->pc, tag, br); 458 pci_conf_write(pb->pc, tag, br, bar); 459 width = 4; 460 461 if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) { 462 /* Upper 16 bits must be one. */ 463 /* XXXJRT -- is this really true? */ 464 mask |= 0xffff0000; 465 466 size = PCI_MAPREG_IO_SIZE(mask); 467 if (size == 0) { 468 if (pci_conf_debug) { 469 print_tag(pb->pc, tag); 470 printf("I/O BAR 0x%x is void\n", br); 471 } 472 continue; 473 } 474 475 if (pb->niowin >= MAX_CONF_IO) { 476 printf("pciconf: too many I/O windows"); 477 return -1; 478 } 479 480 pi = get_io_desc(pb, size); 481 pi->dev = pd; 482 pi->reg = br; 483 pi->size = (u_int64_t) size; 484 pi->align = 4; 485 pi->prefetch = 0; 486 if (pci_conf_debug) { 487 print_tag(pb->pc, tag); 488 printf("Register 0x%x, I/O size %llu\n", 489 br, pi->size); 490 } 491 pb->niowin++; 492 pb->io_total += size; 493 } else if ((mode & PCI_CONF_MAP_MEM) 494 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 495 switch (PCI_MAPREG_MEM_TYPE(mask)) { 496 case PCI_MAPREG_MEM_TYPE_32BIT: 497 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 498 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 499 break; 500 case PCI_MAPREG_MEM_TYPE_64BIT: 501 bar64 = pci_conf_read(pb->pc, tag, br + 4); 502 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 503 mask64 = pci_conf_read(pb->pc, tag, br + 4); 504 pci_conf_write(pb->pc, tag, br + 4, bar64); 505 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 506 (((u_int64_t) mask64) << 32) | mask); 507 width = 8; 508 continue; 509 default: 510 print_tag(pb->pc, tag); 511 printf("reserved mapping type 0x%x\n", 512 PCI_MAPREG_MEM_TYPE(mask)); 513 continue; 514 } 515 516 if (size == 0) { 517 if (pci_conf_debug) { 518 print_tag(pb->pc, tag); 519 printf("MEM%d BAR 0x%x is void\n", 520 PCI_MAPREG_MEM_TYPE(mask) == 521 PCI_MAPREG_MEM_TYPE_64BIT ? 522 64 : 32, br); 523 } 524 continue; 525 } 526 527 if (pb->nmemwin >= MAX_CONF_MEM) { 528 printf("pciconf: too many memory windows"); 529 return -1; 530 } 531 532 pm = get_mem_desc(pb, size); 533 pm->dev = pd; 534 pm->reg = br; 535 pm->size = size; 536 pm->align = 4; 537 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 538 if (pci_conf_debug) { 539 print_tag(pb->pc, tag); 540 printf("Register 0x%x, memory size %llu\n", 541 br, pm->size); 542 } 543 pb->nmemwin++; 544 if (pm->prefetch) { 545 pb->pmem_total += size; 546 } else { 547 pb->mem_total += size; 548 } 549 } 550 } 551 552 if (mode & PCI_CONF_MAP_ROM) { 553 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 554 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 555 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 556 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 557 558 if (mask != 0 && mask != 0xffffffff) { 559 if (pb->nmemwin >= MAX_CONF_MEM) { 560 printf("pciconf: too many memory windows"); 561 return -1; 562 } 563 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 564 565 pm = get_mem_desc(pb, size); 566 pm->dev = pd; 567 pm->reg = PCI_MAPREG_ROM; 568 pm->size = size; 569 pm->align = 4; 570 pm->prefetch = 1; 571 if (pci_conf_debug) { 572 print_tag(pb->pc, tag); 573 printf("Expansion ROM memory size %llu\n", pm->size); 574 } 575 pb->nmemwin++; 576 pb->pmem_total += size; 577 } 578 } 579 580 return 0; 581 } 582 583 /************************************************************************/ 584 /************************************************************************/ 585 /******************** Bus configuration routines ********************/ 586 /************************************************************************/ 587 /************************************************************************/ 588 static u_int64_t 589 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 590 { 591 int r; 592 u_long addr; 593 594 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 595 if (r) { 596 addr = (u_long) -1; 597 printf("extent_alloc(%p, %llu, %d) returned %d\n", 598 ex, amt, align, r); 599 extent_print(ex); 600 } 601 return (pcireg_t) addr; 602 } 603 604 static int 605 setup_iowins(pciconf_bus_t *pb) 606 { 607 pciconf_win_t *pi; 608 pciconf_dev_t *pd; 609 610 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 611 if (pi->size == 0) 612 continue; 613 614 pd = pi->dev; 615 pi->address = pci_allocate_range(pb->ioext, pi->size, 616 pi->align); 617 if (pi->address == -1) { 618 print_tag(pd->pc, pd->tag); 619 printf("Failed to allocate PCI I/O space (%llu req)\n", 620 pi->size); 621 return -1; 622 } 623 if (!pb->io_32bit && pi->address > 0xFFFF) { 624 pi->address = 0; 625 pd->enable = 0; 626 } 627 if (pd->ppb && pi->reg == 0) { 628 pd->ppb->ioext = extent_create("pciconf", pi->address, 629 pi->address + pi->size, M_DEVBUF, NULL, 0, 630 EX_NOWAIT); 631 if (pd->ppb->ioext == NULL) { 632 print_tag(pd->pc, pd->tag); 633 printf("Failed to alloc I/O ext. for bus %d\n", 634 pd->ppb->busno); 635 return -1; 636 } 637 continue; 638 } 639 if (pci_conf_debug) { 640 print_tag(pd->pc, pd->tag); 641 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 642 pi->size, pi->address, pi->reg); 643 } 644 pci_conf_write(pd->pc, pd->tag, pi->reg, 645 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 646 } 647 return 0; 648 } 649 650 static int 651 setup_memwins(pciconf_bus_t *pb) 652 { 653 pciconf_win_t *pm; 654 pciconf_dev_t *pd; 655 pcireg_t base; 656 struct extent *ex; 657 658 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 659 if (pm->size == 0) 660 continue; 661 662 pd = pm->dev; 663 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 664 pm->address = pci_allocate_range(ex, pm->size, pm->align); 665 if (pm->address == -1) { 666 print_tag(pd->pc, pd->tag); 667 printf( 668 "Failed to allocate PCI memory space (%llu req)\n", 669 pm->size); 670 return -1; 671 } 672 if (pd->ppb && pm->reg == 0) { 673 ex = extent_create("pciconf", pm->address, 674 pm->address + pm->size, M_DEVBUF, NULL, 0, 675 EX_NOWAIT); 676 if (ex == NULL) { 677 print_tag(pd->pc, pd->tag); 678 printf("Failed to alloc MEM ext. for bus %d\n", 679 pd->ppb->busno); 680 return -1; 681 } 682 if (pm->prefetch) { 683 pd->ppb->pmemext = ex; 684 } else { 685 pd->ppb->memext = ex; 686 } 687 continue; 688 } 689 if (pm->prefetch && !pb->pmem_64bit && 690 pm->address > 0xFFFFFFFFULL) { 691 pm->address = 0; 692 pd->enable = 0; 693 } 694 if (pm->reg != PCI_MAPREG_ROM) { 695 if (pci_conf_debug) { 696 print_tag(pd->pc, pd->tag); 697 printf( 698 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 699 pm->size, pm->address, pm->reg); 700 } 701 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 702 base = PCI_MAPREG_MEM_ADDR(pm->address) | 703 PCI_MAPREG_MEM_TYPE(base); 704 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 705 if (PCI_MAPREG_MEM_TYPE(base) == 706 PCI_MAPREG_MEM_TYPE_64BIT) { 707 base = (pcireg_t) 708 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 709 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 710 base); 711 } 712 } 713 } 714 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 715 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 716 pd = pm->dev; 717 if (pci_conf_debug) { 718 print_tag(pd->pc, pd->tag); 719 printf( 720 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 721 pm->size, pm->address, pm->reg); 722 } 723 base = ((pcireg_t) pm->address) | PCI_MAPREG_TYPE_ROM; 724 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 725 } 726 } 727 return 0; 728 } 729 730 /* 731 * Configure I/O, memory, and prefetcable memory spaces, then make 732 * a call to configure_bus(). 733 */ 734 static int 735 configure_bridge(pciconf_dev_t *pd) 736 { 737 unsigned long io_base, io_limit, mem_base, mem_limit; 738 pciconf_bus_t *pb; 739 pcireg_t io, iohigh, mem, cmd; 740 int rv; 741 742 pb = pd->ppb; 743 /* Configure I/O base & limit*/ 744 if (pb->ioext) { 745 io_base = pb->ioext->ex_start; 746 io_limit = pb->ioext->ex_end; 747 } else { 748 io_base = 0x1000; /* 4K */ 749 io_limit = 0x0000; 750 } 751 if (pb->io_32bit) { 752 iohigh = 753 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 754 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 755 } else { 756 if (io_limit > 0xFFFF) { 757 printf("Bus %d bridge does not support 32-bit I/O. ", 758 pb->busno); 759 printf("Disabling I/O accesses\n"); 760 io_base = 0x1000; /* 4K */ 761 io_limit = 0x0000; 762 } 763 iohigh = 0; 764 } 765 io &= (PCI_BRIDGE_STATIO_STATUS_MASK << 766 PCI_BRIDGE_STATIO_STATUS_SHIFT); 767 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 768 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 769 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 770 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 771 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 772 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 773 774 /* Configure mem base & limit */ 775 if (pb->memext) { 776 mem_base = pb->memext->ex_start; 777 mem_limit = pb->memext->ex_end; 778 } else { 779 mem_base = 0x100000; /* 1M */ 780 mem_limit = 0x000000; 781 } 782 if (mem_limit > 0xFFFFFFFFULL) { 783 printf("Bus %d bridge MEM range out of range. ", pb->busno); 784 printf("Disabling MEM accesses\n"); 785 mem_base = 0x100000; /* 1M */ 786 mem_limit = 0x000000; 787 } 788 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 789 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 790 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 791 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 792 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 793 794 /* Configure prefetchable mem base & limit */ 795 if (pb->pmemext) { 796 mem_base = pb->pmemext->ex_start; 797 mem_limit = pb->pmemext->ex_end; 798 } else { 799 mem_base = 0x100000; /* 1M */ 800 mem_limit = 0x000000; 801 } 802 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 803 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 804 printf("Bus %d bridge does not support 64-bit PMEM. ", 805 pb->busno); 806 printf("Disabling prefetchable-MEM accesses\n"); 807 mem_base = 0x100000; /* 1M */ 808 mem_limit = 0x000000; 809 } 810 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 811 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 812 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 813 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 814 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 815 /* 816 * XXX -- 64-bit systems need a lot more than just this... 817 */ 818 if (sizeof(u_long) > 4) { 819 mem_base = (int64_t) mem_base >> 32; 820 mem_limit = (int64_t) mem_limit >> 32; 821 } 822 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 823 mem_base & 0xffffffff); 824 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 825 mem_limit & 0xffffffff); 826 827 rv = configure_bus(pb); 828 829 if (pb->ioext) 830 extent_destroy(pb->ioext); 831 if (pb->memext) 832 extent_destroy(pb->memext); 833 if (pb->pmemext) 834 extent_destroy(pb->pmemext); 835 if (rv == 0) { 836 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 837 cmd &= PCI_BRIDGE_CONTROL_MASK; 838 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 839 << PCI_BRIDGE_CONTROL_SHIFT; 840 if (pb->fast_b2b) { 841 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 842 << PCI_BRIDGE_CONTROL_SHIFT; 843 } 844 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 845 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 846 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 847 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 848 } 849 850 return rv; 851 } 852 853 /* 854 * Calculate latency values, allocate I/O and MEM segments, then set them 855 * up. If a PCI-PCI bridge is found, configure the bridge separately, 856 * which will cause a recursive call back here. 857 */ 858 static int 859 configure_bus(pciconf_bus_t *pb) 860 { 861 pciconf_dev_t *pd; 862 int def_ltim, max_ltim, band; 863 864 /* MIN_GNT assumes a clock rate of 33MHz */ 865 max_ltim = pb->max_mingnt * 33 / 4; /* cvt to cycle count */ 866 band = 40000000; /* 0.25us cycles/sec */ 867 if (band < pb->bandwidth_used) { 868 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 869 pb->busno); 870 def_ltim = -1; 871 } else { 872 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 873 if (def_ltim > pb->min_maxlat) 874 def_ltim = pb->min_maxlat; 875 def_ltim = def_ltim * 33 / 4; 876 } 877 def_ltim = (def_ltim + 7) & ~7; 878 max_ltim = (max_ltim + 7) & ~7; 879 880 pb->def_ltim = MIN( def_ltim, 255 ); 881 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 882 883 /* 884 * Now we have what we need to initialize the devices. 885 * It would probably be better if we could allocate all of these 886 * for all busses at once, but "not right now". First, get a list 887 * of free memory ranges from the m.d. system. 888 */ 889 if (setup_iowins(pb) || setup_memwins(pb)) { 890 printf("PCI bus configuration failed: "); 891 printf("unable to assign all I/O and memory ranges."); 892 return -1; 893 } 894 895 /* 896 * Configure the latency for the devices, and enable them. 897 */ 898 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 899 pcireg_t cmd, class, misc; 900 int ltim; 901 902 if (pci_conf_debug) { 903 print_tag(pd->pc, pd->tag); 904 printf("Configuring device.\n"); 905 } 906 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 907 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 908 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 909 cmd |= PCI_COMMAND_MASTER_ENABLE 910 | PCI_COMMAND_SERR_ENABLE 911 | PCI_COMMAND_PARITY_ENABLE; 912 if (pb->fast_b2b) 913 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 914 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 915 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 916 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 917 ltim = pd->min_gnt * 33 / 4; 918 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 919 } else { 920 ltim = MIN (pb->def_ltim, pb->max_ltim); 921 } 922 if (!pd->enable) { 923 print_tag(pd->pc, pd->tag); 924 printf("Disabled due to lack of resources.\n"); 925 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 926 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 927 } 928 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 929 930 misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) 931 | ((ltim & 0xff) << PCI_LATTIMER_SHIFT); 932 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 933 934 if (pd->ppb) { 935 if (configure_bridge(pd) < 0) 936 return -1; 937 continue; 938 } 939 } 940 941 if (pci_conf_debug) { 942 printf("PCI bus %d configured\n", pb->busno); 943 } 944 945 return 0; 946 } 947 948 /* 949 * Let's configure the PCI bus. 950 * This consists of basically scanning for all existing devices, 951 * identifying their needs, and then making another pass over them 952 * to set: 953 * 1. I/O addresses 954 * 2. Memory addresses (Prefetchable and not) 955 * 3. PCI command register 956 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 957 * Header type, Latency timer, Cache line size) register 958 * 959 * The command register is set to enable fast back-to-back transactions 960 * if the host bridge says it can handle it. We also configure 961 * Master Enable, SERR enable, parity enable, and (if this is not a 962 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 963 * will not report some I/O space. 964 * 965 * The latency is computed to be a "fair share" of the bus bandwidth. 966 * The bus bandwidth variable is initialized to the number of PCI cycles 967 * in one second. The number of cycles taken for one transaction by each 968 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 969 * Care is taken to ensure that the latency timer won't be set such that 970 * it would exceed the critical time for any device. 971 * 972 * This is complicated somewhat due to the presence of bridges. PCI-PCI 973 * bridges are probed and configured recursively. 974 */ 975 int 976 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 977 struct extent *memext, struct extent *pmemext) 978 { 979 pciconf_bus_t *pb; 980 int rv; 981 982 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 983 pb->busno = 0; 984 pb->busno_spacing = PCI_BUSNO_SPACING; 985 pb->next_busno = pb->busno + 1; 986 pb->last_busno = 255; 987 pb->parent_bus = NULL; 988 pb->swiz = 0; 989 pb->io_32bit = 1; 990 pb->pmem_64bit = 0; 991 pb->ioext = ioext; 992 pb->memext = memext; 993 if (pmemext == NULL) { 994 pb->pmemext = memext; 995 } else { 996 pb->pmemext = pmemext; 997 } 998 pb->pc = pc; 999 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1000 1001 rv = probe_bus(pb); 1002 if (rv == 0) { 1003 rv = configure_bus(pb); 1004 } 1005 1006 /* 1007 * All done! 1008 */ 1009 free(pb, M_DEVBUF); 1010 return rv; 1011 } 1012
Indexes created Wed Sep 24 02:09:48 GMT 2025