pciconf.c revision 1.42
1 /* $NetBSD: pciconf.c,v 1.42 2019/10/01 18:00:08 chs Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.42 2019/10/01 18:00:08 chs Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 #include <sys/kmem.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pciconf.h> 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pccbbreg.h> 83 84 int pci_conf_debug = 0; 85 86 #if !defined(MIN) 87 #define MIN(a,b) (((a)<(b))?(a):(b)) 88 #define MAX(a,b) (((a)>(b))?(a):(b)) 89 #endif 90 91 /* per-bus constants. */ 92 #define MAX_CONF_DEV 32 /* Arbitrary */ 93 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 94 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 95 96 struct _s_pciconf_bus_t; /* Forward declaration */ 97 98 typedef struct _s_pciconf_dev_t { 99 int ipin; 100 int iline; 101 int min_gnt; 102 int max_lat; 103 int enable; 104 pcitag_t tag; 105 pci_chipset_tag_t pc; 106 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 107 } pciconf_dev_t; 108 109 typedef struct _s_pciconf_win_t { 110 pciconf_dev_t *dev; 111 int reg; /* 0 for busses */ 112 int align; 113 int prefetch; 114 uint64_t size; 115 uint64_t address; 116 } pciconf_win_t; 117 118 typedef struct _s_pciconf_bus_t { 119 int busno; 120 int next_busno; 121 int last_busno; 122 int max_mingnt; 123 int min_maxlat; 124 int cacheline_size; 125 int prefetch; 126 int fast_b2b; 127 int freq_66; 128 int def_ltim; 129 int max_ltim; 130 int bandwidth_used; 131 int swiz; 132 int io_32bit; 133 int pmem_64bit; 134 int io_align; 135 int mem_align; 136 int pmem_align; 137 138 int ndevs; 139 pciconf_dev_t device[MAX_CONF_DEV]; 140 141 /* These should be sorted in order of decreasing size */ 142 int nmemwin; 143 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 144 int niowin; 145 pciconf_win_t pciiowin[MAX_CONF_IO]; 146 147 bus_size_t io_total; 148 bus_size_t mem_total; 149 bus_size_t pmem_total; 150 151 struct extent *ioext; 152 struct extent *memext; 153 struct extent *pmemext; 154 155 pci_chipset_tag_t pc; 156 struct _s_pciconf_bus_t *parent_bus; 157 } pciconf_bus_t; 158 159 static int probe_bus(pciconf_bus_t *); 160 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 161 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 162 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 163 static int setup_iowins(pciconf_bus_t *); 164 static int setup_memwins(pciconf_bus_t *); 165 static int configure_bridge(pciconf_dev_t *); 166 static int configure_bus(pciconf_bus_t *); 167 static uint64_t pci_allocate_range(struct extent *, uint64_t, int); 168 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 169 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 170 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 171 172 static void print_tag(pci_chipset_tag_t, pcitag_t); 173 174 static void 175 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 176 { 177 int bus, dev, func; 178 179 pci_decompose_tag(pc, tag, &bus, &dev, &func); 180 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 181 } 182 183 /************************************************************************/ 184 /************************************************************************/ 185 /*********************** Bus probing routines ***********************/ 186 /************************************************************************/ 187 /************************************************************************/ 188 static pciconf_win_t * 189 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 190 { 191 int i, n; 192 193 n = pb->niowin; 194 for (i = n; i > 0 && size > pb->pciiowin[i-1].size; i--) 195 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 196 return &pb->pciiowin[i]; 197 } 198 199 static pciconf_win_t * 200 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 201 { 202 int i, n; 203 204 n = pb->nmemwin; 205 for (i = n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 206 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 207 return &pb->pcimemwin[i]; 208 } 209 210 /* 211 * Set up bus common stuff, then loop over devices & functions. 212 * If we find something, call pci_do_device_query()). 213 */ 214 static int 215 probe_bus(pciconf_bus_t *pb) 216 { 217 int device; 218 uint8_t devs[32]; 219 int i, n; 220 221 pb->ndevs = 0; 222 pb->niowin = 0; 223 pb->nmemwin = 0; 224 pb->freq_66 = 1; 225 #ifdef PCICONF_NO_FAST_B2B 226 pb->fast_b2b = 0; 227 #else 228 pb->fast_b2b = 1; 229 #endif 230 pb->prefetch = 1; 231 pb->max_mingnt = 0; /* we are looking for the maximum */ 232 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 233 pb->bandwidth_used = 0; 234 235 n = pci_bus_devorder(pb->pc, pb->busno, devs, __arraycount(devs)); 236 for (i = 0; i < n; i++) { 237 pcitag_t tag; 238 pcireg_t id, bhlcr; 239 int function, nfunction; 240 int confmode; 241 242 device = devs[i]; 243 244 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 245 if (pci_conf_debug) { 246 print_tag(pb->pc, tag); 247 } 248 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 249 250 if (pci_conf_debug) { 251 printf("id=%x: Vendor=%x, Product=%x\n", 252 id, PCI_VENDOR(id), PCI_PRODUCT(id)); 253 } 254 /* Invalid vendor ID value? */ 255 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 256 continue; 257 258 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 259 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 260 for (function = 0; function < nfunction; function++) { 261 tag = pci_make_tag(pb->pc, pb->busno, device, function); 262 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 263 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 264 continue; 265 if (pb->ndevs + 1 < MAX_CONF_DEV) { 266 if (pci_conf_debug) { 267 print_tag(pb->pc, tag); 268 printf("Found dev 0x%04x 0x%04x -- " 269 "really probing.\n", 270 PCI_VENDOR(id), PCI_PRODUCT(id)); 271 } 272 #ifdef __HAVE_PCI_CONF_HOOK 273 confmode = pci_conf_hook(pb->pc, pb->busno, 274 device, function, id); 275 if (confmode == 0) 276 continue; 277 #else 278 /* 279 * Don't enable expansion ROMS -- some cards 280 * share address decoders between the EXPROM 281 * and PCI memory space, and enabling the ROM 282 * when not needed will cause all sorts of 283 * lossage. 284 */ 285 confmode = PCI_CONF_DEFAULT; 286 #endif 287 if (pci_do_device_query(pb, tag, device, 288 function, confmode)) 289 return -1; 290 pb->ndevs++; 291 } 292 } 293 } 294 return 0; 295 } 296 297 static void 298 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 299 { 300 pb->busno = parent->next_busno; 301 pb->next_busno = pb->busno + 1; 302 } 303 304 static void 305 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 306 { 307 pcireg_t busreg; 308 309 busreg = __SHIFTIN(prim, PCI_BRIDGE_BUS_PRIMARY); 310 busreg |= __SHIFTIN(sec, PCI_BRIDGE_BUS_SECONDARY); 311 busreg |= __SHIFTIN(sub, PCI_BRIDGE_BUS_SUBORDINATE); 312 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 313 } 314 315 static pciconf_bus_t * 316 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 317 { 318 pciconf_bus_t *pb; 319 pcireg_t io, pmem; 320 pciconf_win_t *pi, *pm; 321 322 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_SLEEP); 323 pb->cacheline_size = parent->cacheline_size; 324 pb->parent_bus = parent; 325 alloc_busno(parent, pb); 326 327 pb->mem_align = 0x100000; /* 1M alignment */ 328 pb->pmem_align = 0x100000; /* 1M alignment */ 329 pb->io_align = 0x1000; /* 4K alignment */ 330 331 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 332 333 pb->swiz = parent->swiz + dev; 334 335 pb->ioext = NULL; 336 pb->memext = NULL; 337 pb->pmemext = NULL; 338 pb->pc = parent->pc; 339 pb->io_total = pb->mem_total = pb->pmem_total = 0; 340 341 pb->io_32bit = 0; 342 if (parent->io_32bit) { 343 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 344 if (PCI_BRIDGE_IO_32BITS(io)) 345 pb->io_32bit = 1; 346 } 347 348 pb->pmem_64bit = 0; 349 if (parent->pmem_64bit) { 350 pmem = pci_conf_read(parent->pc, pd->tag, 351 PCI_BRIDGE_PREFETCHMEM_REG); 352 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) 353 pb->pmem_64bit = 1; 354 } 355 356 if (probe_bus(pb)) { 357 printf("Failed to probe bus %d\n", pb->busno); 358 goto err; 359 } 360 361 /* We have found all subordinate busses now, reprogram busreg. */ 362 pb->last_busno = pb->next_busno - 1; 363 parent->next_busno = pb->next_busno; 364 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 365 pb->last_busno); 366 if (pci_conf_debug) 367 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 368 parent->busno, pb->busno, pb->last_busno); 369 370 if (pb->io_total > 0) { 371 if (parent->niowin >= MAX_CONF_IO) { 372 printf("pciconf: too many (%d) I/O windows\n", 373 parent->niowin); 374 goto err; 375 } 376 pb->io_total |= pb->io_align - 1; /* Round up */ 377 pi = get_io_desc(parent, pb->io_total); 378 pi->dev = pd; 379 pi->reg = 0; 380 pi->size = pb->io_total; 381 pi->align = pb->io_align; /* 4K min alignment */ 382 if (parent->io_align < pb->io_align) 383 parent->io_align = pb->io_align; 384 pi->prefetch = 0; 385 parent->niowin++; 386 parent->io_total += pb->io_total; 387 } 388 389 if (pb->mem_total > 0) { 390 if (parent->nmemwin >= MAX_CONF_MEM) { 391 printf("pciconf: too many (%d) MEM windows\n", 392 parent->nmemwin); 393 goto err; 394 } 395 pb->mem_total |= pb->mem_align - 1; /* Round up */ 396 pm = get_mem_desc(parent, pb->mem_total); 397 pm->dev = pd; 398 pm->reg = 0; 399 pm->size = pb->mem_total; 400 pm->align = pb->mem_align; /* 1M min alignment */ 401 if (parent->mem_align < pb->mem_align) 402 parent->mem_align = pb->mem_align; 403 pm->prefetch = 0; 404 parent->nmemwin++; 405 parent->mem_total += pb->mem_total; 406 } 407 408 if (pb->pmem_total > 0) { 409 if (parent->nmemwin >= MAX_CONF_MEM) { 410 printf("pciconf: too many MEM windows\n"); 411 goto err; 412 } 413 pb->pmem_total |= pb->pmem_align - 1; /* Round up */ 414 pm = get_mem_desc(parent, pb->pmem_total); 415 pm->dev = pd; 416 pm->reg = 0; 417 pm->size = pb->pmem_total; 418 pm->align = pb->pmem_align; /* 1M alignment */ 419 if (parent->pmem_align < pb->pmem_align) 420 parent->pmem_align = pb->pmem_align; 421 pm->prefetch = 1; 422 parent->nmemwin++; 423 parent->pmem_total += pb->pmem_total; 424 } 425 426 return pb; 427 err: 428 kmem_free(pb, sizeof(*pb)); 429 return NULL; 430 } 431 432 static int 433 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, 434 int mode) 435 { 436 pciconf_dev_t *pd; 437 pciconf_win_t *pi, *pm; 438 pcireg_t classreg, cmd, icr, bhlc, bar, mask, bar64, mask64, 439 busreg; 440 uint64_t size; 441 int br, width, reg_start, reg_end; 442 443 pd = &pb->device[pb->ndevs]; 444 pd->pc = pb->pc; 445 pd->tag = tag; 446 pd->ppb = NULL; 447 pd->enable = mode; 448 449 classreg = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 450 451 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 452 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 453 454 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE 455 && PCI_HDRTYPE_TYPE(bhlc) != PCI_HDRTYPE_PPB) { 456 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 457 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 458 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 459 } else if (pci_conf_debug) { 460 print_tag(pb->pc, tag); 461 printf("device is a bridge; not clearing enables\n"); 462 } 463 464 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 465 pb->fast_b2b = 0; 466 467 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 468 pb->freq_66 = 0; 469 470 switch (PCI_HDRTYPE_TYPE(bhlc)) { 471 case PCI_HDRTYPE_DEVICE: 472 reg_start = PCI_MAPREG_START; 473 reg_end = PCI_MAPREG_END; 474 break; 475 case PCI_HDRTYPE_PPB: 476 pd->ppb = query_bus(pb, pd, dev); 477 if (pd->ppb == NULL) 478 return -1; 479 return 0; 480 case PCI_HDRTYPE_PCB: 481 reg_start = PCI_MAPREG_START; 482 reg_end = PCI_MAPREG_PCB_END; 483 484 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 485 busreg = (busreg & 0xff000000) | 486 __SHIFTIN(pb->busno, PCI_BRIDGE_BUS_PRIMARY) | 487 __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SECONDARY) | 488 __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SUBORDINATE); 489 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 490 491 pb->next_busno++; 492 break; 493 default: 494 return -1; 495 } 496 497 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 498 pd->ipin = PCI_INTERRUPT_PIN(icr); 499 pd->iline = PCI_INTERRUPT_LINE(icr); 500 pd->min_gnt = PCI_MIN_GNT(icr); 501 pd->max_lat = PCI_MAX_LAT(icr); 502 if (pd->iline || pd->ipin) { 503 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 504 &pd->iline); 505 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 506 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 507 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 508 } 509 510 if (pd->min_gnt != 0 || pd->max_lat != 0) { 511 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 512 pb->max_mingnt = pd->min_gnt; 513 514 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 515 pb->min_maxlat = pd->max_lat; 516 517 pb->bandwidth_used += pd->min_gnt * 4000000 / 518 (pd->min_gnt + pd->max_lat); 519 } 520 521 width = 4; 522 for (br = reg_start; br < reg_end; br += width) { 523 #if 0 524 /* XXX Should only ignore if IDE not in legacy mode? */ 525 if (PCI_CLASS(classreg) == PCI_CLASS_MASS_STORAGE && 526 PCI_SUBCLASS(classreg) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 527 break; 528 } 529 #endif 530 bar = pci_conf_read(pb->pc, tag, br); 531 pci_conf_write(pb->pc, tag, br, 0xffffffff); 532 mask = pci_conf_read(pb->pc, tag, br); 533 pci_conf_write(pb->pc, tag, br, bar); 534 width = 4; 535 536 if ( (mode & PCI_CONF_MAP_IO) 537 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 538 /* 539 * Upper 16 bits must be one. Devices may hardwire 540 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 541 */ 542 mask |= 0xffff0000; 543 544 size = PCI_MAPREG_IO_SIZE(mask); 545 if (size == 0) { 546 if (pci_conf_debug) { 547 print_tag(pb->pc, tag); 548 printf("I/O BAR 0x%x is void\n", br); 549 } 550 continue; 551 } 552 553 if (pb->niowin >= MAX_CONF_IO) { 554 printf("pciconf: too many I/O windows\n"); 555 return -1; 556 } 557 558 pi = get_io_desc(pb, size); 559 pi->dev = pd; 560 pi->reg = br; 561 pi->size = (uint64_t) size; 562 pi->align = 4; 563 if (pb->io_align < pi->size) 564 pb->io_align = pi->size; 565 pi->prefetch = 0; 566 if (pci_conf_debug) { 567 print_tag(pb->pc, tag); 568 printf("Register 0x%x, I/O size %" PRIu64 "\n", 569 br, pi->size); 570 } 571 pb->niowin++; 572 pb->io_total += size; 573 } else if ((mode & PCI_CONF_MAP_MEM) 574 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 575 switch (PCI_MAPREG_MEM_TYPE(mask)) { 576 case PCI_MAPREG_MEM_TYPE_32BIT: 577 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 578 size = (uint64_t) PCI_MAPREG_MEM_SIZE(mask); 579 break; 580 case PCI_MAPREG_MEM_TYPE_64BIT: 581 bar64 = pci_conf_read(pb->pc, tag, br + 4); 582 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 583 mask64 = pci_conf_read(pb->pc, tag, br + 4); 584 pci_conf_write(pb->pc, tag, br + 4, bar64); 585 size = (uint64_t) PCI_MAPREG_MEM64_SIZE( 586 (((uint64_t) mask64) << 32) | mask); 587 width = 8; 588 break; 589 default: 590 print_tag(pb->pc, tag); 591 printf("reserved mapping type 0x%x\n", 592 PCI_MAPREG_MEM_TYPE(mask)); 593 continue; 594 } 595 596 if (size == 0) { 597 if (pci_conf_debug) { 598 print_tag(pb->pc, tag); 599 printf("MEM%d BAR 0x%x is void\n", 600 PCI_MAPREG_MEM_TYPE(mask) == 601 PCI_MAPREG_MEM_TYPE_64BIT ? 602 64 : 32, br); 603 } 604 continue; 605 } else { 606 if (pci_conf_debug) { 607 print_tag(pb->pc, tag); 608 printf("MEM%d BAR 0x%x has size %#lx\n", 609 PCI_MAPREG_MEM_TYPE(mask) == 610 PCI_MAPREG_MEM_TYPE_64BIT ? 611 64 : 32, br, (unsigned long)size); 612 } 613 } 614 615 if (pb->nmemwin >= MAX_CONF_MEM) { 616 printf("pciconf: too many memory windows\n"); 617 return -1; 618 } 619 620 pm = get_mem_desc(pb, size); 621 pm->dev = pd; 622 pm->reg = br; 623 pm->size = size; 624 pm->align = 4; 625 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 626 if (pci_conf_debug) { 627 print_tag(pb->pc, tag); 628 printf("Register 0x%x, memory size %" 629 PRIu64 "\n", br, pm->size); 630 } 631 pb->nmemwin++; 632 if (pm->prefetch) { 633 pb->pmem_total += size; 634 if (pb->pmem_align < pm->size) 635 pb->pmem_align = pm->size; 636 } else { 637 pb->mem_total += size; 638 if (pb->mem_align < pm->size) 639 pb->mem_align = pm->size; 640 } 641 } 642 } 643 644 if (mode & PCI_CONF_MAP_ROM) { 645 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 646 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 647 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 648 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 649 650 if (mask != 0 && mask != 0xffffffff) { 651 if (pb->nmemwin >= MAX_CONF_MEM) { 652 printf("pciconf: too many memory windows\n"); 653 return -1; 654 } 655 size = (uint64_t) PCI_MAPREG_MEM_SIZE(mask); 656 657 pm = get_mem_desc(pb, size); 658 pm->dev = pd; 659 pm->reg = PCI_MAPREG_ROM; 660 pm->size = size; 661 pm->align = 4; 662 pm->prefetch = 1; 663 if (pci_conf_debug) { 664 print_tag(pb->pc, tag); 665 printf("Expansion ROM memory size %" 666 PRIu64 "\n", pm->size); 667 } 668 pb->nmemwin++; 669 pb->pmem_total += size; 670 } 671 } else { 672 /* Don't enable ROMs if we aren't going to map them. */ 673 mode &= ~PCI_CONF_ENABLE_ROM; 674 pd->enable &= ~PCI_CONF_ENABLE_ROM; 675 } 676 677 if (!(mode & PCI_CONF_ENABLE_ROM)) { 678 /* Ensure ROM is disabled */ 679 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 680 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 681 bar & ~PCI_MAPREG_ROM_ENABLE); 682 } 683 684 return 0; 685 } 686 687 /************************************************************************/ 688 /************************************************************************/ 689 /******************** Bus configuration routines ********************/ 690 /************************************************************************/ 691 /************************************************************************/ 692 static uint64_t 693 pci_allocate_range(struct extent *ex, uint64_t amt, int align) 694 { 695 int r; 696 u_long addr; 697 698 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 699 if (r) { 700 printf("extent_alloc(%p, %#" PRIx64 ", %#x) returned %d\n", 701 ex, amt, align, r); 702 extent_print(ex); 703 return ~0ULL; 704 } 705 return addr; 706 } 707 708 static int 709 setup_iowins(pciconf_bus_t *pb) 710 { 711 pciconf_win_t *pi; 712 pciconf_dev_t *pd; 713 714 for (pi = pb->pciiowin; pi < &pb->pciiowin[pb->niowin]; pi++) { 715 if (pi->size == 0) 716 continue; 717 718 pd = pi->dev; 719 pi->address = pci_allocate_range(pb->ioext, pi->size, 720 pi->align); 721 if (~pi->address == 0) { 722 print_tag(pd->pc, pd->tag); 723 printf("Failed to allocate PCI I/O space (%" 724 PRIu64 " req)\n", pi->size); 725 return -1; 726 } 727 if (pd->ppb && pi->reg == 0) { 728 pd->ppb->ioext = extent_create("pciconf", pi->address, 729 pi->address + pi->size, NULL, 0, 730 EX_NOWAIT); 731 if (pd->ppb->ioext == NULL) { 732 print_tag(pd->pc, pd->tag); 733 printf("Failed to alloc I/O ext. for bus %d\n", 734 pd->ppb->busno); 735 return -1; 736 } 737 continue; 738 } 739 if (!pb->io_32bit && pi->address > 0xFFFF) { 740 pi->address = 0; 741 pd->enable &= ~PCI_CONF_ENABLE_IO; 742 } else { 743 pd->enable |= PCI_CONF_ENABLE_IO; 744 } 745 if (pci_conf_debug) { 746 print_tag(pd->pc, pd->tag); 747 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 748 " (reg %x)\n", pi->size, pi->address, pi->reg); 749 } 750 pci_conf_write(pd->pc, pd->tag, pi->reg, 751 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 752 } 753 return 0; 754 } 755 756 static int 757 setup_memwins(pciconf_bus_t *pb) 758 { 759 pciconf_win_t *pm; 760 pciconf_dev_t *pd; 761 pcireg_t base; 762 struct extent *ex; 763 764 for (pm = pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin]; pm++) { 765 if (pm->size == 0) 766 continue; 767 768 pd = pm->dev; 769 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 770 pm->address = pci_allocate_range(ex, pm->size, pm->align); 771 if (~pm->address == 0) { 772 print_tag(pd->pc, pd->tag); 773 printf( 774 "Failed to allocate PCI memory space (%" PRIu64 775 " req)\n", pm->size); 776 return -1; 777 } 778 if (pd->ppb && pm->reg == 0) { 779 ex = extent_create("pciconf", pm->address, 780 pm->address + pm->size, NULL, 0, EX_NOWAIT); 781 if (ex == NULL) { 782 print_tag(pd->pc, pd->tag); 783 printf("Failed to alloc MEM ext. for bus %d\n", 784 pd->ppb->busno); 785 return -1; 786 } 787 if (pm->prefetch) 788 pd->ppb->pmemext = ex; 789 else 790 pd->ppb->memext = ex; 791 792 continue; 793 } 794 if (pm->prefetch && !pb->pmem_64bit && 795 pm->address > 0xFFFFFFFFULL) { 796 pm->address = 0; 797 pd->enable &= ~PCI_CONF_ENABLE_MEM; 798 } else 799 pd->enable |= PCI_CONF_ENABLE_MEM; 800 801 if (pm->reg != PCI_MAPREG_ROM) { 802 if (pci_conf_debug) { 803 print_tag(pd->pc, pd->tag); 804 printf( 805 "Putting %" PRIu64 " MEM bytes @ %#" 806 PRIx64 " (reg %x)\n", pm->size, 807 pm->address, pm->reg); 808 } 809 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 810 base = PCI_MAPREG_MEM_ADDR(pm->address) | 811 PCI_MAPREG_MEM_TYPE(base); 812 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 813 if (PCI_MAPREG_MEM_TYPE(base) == 814 PCI_MAPREG_MEM_TYPE_64BIT) { 815 base = (pcireg_t) 816 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 817 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 818 base); 819 } 820 } 821 } 822 for (pm = pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin]; pm++) { 823 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 824 pd = pm->dev; 825 if (!(pd->enable & PCI_CONF_MAP_ROM)) 826 continue; 827 if (pci_conf_debug) { 828 print_tag(pd->pc, pd->tag); 829 printf( 830 "Putting %" PRIu64 " ROM bytes @ %#" 831 PRIx64 " (reg %x)\n", pm->size, 832 pm->address, pm->reg); 833 } 834 base = (pcireg_t) pm->address; 835 if (pd->enable & PCI_CONF_ENABLE_ROM) 836 base |= PCI_MAPREG_ROM_ENABLE; 837 838 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 839 } 840 } 841 return 0; 842 } 843 844 /* 845 * Configure I/O, memory, and prefetcable memory spaces, then make 846 * a call to configure_bus(). 847 */ 848 static int 849 configure_bridge(pciconf_dev_t *pd) 850 { 851 unsigned long io_base, io_limit, mem_base, mem_limit; 852 pciconf_bus_t *pb; 853 pcireg_t io, iohigh, mem, cmd; 854 int rv; 855 bool isprefetchmem64; 856 857 pb = pd->ppb; 858 /* Configure I/O base & limit*/ 859 if (pb->ioext) { 860 io_base = pb->ioext->ex_start; 861 io_limit = pb->ioext->ex_end; 862 } else { 863 io_base = 0x1000; /* 4K */ 864 io_limit = 0x0000; 865 } 866 if (pb->io_32bit) { 867 iohigh = __SHIFTIN(io_base >> 16, PCI_BRIDGE_IOHIGH_BASE) | 868 __SHIFTIN(io_limit >> 16, PCI_BRIDGE_IOHIGH_LIMIT); 869 } else { 870 if (io_limit > 0xFFFF) { 871 printf("Bus %d bridge does not support 32-bit I/O. ", 872 pb->busno); 873 printf("Disabling I/O accesses\n"); 874 io_base = 0x1000; /* 4K */ 875 io_limit = 0x0000; 876 } 877 iohigh = 0; 878 } 879 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 880 PCI_BRIDGE_STATIO_STATUS; 881 io |= __SHIFTIN((io_base >> 8) & PCI_BRIDGE_STATIO_IOADDR, 882 PCI_BRIDGE_STATIO_IOBASE); 883 io |= __SHIFTIN((io_limit >> 8) & PCI_BRIDGE_STATIO_IOADDR, 884 PCI_BRIDGE_STATIO_IOLIMIT); 885 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 886 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 887 888 /* Configure mem base & limit */ 889 if (pb->memext) { 890 mem_base = pb->memext->ex_start; 891 mem_limit = pb->memext->ex_end; 892 } else { 893 mem_base = 0x100000; /* 1M */ 894 mem_limit = 0x000000; 895 } 896 #if ULONG_MAX > 0xffffffff 897 if (mem_limit > 0xFFFFFFFFULL) { 898 printf("Bus %d bridge MEM range out of range. ", pb->busno); 899 printf("Disabling MEM accesses\n"); 900 mem_base = 0x100000; /* 1M */ 901 mem_limit = 0x000000; 902 } 903 #endif 904 mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_MEMORY_ADDR, 905 PCI_BRIDGE_MEMORY_BASE); 906 mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_MEMORY_ADDR, 907 PCI_BRIDGE_MEMORY_LIMIT); 908 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 909 910 /* Configure prefetchable mem base & limit */ 911 if (pb->pmemext) { 912 mem_base = pb->pmemext->ex_start; 913 mem_limit = pb->pmemext->ex_end; 914 } else { 915 mem_base = 0x100000; /* 1M */ 916 mem_limit = 0x000000; 917 } 918 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 919 isprefetchmem64 = PCI_BRIDGE_PREFETCHMEM_64BITS(mem); 920 #if ULONG_MAX > 0xffffffff 921 if (!isprefetchmem64 && mem_limit > 0xFFFFFFFFULL) { 922 printf("Bus %d bridge does not support 64-bit PMEM. ", 923 pb->busno); 924 printf("Disabling prefetchable-MEM accesses\n"); 925 mem_base = 0x100000; /* 1M */ 926 mem_limit = 0x000000; 927 } 928 #endif 929 mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR, 930 PCI_BRIDGE_PREFETCHMEM_BASE); 931 mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR, 932 PCI_BRIDGE_PREFETCHMEM_LIMIT); 933 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 934 /* 935 * XXX -- 64-bit systems need a lot more than just this... 936 */ 937 if (isprefetchmem64) { 938 mem_base = (uint64_t)mem_base >> 32; 939 mem_limit = (uint64_t)mem_limit >> 32; 940 pci_conf_write(pb->pc, pd->tag, 941 PCI_BRIDGE_PREFETCHBASEUP32_REG, mem_base & 0xffffffff); 942 pci_conf_write(pb->pc, pd->tag, 943 PCI_BRIDGE_PREFETCHLIMITUP32_REG, mem_limit & 0xffffffff); 944 } 945 946 rv = configure_bus(pb); 947 948 if (pb->ioext) 949 extent_destroy(pb->ioext); 950 if (pb->memext) 951 extent_destroy(pb->memext); 952 if (pb->pmemext) 953 extent_destroy(pb->pmemext); 954 if (rv == 0) { 955 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 956 cmd &= ~PCI_BRIDGE_CONTROL; /* Clear control bit first */ 957 cmd |= PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR; 958 if (pb->fast_b2b) 959 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B; 960 961 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 962 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 963 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 964 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 965 } 966 967 return rv; 968 } 969 970 /* 971 * Calculate latency values, allocate I/O and MEM segments, then set them 972 * up. If a PCI-PCI bridge is found, configure the bridge separately, 973 * which will cause a recursive call back here. 974 */ 975 static int 976 configure_bus(pciconf_bus_t *pb) 977 { 978 pciconf_dev_t *pd; 979 int def_ltim, max_ltim, band, bus_mhz; 980 981 if (pb->ndevs == 0) { 982 if (pci_conf_debug) 983 printf("PCI bus %d - no devices\n", pb->busno); 984 return 1; 985 } 986 bus_mhz = pb->freq_66 ? 66 : 33; 987 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 988 band = 4000000; /* 0.25us cycles/sec */ 989 if (band < pb->bandwidth_used) { 990 printf("PCI bus %d: Warning: Total bandwidth exceeded!? (%d)\n", 991 pb->busno, pb->bandwidth_used); 992 def_ltim = -1; 993 } else { 994 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 995 if (def_ltim > pb->min_maxlat) 996 def_ltim = pb->min_maxlat; 997 def_ltim = def_ltim * bus_mhz / 4; 998 } 999 def_ltim = (def_ltim + 7) & ~7; 1000 max_ltim = (max_ltim + 7) & ~7; 1001 1002 pb->def_ltim = MIN( def_ltim, 255 ); 1003 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 1004 1005 /* 1006 * Now we have what we need to initialize the devices. 1007 * It would probably be better if we could allocate all of these 1008 * for all busses at once, but "not right now". First, get a list 1009 * of free memory ranges from the m.d. system. 1010 */ 1011 if (setup_iowins(pb) || setup_memwins(pb)) { 1012 printf("PCI bus configuration failed: " 1013 "unable to assign all I/O and memory ranges.\n"); 1014 return -1; 1015 } 1016 1017 /* 1018 * Configure the latency for the devices, and enable them. 1019 */ 1020 for (pd = pb->device; pd < &pb->device[pb->ndevs]; pd++) { 1021 pcireg_t cmd, classreg, misc; 1022 int ltim; 1023 1024 if (pci_conf_debug) { 1025 print_tag(pd->pc, pd->tag); 1026 printf("Configuring device.\n"); 1027 } 1028 classreg = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1029 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1030 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1031 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1032 cmd |= PCI_COMMAND_PARITY_ENABLE; 1033 if (pd->enable & PCI_CONF_ENABLE_SERR) 1034 cmd |= PCI_COMMAND_SERR_ENABLE; 1035 if (pb->fast_b2b) 1036 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1037 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE || 1038 PCI_SUBCLASS(classreg) != PCI_SUBCLASS_BRIDGE_PCI) { 1039 if (pd->enable & PCI_CONF_ENABLE_IO) 1040 cmd |= PCI_COMMAND_IO_ENABLE; 1041 if (pd->enable & PCI_CONF_ENABLE_MEM) 1042 cmd |= PCI_COMMAND_MEM_ENABLE; 1043 if (pd->enable & PCI_CONF_ENABLE_BM) 1044 cmd |= PCI_COMMAND_MASTER_ENABLE; 1045 ltim = pd->min_gnt * bus_mhz / 4; 1046 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1047 } else { 1048 cmd |= PCI_COMMAND_MASTER_ENABLE; 1049 ltim = MIN (pb->def_ltim, pb->max_ltim); 1050 } 1051 if ((pd->enable & 1052 (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) { 1053 print_tag(pd->pc, pd->tag); 1054 printf("Disabled due to lack of resources.\n"); 1055 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1056 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1057 } 1058 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1059 1060 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1061 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1062 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1063 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1064 PCI_CACHELINE_SHIFT; 1065 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1066 1067 if (pd->ppb) { 1068 if (configure_bridge(pd) < 0) 1069 return -1; 1070 continue; 1071 } 1072 } 1073 1074 if (pci_conf_debug) 1075 printf("PCI bus %d configured\n", pb->busno); 1076 1077 return 0; 1078 } 1079 1080 /* 1081 * Let's configure the PCI bus. 1082 * This consists of basically scanning for all existing devices, 1083 * identifying their needs, and then making another pass over them 1084 * to set: 1085 * 1. I/O addresses 1086 * 2. Memory addresses (Prefetchable and not) 1087 * 3. PCI command register 1088 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1089 * Header type, Latency timer, Cache line size) register 1090 * 1091 * The command register is set to enable fast back-to-back transactions 1092 * if the host bridge says it can handle it. We also configure 1093 * Master Enable, SERR enable, parity enable, and (if this is not a 1094 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1095 * will not report some I/O space. 1096 * 1097 * The latency is computed to be a "fair share" of the bus bandwidth. 1098 * The bus bandwidth variable is initialized to the number of PCI cycles 1099 * in one second. The number of cycles taken for one transaction by each 1100 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1101 * Care is taken to ensure that the latency timer won't be set such that 1102 * it would exceed the critical time for any device. 1103 * 1104 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1105 * bridges are probed and configured recursively. 1106 */ 1107 int 1108 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1109 struct extent *memext, struct extent *pmemext, int firstbus, 1110 int cacheline_size) 1111 { 1112 pciconf_bus_t *pb; 1113 int rv; 1114 1115 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_SLEEP); 1116 pb->busno = firstbus; 1117 pb->next_busno = pb->busno + 1; 1118 pb->last_busno = 255; 1119 pb->cacheline_size = cacheline_size; 1120 pb->parent_bus = NULL; 1121 pb->swiz = 0; 1122 pb->io_32bit = 1; 1123 pb->pmem_64bit = 0; 1124 pb->ioext = ioext; 1125 pb->memext = memext; 1126 if (pmemext == NULL) 1127 pb->pmemext = memext; 1128 else 1129 pb->pmemext = pmemext; 1130 1131 pb->pc = pc; 1132 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1133 1134 rv = probe_bus(pb); 1135 pb->last_busno = pb->next_busno - 1; 1136 if (rv == 0) 1137 rv = configure_bus(pb); 1138 1139 /* 1140 * All done! 1141 */ 1142 kmem_free(pb, sizeof(*pb)); 1143 return rv; 1144 } 1145
Indexes created Thu Sep 25 16:09:42 GMT 2025