pciconf.c revision 1.7
1 /* $NetBSD: pciconf.c,v 1.7 2001/08/28 15:13:48 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Do this in 2 passes, with an MD hook to control the behavior: 44 * (1) Configure the bus (possibly including expansion 45 * ROMs. 46 * (2) Another pass to disable expansion ROMs if they're 47 * mapped (since you're not supposed to leave them 48 * mapped when you're not using them). 49 * This would facilitate MD code executing the expansion ROMs 50 * if necessary (possibly with an x86 emulator) to configure 51 * devices (e.g. VGA cards). 52 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 53 * information around & be able to reconfigure on the fly. 54 * - Deal with segments (See IA64 System Abstraction Layer) 55 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 56 * - Deal with ISA/VGA/VGA palette snooping 57 * - Deal with device capabilities on bridges 58 * - Worry about changing a bridge to/from transparency. 59 */ 60 61 #include "opt_pci.h" 62 63 #include <sys/param.h> 64 #include <sys/extent.h> 65 #include <sys/queue.h> 66 #include <sys/systm.h> 67 #include <sys/malloc.h> 68 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pciconf.h> 71 #include <dev/pci/pcidevs.h> 72 73 int pci_conf_debug = 0; 74 75 #if !defined(MIN) 76 #define MIN(a,b) (((a)<(b))?(a):(b)) 77 #define MAX(a,b) (((a)>(b))?(a):(b)) 78 #endif 79 80 /* per-bus constants. */ 81 #define MAX_CONF_DEV 8 /* Arbitrary */ 82 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 83 #define MAX_CONF_IO (1 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 84 85 #define PCI_BUSNO_SPACING (1 << 5) 86 87 struct _s_pciconf_bus_t; /* Forward declaration */ 88 89 typedef struct _s_pciconf_dev_t { 90 int ipin; 91 int iline; 92 int min_gnt; 93 int max_lat; 94 int enable; 95 pcitag_t tag; 96 pci_chipset_tag_t pc; 97 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 98 } pciconf_dev_t; 99 100 typedef struct _s_pciconf_win_t { 101 pciconf_dev_t *dev; 102 int reg; /* 0 for busses */ 103 int align; 104 int prefetch; 105 u_int64_t size; 106 u_int64_t address; 107 } pciconf_win_t; 108 109 typedef struct _s_pciconf_bus_t { 110 int busno; 111 int next_busno; 112 int last_busno; 113 int busno_spacing; 114 int max_mingnt; 115 int min_maxlat; 116 int prefetch; 117 int fast_b2b; 118 int freq_66; 119 int def_ltim; 120 int max_ltim; 121 int bandwidth_used; 122 int swiz; 123 int io_32bit; 124 int pmem_64bit; 125 126 int ndevs; 127 pciconf_dev_t device[MAX_CONF_DEV]; 128 129 /* These should be sorted in order of decreasing size */ 130 int nmemwin; 131 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 132 int niowin; 133 pciconf_win_t pciiowin[MAX_CONF_IO]; 134 135 bus_size_t io_total; 136 bus_size_t mem_total; 137 bus_size_t pmem_total; 138 139 struct extent *ioext; 140 struct extent *memext; 141 struct extent *pmemext; 142 143 pci_chipset_tag_t pc; 144 struct _s_pciconf_bus_t *parent_bus; 145 } pciconf_bus_t; 146 147 static int probe_bus(pciconf_bus_t *); 148 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 149 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 150 static int setup_iowins(pciconf_bus_t *); 151 static int setup_memwins(pciconf_bus_t *); 152 static int configure_bridge(pciconf_dev_t *); 153 static int configure_bus(pciconf_bus_t *); 154 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 155 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 156 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 157 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 158 159 static void print_tag(pci_chipset_tag_t, pcitag_t); 160 161 static void 162 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 163 { 164 int bus, dev, func; 165 166 pci_decompose_tag(pc, tag, &bus, &dev, &func); 167 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 168 } 169 170 /************************************************************************/ 171 /************************************************************************/ 172 /*********************** Bus probing routines ***********************/ 173 /************************************************************************/ 174 /************************************************************************/ 175 static pciconf_win_t * 176 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 177 { 178 int i, n; 179 180 n = pb->niowin; 181 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 182 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 183 return &pb->pciiowin[i]; 184 } 185 186 static pciconf_win_t * 187 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 188 { 189 int i, n; 190 191 n = pb->nmemwin; 192 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 193 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 194 return &pb->pcimemwin[i]; 195 } 196 197 /* 198 * Set up bus common stuff, then loop over devices & functions. 199 * If we find something, call pci_do_device_query()). 200 */ 201 static int 202 probe_bus(pciconf_bus_t *pb) 203 { 204 int device, maxdevs; 205 206 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 207 pb->ndevs = 0; 208 pb->niowin = 0; 209 pb->nmemwin = 0; 210 pb->freq_66 = 1; 211 pb->fast_b2b = 1; 212 pb->prefetch = 1; 213 pb->max_mingnt = 0; /* we are looking for the maximum */ 214 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 215 pb->bandwidth_used = 0; 216 217 for (device=0; device < maxdevs; device++) { 218 pcitag_t tag; 219 pcireg_t id, bhlcr; 220 int function, nfunction; 221 int confmode; 222 223 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 224 if (pci_conf_debug) { 225 print_tag(pb->pc, tag); 226 printf("probing with tag 0x%lx.\n", (u_long) tag); 227 } 228 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 229 230 if (pci_conf_debug) { 231 printf("id=%x: Vendor=%x, Product=%x\n", 232 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 233 } 234 /* Invalid vendor ID value? */ 235 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 236 continue; 237 238 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 239 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 240 for (function = 0 ; function < nfunction ; function++) { 241 tag = pci_make_tag(pb->pc, pb->busno, device, function); 242 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 243 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 244 continue; 245 if (pb->ndevs+1 < MAX_CONF_DEV) { 246 if (pci_conf_debug) { 247 print_tag(pb->pc, tag); 248 printf("Found dev 0x%04x 0x%04x -- " 249 "really probing.\n", 250 PCI_VENDOR(id), PCI_PRODUCT(id)); 251 } 252 #ifdef __HAVE_PCI_CONF_HOOK 253 confmode = pci_conf_hook(pb->pc, pb->busno, 254 device, function, id); 255 if (confmode == 0) 256 continue; 257 #else 258 /* 259 * Don't enable expansion ROMS -- some cards 260 * share address decoders between the EXPROM 261 * and PCI memory space, and enabling the ROM 262 * when not needed will cause all sorts of 263 * lossage. 264 */ 265 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 266 #endif 267 if (pci_do_device_query(pb, tag, device, 268 function, confmode)) 269 return -1; 270 pb->ndevs++; 271 } 272 } 273 } 274 return 0; 275 } 276 277 static void 278 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 279 { 280 pb->busno = parent->next_busno; 281 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 282 panic("Too many PCI busses on bus %d", parent->busno); 283 parent->next_busno = parent->next_busno + parent->busno_spacing; 284 pb->next_busno = pb->busno+1; 285 pb->busno_spacing = parent->busno_spacing >> 1; 286 if (!pb->busno_spacing) 287 panic("PCI busses nested too deep."); 288 pb->last_busno = parent->next_busno - 1; 289 } 290 291 static pciconf_bus_t * 292 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 293 { 294 pciconf_bus_t *pb; 295 pcireg_t busreg, io, pmem; 296 pciconf_win_t *pi, *pm; 297 298 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 299 if (!pb) 300 panic("Unable to allocate memory for PCI configuration."); 301 302 pb->parent_bus = parent; 303 alloc_busno(parent, pb); 304 if (pci_conf_debug) 305 printf("PCI bus bridge covers busses %d-%d\n", 306 pb->busno, pb->last_busno); 307 308 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 309 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 310 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 311 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 312 313 pb->swiz = parent->swiz + dev; 314 315 pb->ioext = NULL; 316 pb->memext = NULL; 317 pb->pmemext = NULL; 318 pb->pc = parent->pc; 319 pb->io_total = pb->mem_total = pb->pmem_total = 0; 320 321 pb->io_32bit = 0; 322 if (parent->io_32bit) { 323 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 324 if (PCI_BRIDGE_IO_32BITS(io)) { 325 pb->io_32bit = 1; 326 } 327 } 328 329 pb->pmem_64bit = 0; 330 if (parent->pmem_64bit) { 331 pmem = pci_conf_read(pb->pc, pd->tag, 332 PCI_BRIDGE_PREFETCHMEM_REG); 333 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 334 pb->pmem_64bit = 1; 335 } 336 } 337 338 if (probe_bus(pb)) { 339 printf("Failed to probe bus %d\n", pb->busno); 340 goto err; 341 } 342 343 if (pb->io_total > 0) { 344 if (parent->niowin >= MAX_CONF_IO) { 345 printf("pciconf: too many I/O windows"); 346 goto err; 347 } 348 pb->io_total |= 0xfff; /* Round up */ 349 pi = get_io_desc(parent, pb->io_total); 350 pi->dev = pd; 351 pi->reg = 0; 352 pi->size = pb->io_total; 353 pi->align = 0x1000; /* 4K alignment */ 354 pi->prefetch = 0; 355 parent->niowin++; 356 parent->io_total += pb->io_total; 357 } 358 359 if (pb->mem_total > 0) { 360 if (parent->nmemwin >= MAX_CONF_MEM) { 361 printf("pciconf: too many MEM windows"); 362 goto err; 363 } 364 pb->mem_total |= 0xfffff; /* Round up */ 365 pm = get_mem_desc(parent, pb->mem_total); 366 pm->dev = pd; 367 pm->reg = 0; 368 pm->size = pb->mem_total; 369 pm->align = 0x100000; /* 1M alignment */ 370 pm->prefetch = 0; 371 parent->nmemwin++; 372 parent->mem_total += pb->mem_total; 373 } 374 375 if (pb->pmem_total > 0) { 376 if (parent->nmemwin >= MAX_CONF_MEM) { 377 printf("pciconf: too many MEM windows"); 378 goto err; 379 } 380 pb->pmem_total |= 0xfffff; /* Round up */ 381 pm = get_mem_desc(parent, pb->pmem_total); 382 pm->dev = pd; 383 pm->reg = 0; 384 pm->size = pb->pmem_total; 385 pm->align = 0x100000; /* 1M alignment */ 386 pm->prefetch = 1; 387 parent->nmemwin++; 388 parent->pmem_total += pb->pmem_total; 389 } 390 391 return pb; 392 err: 393 free(pb, M_DEVBUF); 394 return NULL; 395 } 396 397 static int 398 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 399 { 400 pciconf_dev_t *pd; 401 pciconf_win_t *pi, *pm; 402 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 403 u_int64_t size; 404 int br, width; 405 406 pd = &pb->device[pb->ndevs]; 407 pd->pc = pb->pc; 408 pd->tag = tag; 409 pd->ppb = NULL; 410 pd->enable = mode; 411 412 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 413 414 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 415 416 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 417 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 418 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 419 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 420 } else if (pci_conf_debug) { 421 print_tag(pb->pc, tag); 422 printf("device is a bridge; not clearing enables\n"); 423 } 424 425 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 426 pb->fast_b2b = 0; 427 428 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 429 pb->freq_66 = 0; 430 431 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 432 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 433 pd->ppb = query_bus(pb, pd, dev); 434 if (pd->ppb == NULL) 435 return -1; 436 return 0; 437 } 438 439 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 440 pd->ipin = PCI_INTERRUPT_PIN(icr); 441 pd->iline = PCI_INTERRUPT_LINE(icr); 442 pd->min_gnt = PCI_MIN_GNT(icr); 443 pd->max_lat = PCI_MAX_LAT(icr); 444 if (pd->iline || pd->ipin) { 445 pci_conf_interrupt(pb->pc, pb->busno, dev, func, pb->swiz, 446 &pd->iline); 447 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 448 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 449 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 450 } 451 452 if (pd->min_gnt != 0 || pd->max_lat != 0) { 453 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 454 pb->max_mingnt = pd->min_gnt; 455 456 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 457 pb->min_maxlat = pd->max_lat; 458 459 pb->bandwidth_used += pd->min_gnt * 4000000 / 460 (pd->min_gnt + pd->max_lat); 461 } 462 463 width = 4; 464 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 465 #if 0 466 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 467 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 468 break; 469 } 470 #endif 471 bar = pci_conf_read(pb->pc, tag, br); 472 pci_conf_write(pb->pc, tag, br, 0xffffffff); 473 mask = pci_conf_read(pb->pc, tag, br); 474 pci_conf_write(pb->pc, tag, br, bar); 475 width = 4; 476 477 if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) { 478 /* Upper 16 bits must be one. */ 479 /* XXXJRT -- is this really true? */ 480 mask |= 0xffff0000; 481 482 size = PCI_MAPREG_IO_SIZE(mask); 483 if (size == 0) { 484 if (pci_conf_debug) { 485 print_tag(pb->pc, tag); 486 printf("I/O BAR 0x%x is void\n", br); 487 } 488 continue; 489 } 490 491 if (pb->niowin >= MAX_CONF_IO) { 492 printf("pciconf: too many I/O windows"); 493 return -1; 494 } 495 496 pi = get_io_desc(pb, size); 497 pi->dev = pd; 498 pi->reg = br; 499 pi->size = (u_int64_t) size; 500 pi->align = 4; 501 pi->prefetch = 0; 502 if (pci_conf_debug) { 503 print_tag(pb->pc, tag); 504 printf("Register 0x%x, I/O size %llu\n", 505 br, pi->size); 506 } 507 pb->niowin++; 508 pb->io_total += size; 509 } else if ((mode & PCI_CONF_MAP_MEM) 510 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 511 switch (PCI_MAPREG_MEM_TYPE(mask)) { 512 case PCI_MAPREG_MEM_TYPE_32BIT: 513 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 514 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 515 break; 516 case PCI_MAPREG_MEM_TYPE_64BIT: 517 bar64 = pci_conf_read(pb->pc, tag, br + 4); 518 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 519 mask64 = pci_conf_read(pb->pc, tag, br + 4); 520 pci_conf_write(pb->pc, tag, br + 4, bar64); 521 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 522 (((u_int64_t) mask64) << 32) | mask); 523 width = 8; 524 continue; 525 default: 526 print_tag(pb->pc, tag); 527 printf("reserved mapping type 0x%x\n", 528 PCI_MAPREG_MEM_TYPE(mask)); 529 continue; 530 } 531 532 if (size == 0) { 533 if (pci_conf_debug) { 534 print_tag(pb->pc, tag); 535 printf("MEM%d BAR 0x%x is void\n", 536 PCI_MAPREG_MEM_TYPE(mask) == 537 PCI_MAPREG_MEM_TYPE_64BIT ? 538 64 : 32, br); 539 } 540 continue; 541 } 542 543 if (pb->nmemwin >= MAX_CONF_MEM) { 544 printf("pciconf: too many memory windows"); 545 return -1; 546 } 547 548 pm = get_mem_desc(pb, size); 549 pm->dev = pd; 550 pm->reg = br; 551 pm->size = size; 552 pm->align = 4; 553 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 554 if (pci_conf_debug) { 555 print_tag(pb->pc, tag); 556 printf("Register 0x%x, memory size %llu\n", 557 br, pm->size); 558 } 559 pb->nmemwin++; 560 if (pm->prefetch) { 561 pb->pmem_total += size; 562 } else { 563 pb->mem_total += size; 564 } 565 } 566 } 567 568 if (mode & PCI_CONF_MAP_ROM) { 569 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 570 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 571 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 572 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 573 574 if (mask != 0 && mask != 0xffffffff) { 575 if (pb->nmemwin >= MAX_CONF_MEM) { 576 printf("pciconf: too many memory windows"); 577 return -1; 578 } 579 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 580 581 pm = get_mem_desc(pb, size); 582 pm->dev = pd; 583 pm->reg = PCI_MAPREG_ROM; 584 pm->size = size; 585 pm->align = 4; 586 pm->prefetch = 1; 587 if (pci_conf_debug) { 588 print_tag(pb->pc, tag); 589 printf("Expansion ROM memory size %llu\n", pm->size); 590 } 591 pb->nmemwin++; 592 pb->pmem_total += size; 593 } 594 } 595 596 return 0; 597 } 598 599 /************************************************************************/ 600 /************************************************************************/ 601 /******************** Bus configuration routines ********************/ 602 /************************************************************************/ 603 /************************************************************************/ 604 static u_int64_t 605 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 606 { 607 int r; 608 u_long addr; 609 610 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 611 if (r) { 612 addr = (u_long) -1; 613 printf("extent_alloc(%p, %llu, %d) returned %d\n", 614 ex, amt, align, r); 615 extent_print(ex); 616 } 617 return (pcireg_t) addr; 618 } 619 620 static int 621 setup_iowins(pciconf_bus_t *pb) 622 { 623 pciconf_win_t *pi; 624 pciconf_dev_t *pd; 625 626 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 627 if (pi->size == 0) 628 continue; 629 630 pd = pi->dev; 631 pi->address = pci_allocate_range(pb->ioext, pi->size, 632 pi->align); 633 if (pi->address == -1) { 634 print_tag(pd->pc, pd->tag); 635 printf("Failed to allocate PCI I/O space (%llu req)\n", 636 pi->size); 637 return -1; 638 } 639 if (!pb->io_32bit && pi->address > 0xFFFF) { 640 pi->address = 0; 641 pd->enable = 0; 642 } 643 if (pd->ppb && pi->reg == 0) { 644 pd->ppb->ioext = extent_create("pciconf", pi->address, 645 pi->address + pi->size, M_DEVBUF, NULL, 0, 646 EX_NOWAIT); 647 if (pd->ppb->ioext == NULL) { 648 print_tag(pd->pc, pd->tag); 649 printf("Failed to alloc I/O ext. for bus %d\n", 650 pd->ppb->busno); 651 return -1; 652 } 653 continue; 654 } 655 if (pci_conf_debug) { 656 print_tag(pd->pc, pd->tag); 657 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 658 pi->size, pi->address, pi->reg); 659 } 660 pci_conf_write(pd->pc, pd->tag, pi->reg, 661 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 662 } 663 return 0; 664 } 665 666 static int 667 setup_memwins(pciconf_bus_t *pb) 668 { 669 pciconf_win_t *pm; 670 pciconf_dev_t *pd; 671 pcireg_t base; 672 struct extent *ex; 673 674 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 675 if (pm->size == 0) 676 continue; 677 678 pd = pm->dev; 679 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 680 pm->address = pci_allocate_range(ex, pm->size, pm->align); 681 if (pm->address == -1) { 682 print_tag(pd->pc, pd->tag); 683 printf( 684 "Failed to allocate PCI memory space (%llu req)\n", 685 pm->size); 686 return -1; 687 } 688 if (pd->ppb && pm->reg == 0) { 689 ex = extent_create("pciconf", pm->address, 690 pm->address + pm->size, M_DEVBUF, NULL, 0, 691 EX_NOWAIT); 692 if (ex == NULL) { 693 print_tag(pd->pc, pd->tag); 694 printf("Failed to alloc MEM ext. for bus %d\n", 695 pd->ppb->busno); 696 return -1; 697 } 698 if (pm->prefetch) { 699 pd->ppb->pmemext = ex; 700 } else { 701 pd->ppb->memext = ex; 702 } 703 continue; 704 } 705 if (pm->prefetch && !pb->pmem_64bit && 706 pm->address > 0xFFFFFFFFULL) { 707 pm->address = 0; 708 pd->enable = 0; 709 } 710 if (pm->reg != PCI_MAPREG_ROM) { 711 if (pci_conf_debug) { 712 print_tag(pd->pc, pd->tag); 713 printf( 714 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 715 pm->size, pm->address, pm->reg); 716 } 717 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 718 base = PCI_MAPREG_MEM_ADDR(pm->address) | 719 PCI_MAPREG_MEM_TYPE(base); 720 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 721 if (PCI_MAPREG_MEM_TYPE(base) == 722 PCI_MAPREG_MEM_TYPE_64BIT) { 723 base = (pcireg_t) 724 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 725 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 726 base); 727 } 728 } 729 } 730 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 731 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 732 pd = pm->dev; 733 if (pci_conf_debug) { 734 print_tag(pd->pc, pd->tag); 735 printf( 736 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 737 pm->size, pm->address, pm->reg); 738 } 739 base = ((pcireg_t) pm->address) | PCI_MAPREG_TYPE_ROM; 740 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 741 } 742 } 743 return 0; 744 } 745 746 /* 747 * Configure I/O, memory, and prefetcable memory spaces, then make 748 * a call to configure_bus(). 749 */ 750 static int 751 configure_bridge(pciconf_dev_t *pd) 752 { 753 unsigned long io_base, io_limit, mem_base, mem_limit; 754 pciconf_bus_t *pb; 755 pcireg_t io, iohigh, mem, cmd; 756 int rv; 757 758 pb = pd->ppb; 759 /* Configure I/O base & limit*/ 760 if (pb->ioext) { 761 io_base = pb->ioext->ex_start; 762 io_limit = pb->ioext->ex_end; 763 } else { 764 io_base = 0x1000; /* 4K */ 765 io_limit = 0x0000; 766 } 767 if (pb->io_32bit) { 768 iohigh = 769 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 770 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 771 } else { 772 if (io_limit > 0xFFFF) { 773 printf("Bus %d bridge does not support 32-bit I/O. ", 774 pb->busno); 775 printf("Disabling I/O accesses\n"); 776 io_base = 0x1000; /* 4K */ 777 io_limit = 0x0000; 778 } 779 iohigh = 0; 780 } 781 io &= (PCI_BRIDGE_STATIO_STATUS_MASK << 782 PCI_BRIDGE_STATIO_STATUS_SHIFT); 783 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 784 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 785 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 786 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 787 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 788 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 789 790 /* Configure mem base & limit */ 791 if (pb->memext) { 792 mem_base = pb->memext->ex_start; 793 mem_limit = pb->memext->ex_end; 794 } else { 795 mem_base = 0x100000; /* 1M */ 796 mem_limit = 0x000000; 797 } 798 if (mem_limit > 0xFFFFFFFFULL) { 799 printf("Bus %d bridge MEM range out of range. ", pb->busno); 800 printf("Disabling MEM accesses\n"); 801 mem_base = 0x100000; /* 1M */ 802 mem_limit = 0x000000; 803 } 804 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 805 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 806 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 807 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 808 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 809 810 /* Configure prefetchable mem base & limit */ 811 if (pb->pmemext) { 812 mem_base = pb->pmemext->ex_start; 813 mem_limit = pb->pmemext->ex_end; 814 } else { 815 mem_base = 0x100000; /* 1M */ 816 mem_limit = 0x000000; 817 } 818 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 819 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 820 printf("Bus %d bridge does not support 64-bit PMEM. ", 821 pb->busno); 822 printf("Disabling prefetchable-MEM accesses\n"); 823 mem_base = 0x100000; /* 1M */ 824 mem_limit = 0x000000; 825 } 826 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 827 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 828 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 829 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 830 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 831 /* 832 * XXX -- 64-bit systems need a lot more than just this... 833 */ 834 if (sizeof(u_long) > 4) { 835 mem_base = (int64_t) mem_base >> 32; 836 mem_limit = (int64_t) mem_limit >> 32; 837 } 838 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 839 mem_base & 0xffffffff); 840 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 841 mem_limit & 0xffffffff); 842 843 rv = configure_bus(pb); 844 845 if (pb->ioext) 846 extent_destroy(pb->ioext); 847 if (pb->memext) 848 extent_destroy(pb->memext); 849 if (pb->pmemext) 850 extent_destroy(pb->pmemext); 851 if (rv == 0) { 852 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 853 cmd &= PCI_BRIDGE_CONTROL_MASK; 854 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 855 << PCI_BRIDGE_CONTROL_SHIFT; 856 if (pb->fast_b2b) { 857 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 858 << PCI_BRIDGE_CONTROL_SHIFT; 859 } 860 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 861 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 862 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 863 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 864 } 865 866 return rv; 867 } 868 869 /* 870 * Calculate latency values, allocate I/O and MEM segments, then set them 871 * up. If a PCI-PCI bridge is found, configure the bridge separately, 872 * which will cause a recursive call back here. 873 */ 874 static int 875 configure_bus(pciconf_bus_t *pb) 876 { 877 pciconf_dev_t *pd; 878 int def_ltim, max_ltim, band; 879 880 /* MIN_GNT assumes a clock rate of 33MHz */ 881 max_ltim = pb->max_mingnt * 33 / 4; /* cvt to cycle count */ 882 band = 40000000; /* 0.25us cycles/sec */ 883 if (band < pb->bandwidth_used) { 884 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 885 pb->busno); 886 def_ltim = -1; 887 } else { 888 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 889 if (def_ltim > pb->min_maxlat) 890 def_ltim = pb->min_maxlat; 891 def_ltim = def_ltim * 33 / 4; 892 } 893 def_ltim = (def_ltim + 7) & ~7; 894 max_ltim = (max_ltim + 7) & ~7; 895 896 pb->def_ltim = MIN( def_ltim, 255 ); 897 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 898 899 /* 900 * Now we have what we need to initialize the devices. 901 * It would probably be better if we could allocate all of these 902 * for all busses at once, but "not right now". First, get a list 903 * of free memory ranges from the m.d. system. 904 */ 905 if (setup_iowins(pb) || setup_memwins(pb)) { 906 printf("PCI bus configuration failed: "); 907 printf("unable to assign all I/O and memory ranges."); 908 return -1; 909 } 910 911 /* 912 * Configure the latency for the devices, and enable them. 913 */ 914 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 915 pcireg_t cmd, class, misc; 916 int ltim; 917 918 if (pci_conf_debug) { 919 print_tag(pd->pc, pd->tag); 920 printf("Configuring device.\n"); 921 } 922 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 923 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 924 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 925 cmd |= PCI_COMMAND_MASTER_ENABLE 926 | PCI_COMMAND_SERR_ENABLE 927 | PCI_COMMAND_PARITY_ENABLE; 928 if (pb->fast_b2b) 929 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 930 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 931 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 932 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 933 ltim = pd->min_gnt * 33 / 4; 934 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 935 } else { 936 ltim = MIN (pb->def_ltim, pb->max_ltim); 937 } 938 if (!pd->enable) { 939 print_tag(pd->pc, pd->tag); 940 printf("Disabled due to lack of resources.\n"); 941 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 942 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 943 } 944 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 945 946 misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) 947 | ((ltim & 0xff) << PCI_LATTIMER_SHIFT); 948 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 949 950 if (pd->ppb) { 951 if (configure_bridge(pd) < 0) 952 return -1; 953 continue; 954 } 955 } 956 957 if (pci_conf_debug) { 958 printf("PCI bus %d configured\n", pb->busno); 959 } 960 961 return 0; 962 } 963 964 /* 965 * Let's configure the PCI bus. 966 * This consists of basically scanning for all existing devices, 967 * identifying their needs, and then making another pass over them 968 * to set: 969 * 1. I/O addresses 970 * 2. Memory addresses (Prefetchable and not) 971 * 3. PCI command register 972 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 973 * Header type, Latency timer, Cache line size) register 974 * 975 * The command register is set to enable fast back-to-back transactions 976 * if the host bridge says it can handle it. We also configure 977 * Master Enable, SERR enable, parity enable, and (if this is not a 978 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 979 * will not report some I/O space. 980 * 981 * The latency is computed to be a "fair share" of the bus bandwidth. 982 * The bus bandwidth variable is initialized to the number of PCI cycles 983 * in one second. The number of cycles taken for one transaction by each 984 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 985 * Care is taken to ensure that the latency timer won't be set such that 986 * it would exceed the critical time for any device. 987 * 988 * This is complicated somewhat due to the presence of bridges. PCI-PCI 989 * bridges are probed and configured recursively. 990 */ 991 int 992 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 993 struct extent *memext, struct extent *pmemext) 994 { 995 pciconf_bus_t *pb; 996 int rv; 997 998 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 999 pb->busno = 0; 1000 pb->busno_spacing = PCI_BUSNO_SPACING; 1001 pb->next_busno = pb->busno + 1; 1002 pb->last_busno = 255; 1003 pb->parent_bus = NULL; 1004 pb->swiz = 0; 1005 pb->io_32bit = 1; 1006 pb->pmem_64bit = 0; 1007 pb->ioext = ioext; 1008 pb->memext = memext; 1009 if (pmemext == NULL) { 1010 pb->pmemext = memext; 1011 } else { 1012 pb->pmemext = pmemext; 1013 } 1014 pb->pc = pc; 1015 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1016 1017 rv = probe_bus(pb); 1018 if (rv == 0) { 1019 rv = configure_bus(pb); 1020 } 1021 1022 /* 1023 * All done! 1024 */ 1025 free(pb, M_DEVBUF); 1026 return rv; 1027 } 1028
Indexes created Wed Sep 24 22:09:59 GMT 2025