pciide_piix_reg.h revision 1.2
1 1.2 bouyer /* $NetBSD: pciide_piix_reg.h,v 1.2 1998/10/12 16:09:21 bouyer Exp $ */ 2 1.2 bouyer 3 1.2 bouyer /* 4 1.2 bouyer * Copyright (c) 1998 Manuel Bouyer. 5 1.2 bouyer * 6 1.2 bouyer * Redistribution and use in source and binary forms, with or without 7 1.2 bouyer * modification, are permitted provided that the following conditions 8 1.2 bouyer * are met: 9 1.2 bouyer * 1. Redistributions of source code must retain the above copyright 10 1.2 bouyer * notice, this list of conditions and the following disclaimer. 11 1.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 12 1.2 bouyer * notice, this list of conditions and the following disclaimer in the 13 1.2 bouyer * documentation and/or other materials provided with the distribution. 14 1.2 bouyer * 3. All advertising materials mentioning features or use of this software 15 1.2 bouyer * must display the following acknowledgement: 16 1.2 bouyer * This product includes software developed by the University of 17 1.2 bouyer * California, Berkeley and its contributors. 18 1.2 bouyer * 4. Neither the name of the University nor the names of its contributors 19 1.2 bouyer * may be used to endorse or promote products derived from this software 20 1.2 bouyer * without specific prior written permission. 21 1.2 bouyer * 22 1.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 1.2 bouyer * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 1.2 bouyer * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 1.2 bouyer * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 1.2 bouyer * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.2 bouyer * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 1.2 bouyer * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.2 bouyer * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.2 bouyer * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.2 bouyer * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.2 bouyer * SUCH DAMAGE. 33 1.2 bouyer * 34 1.2 bouyer */ 35 1.2 bouyer 36 1.2 bouyer /* 37 1.2 bouyer * Registers definitions for Intel's PIIX serie PCI IDE controllers. 38 1.2 bouyer * See Intel's 39 1.2 bouyer * "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR" and 40 1.2 bouyer * "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" 41 1.2 bouyer * available from http://www.intel.com/ 42 1.2 bouyer */ 43 1.2 bouyer 44 1.2 bouyer /* 45 1.2 bouyer * Bus master interface base address register 46 1.2 bouyer */ 47 1.2 bouyer #define PIIX_BMIBA 0x20 48 1.2 bouyer #define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0) 49 1.2 bouyer #define PIIX_BMIBA_RTE(x) (x & 0x000000001) 50 1.2 bouyer #define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */ 51 1.2 bouyer 52 1.2 bouyer /* 53 1.2 bouyer * IDE timing register 54 1.2 bouyer * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel 55 1.2 bouyer */ 56 1.2 bouyer #define PIIX_IDETIM 0x40 57 1.2 bouyer #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF) 58 1.2 bouyer #define PIIX_IDETIM_SET(x, bytes, channel) \ 59 1.2 bouyer ((x) | ((bytes) << (16 * (channel)))) 60 1.2 bouyer #define PIIX_IDETIM_CLEAR(x, bytes, channel) \ 61 1.2 bouyer ((x) & ~((bytes) << (16 * (channel)))) 62 1.2 bouyer 63 1.2 bouyer #define PIIX_IDETIM_IDE 0x8000 /* PIIX decode IDE registers */ 64 1.2 bouyer #define PIIX_IDETIM_SITRE 0x4000 /* slaves IDE timing registers 65 1.2 bouyer enabled (PIIX3/4 only) */ 66 1.2 bouyer #define PIIX_IDETIM_ISP_MASK 0x3000 /* IOrdy sample point */ 67 1.2 bouyer #define PIIX_IDETIM_ISP_SHIFT 12 68 1.2 bouyer #define PIIX_IDETIM_ISP_SET(x) ((x) << PIIX_IDETIM_ISP_SHIFT) 69 1.2 bouyer #define PIIX_IDETIM_RTC_MASK 0x0300 /* recovery time */ 70 1.2 bouyer #define PIIX_IDETIM_RTC_SHIFT 8 71 1.2 bouyer #define PIIX_IDETIM_RTC_SET(x) ((x) << PIIX_IDETIM_RTC_SHIFT) 72 1.2 bouyer #define PIIX_IDETIM_DTE(d) (0x0008 << (4 * (d))) /* DMA timing only */ 73 1.2 bouyer #define PIIX_IDETIM_PPE(d) (0x0004 << (4 * (d))) /* prefetch/posting */ 74 1.2 bouyer #define PIIX_IDETIM_IE(d) (0x0002 << (4 * (d))) /* IORDY enable */ 75 1.2 bouyer #define PIIX_IDETIM_TIME(d) (0x0001 << (4 * (d))) /* Fast timing enable */ 76 1.2 bouyer /* 77 1.2 bouyer * Slave IDE timing register (PIIX3/4 only) 78 1.2 bouyer * This register must be enabled via the PIIX_IDETIM_SITRE bit 79 1.2 bouyer */ 80 1.2 bouyer #define PIIX_SIDETIM 0x44 81 1.2 bouyer #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4)) 82 1.2 bouyer #define PIIX_SIDETIM_ISP_SHIFT 2 83 1.2 bouyer #define PIIX_SIDETIM_ISP_SET(x, channel) \ 84 1.2 bouyer (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4))) 85 1.2 bouyer #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4)) 86 1.2 bouyer #define PIIX_SIDETIM_RTC_SHIFT 0 87 1.2 bouyer #define PIIX_SIDETIM_RTC_SET(x, channel) \ 88 1.2 bouyer (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4))) 89 1.2 bouyer 90 1.2 bouyer /* 91 1.2 bouyer * Ultra DMA/33 register (PIIX4 only) 92 1.2 bouyer */ 93 1.2 bouyer #define PIIX_UDMAREG 0x48 94 1.2 bouyer /* Control register */ 95 1.2 bouyer #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive))) 96 1.2 bouyer /* Ultra DMA/33 timing register (PIIX4 only) */ 97 1.2 bouyer #define PIIX_UDMATIM_SHIFT 16 98 1.2 bouyer #define PIIX_UDMATIM_SET(x, channel, drive) \ 99 1.2 bouyer (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT) 100 1.2 bouyer /* 101 1.2 bouyer * these tables define the differents values to upload to the 102 1.2 bouyer * ISP and RTC registers for the various PIO and DMA mode 103 1.2 bouyer * (from the PIIX4 doc). 104 1.2 bouyer */ 105 1.2 bouyer static int8_t piix_isp_pio[] = {0x00, 0x00, 0x01, 0x02, 0x02}; 106 1.2 bouyer static int8_t piix_rtc_pio[] = {0x00, 0x00, 0x00, 0x01, 0x03}; 107 1.2 bouyer static int8_t piix_isp_dma[] = {0x00, 0x02, 0x02}; 108 1.2 bouyer static int8_t piix_rtc_dma[] = {0x00, 0x02, 0x03}; 109 1.2 bouyer static int8_t piix4_sct_udma[] = {0x00, 0x01, 0x02}; 110
Indexes created Sat Sep 27 14:09:57 GMT 2025