pciide_piix_reg.h revision 1.12
1 /* $NetBSD: pciide_piix_reg.h,v 1.12 2006/09/03 18:30:35 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Registers definitions for Intel's PIIX serie PCI IDE controllers. 35 * See Intel's 36 * "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR" 37 * "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" and 38 * "Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub" 39 * available from http://developers.intel.com/ 40 */ 41 42 /* 43 * Bus master interface base address register 44 */ 45 #define PIIX_BMIBA 0x20 46 #define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0) 47 #define PIIX_BMIBA_RTE(x) (x & 0x000000001) 48 #define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */ 49 50 /* 51 * IDE timing register 52 * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel 53 */ 54 #define PIIX_IDETIM 0x40 55 #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF) 56 #define PIIX_IDETIM_SET(x, bytes, channel) \ 57 ((x) | ((bytes) << (16 * (channel)))) 58 #define PIIX_IDETIM_CLEAR(x, bytes, channel) \ 59 ((x) & ~((bytes) << (16 * (channel)))) 60 61 #define PIIX_IDETIM_IDE 0x8000 /* PIIX decode IDE registers */ 62 #define PIIX_IDETIM_SITRE 0x4000 /* slaves IDE timing registers 63 enabled (PIIX3/4 only) */ 64 #define PIIX_IDETIM_ISP_MASK 0x3000 /* IOrdy sample point */ 65 #define PIIX_IDETIM_ISP_SHIFT 12 66 #define PIIX_IDETIM_ISP_SET(x) ((x) << PIIX_IDETIM_ISP_SHIFT) 67 #define PIIX_IDETIM_RTC_MASK 0x0300 /* recovery time */ 68 #define PIIX_IDETIM_RTC_SHIFT 8 69 #define PIIX_IDETIM_RTC_SET(x) ((x) << PIIX_IDETIM_RTC_SHIFT) 70 #define PIIX_IDETIM_DTE(d) (0x0008 << (4 * (d))) /* DMA timing only */ 71 #define PIIX_IDETIM_PPE(d) (0x0004 << (4 * (d))) /* prefetch/posting */ 72 #define PIIX_IDETIM_IE(d) (0x0002 << (4 * (d))) /* IORDY enable */ 73 #define PIIX_IDETIM_TIME(d) (0x0001 << (4 * (d))) /* Fast timing enable */ 74 /* 75 * Slave IDE timing register (PIIX3/4 only) 76 * This register must be enabled via the PIIX_IDETIM_SITRE bit 77 */ 78 #define PIIX_SIDETIM 0x44 79 #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4)) 80 #define PIIX_SIDETIM_ISP_SHIFT 2 81 #define PIIX_SIDETIM_ISP_SET(x, channel) \ 82 (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4))) 83 #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4)) 84 #define PIIX_SIDETIM_RTC_SHIFT 0 85 #define PIIX_SIDETIM_RTC_SET(x, channel) \ 86 (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4))) 87 88 /* 89 * Ultra DMA/33 register (PIIX4 only) 90 */ 91 #define PIIX_UDMAREG 0x48 92 /* Control register */ 93 #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive))) 94 /* Ultra DMA/33 timing register (PIIX4 only) */ 95 #define PIIX_UDMATIM 0x4a 96 #define PIIX_UDMATIM_SHIFT 16 97 #define PIIX_UDMATIM_SET(x, channel, drive) \ 98 (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT) 99 100 /* 101 * IDE config register (ICH/ICH0/ICH2 only) 102 */ 103 #define PIIX_CONFIG 0x54 104 #define PIIX_CONFIG_PINGPONG 0x0400 105 /* The following are only for the 82801AA (ICH) and 82801BA (ICH2) */ 106 #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive))) 107 #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive))) 108 /* The following are only for the 82801BA (ICH2) */ 109 #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive))) 110 111 /* 112 * these tables define the differents values to upload to the 113 * ISP and RTC registers for the various PIO and DMA mode 114 * (from the PIIX4 doc). 115 */ 116 static const int8_t piix_isp_pio[] __attribute__((__unused__)) = 117 {0x00, 0x00, 0x01, 0x02, 0x02}; 118 static const int8_t piix_rtc_pio[] __attribute__((__unused__)) = 119 {0x00, 0x00, 0x00, 0x01, 0x03}; 120 static const int8_t piix_isp_dma[] __attribute__((__unused__)) = 121 {0x00, 0x02, 0x02}; 122 static const int8_t piix_rtc_dma[] __attribute__((__unused__)) = 123 {0x00, 0x02, 0x03}; 124 static const int8_t piix4_sct_udma[] __attribute__((__unused__)) = 125 {0x00, 0x01, 0x02, 0x01, 0x02, 0x01}; 126 127 /* 128 * ICH5/ICH5R SATA registers definitions 129 */ 130 #define ICH5_SATA_MAP 0x90 /* Address Map Register */ 131 #define ICH5_SATA_MAP_MV_MASK 0x07 /* Map Value mask */ 132 #define ICH5_SATA_MAP_COMBINED 0x04 /* Combined mode */ 133 134 #define ICH5_SATA_PI 0x09 /* Program Interface register */ 135 #define ICH5_SATA_PI_PRI_NATIVE 0x01 /* Put Pri IDE channel in native mode */ 136 #define ICH5_SATA_PI_SEC_NATIVE 0x04 /* Put Sec IDE channel in native mode */ 137 138 #define ICH_SATA_PCS 0x92 /* Port Control and Status Register */ 139 #define ICH_SATA_PCS_P0E 0x01 /* Port 0 enabled */ 140 #define ICH_SATA_PCS_P1E 0x02 /* Port 1 enabled */ 141 #define ICH_SATA_PCS_P0P 0x10 /* Port 0 present */ 142 #define ICH_SATA_PCS_P1P 0x20 /* Port 1 present */ 143 144 /* 145 * * ICH6/ICH7 SATA registers definitions 146 * */ 147 #define ICH6_SATA_MAP_CMB_MASK 0x03 /* Combined mode bits */ 148 #define ICH6_SATA_MAP_CMB_PRI 0x01 /* Combined mode, IDE Primary */ 149 #define ICH6_SATA_MAP_CMB_SEC 0x02 /* Combined mode, IDE Secondary */ 150 #define ICH7_SATA_MAP_SMS_MASK 0xc0 /* SATA Mode Select */ 151 #define ICH7_SATA_MAP_SMS_IDE 0x00 152 #define ICH7_SATA_MAP_SMS_AHCI 0x40 153 #define ICH7_SATA_MAP_SMS_RAID 0x80 154
Indexes created Mon Sep 29 21:09:56 GMT 2025