piixpmreg.h revision 1.13
1 /* $NetBSD: piixpmreg.h,v 1.13 2023/01/10 00:05:53 msaitoh Exp $ */ 2 /* $OpenBSD: piixreg.h,v 1.3 2006/01/03 22:39:03 grange Exp $ */ 3 4 /*- 5 * Copyright (c) 2016 Andriy Gapon <avg (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/dev/amdsbwd/amd_chipset.h 333269 2018-05-05 05:22:11Z avg $ 30 */ 31 32 /* 33 * Copyright (c) 2005 Alexander Yurchenko <grange (at) openbsd.org> 34 * 35 * Permission to use, copy, modify, and distribute this software for any 36 * purpose with or without fee is hereby granted, provided that the above 37 * copyright notice and this permission notice appear in all copies. 38 * 39 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 40 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 41 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 42 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 43 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 44 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 45 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 46 */ 47 48 #ifndef _DEV_PCI_PIIXREG_H_ 49 #define _DEV_PCI_PIIXREG_H_ 50 51 /* 52 * Intel PCI-to-ISA / IDE Xcelerator (PIIX) register definitions. 53 */ 54 55 /* 56 * Power management registers. 57 */ 58 59 /* PCI configuration registers */ 60 #define PIIX_PM_BASE 0x40 /* Power management base address */ 61 #define PIIX_PM_BASE_CSB5_RESET 0x10 /* CSB5 PM reset */ 62 #define PIIX_DEVACTA 0x54 /* Device activity A (function 3) */ 63 #define PIIX_DEVACTB 0x58 /* Device activity B (function 3) */ 64 #define PIIX_PMREGMISC 0x80 /* Misc. Power management */ 65 #define PIIX_SMB_BASE 0x90 /* SMBus base address */ 66 #define PIIX_SMB_HOSTC 0xd0 /* SMBus host configuration */ 67 #define PIIX_SMB_HOSTC_HSTEN (1 << 16) /* enable host controller */ 68 #define PIIX_SMB_HOSTC_SMI (0 << 17) /* SMI */ 69 #define PIIX_SMB_HOSTC_IRQ (4 << 17) /* IRQ 9 */ 70 #define PIIX_SMB_HOSTC_INTMASK (7 << 17) 71 72 /* SMBus I/O registers */ 73 #define PIIX_SMB_HS 0x00 /* host status */ 74 #define PIIX_SMB_HS_BUSY (1 << 0) /* running a command */ 75 #define PIIX_SMB_HS_INTR (1 << 1) /* command completed */ 76 #define PIIX_SMB_HS_DEVERR (1 << 2) /* command error */ 77 #define PIIX_SMB_HS_BUSERR (1 << 3) /* transaction collision */ 78 #define PIIX_SMB_HS_FAILED (1 << 4) /* failed bus transaction */ 79 #define PIIX_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED" 80 #define PIIX_SMB_HC 0x02 /* host control */ 81 #define PIIX_SMB_HC_INTREN (1 << 0) /* enable interrupts */ 82 #define PIIX_SMB_HC_KILL (1 << 1) /* kill current transaction */ 83 #define PIIX_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */ 84 #define PIIX_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */ 85 #define PIIX_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */ 86 #define PIIX_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */ 87 #define PIIX_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */ 88 #define PIIX_SMB_HC_START (1 << 6) /* start transaction */ 89 #define PIIX_SMB_HCMD 0x03 /* host command */ 90 #define PIIX_SMB_TXSLVA 0x04 /* transmit slave address */ 91 #define PIIX_SMB_TXSLVA_READ (1 << 0) /* read direction */ 92 #define PIIX_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */ 93 #define PIIX_SMB_HD0 0x05 /* host data 0 */ 94 #define PIIX_SMB_HD1 0x06 /* host data 1 */ 95 #define PIIX_SMB_HBDB 0x07 /* host block data byte */ 96 #define PIIX_SMB_SC 0x08 /* slave control */ 97 #define PIIX_SMB_SC_ALERTEN (1 << 3) /* enable SMBALERT# */ 98 #define PIIX_SMB_SC_HOSTSEM (1 << 4) /* (W1S) HostSemaphore */ 99 #define PIIX_SMB_SC_CLRHOSTSEM (1 << 5) /* (W1C) ClrHostSemaphore */ 100 #define PIIX_SMB_SC_ECSEM (1 << 6) /* (W1S) EcSemaphore */ 101 #define PIIX_SMB_SC_CLRECSEM (1 << 7) /* (W1C) ClrEcSemaphore */ 102 #define PIIX_SMB_SC_SEMMASK 0xf0 /* Semaphore bits */ 103 104 /* Power management I/O registers */ 105 #define PIIX_PM_PMTMR 0x08 /* power management timer */ 106 107 /* Misc */ 108 #define PIIX_PM_SIZE 0x38 /* Power management I/O space size */ 109 #define PIIX_SMB_SIZE 0x10 /* SMBus I/O space size */ 110 111 /* 112 * AMD SB800 and compatible chipset's configuration registers. 113 * See SB8xx RRG 2.3.3, etc. 114 */ 115 116 /* In the I/O area */ 117 #define SB800_INDIRECTIO_BASE 0xcd6 118 #define SB800_INDIRECTIO_SIZE 2 119 #define SB800_INDIRECTIO_INDEX 0 120 #define SB800_INDIRECTIO_DATA 1 121 122 /* In the MMIO area */ 123 #define SB800_FCH_PM_BASE 0xfed80300 124 #define SB800_FCH_PM_SIZE 8 125 126 #define SB800_PM_SMBUS0EN_LO 0x2c 127 #define SB800_PM_SMBUS0EN_HI 0x2d 128 #define SB800_PM_SMBUS0EN_ENABLE __BIT(0) /* Function enable */ 129 #define SB800_PM_SMBUS0_MASK_C __BITS(2, 1) /* Port mask (PMIO2C) */ 130 #define SB800_PM_SMBUS0EN_BADDR __BITS(15, 5) /* Base address */ 131 132 #define SB800_PM_SMBUS0SEL 0x2e 133 #define SB800_PM_SMBUS0_MASK_E __BITS(2, 1) /* Port mask (PMIO2E) */ 134 #define SB800_PM_SMBUS0SELEN 0x2f 135 #define SB800_PM_USE_SMBUS0SEL __BIT(0) /* 136 * If the bit is set, SMBUS0SEL is 137 * used to select the port. 138 */ 139 140 /* In the SMBus I/O space */ 141 #define SB800_SMB_HOSTC 0x10 /* I2C bus configuration */ 142 #define SB800_SMB_HOSTC_IRQ (1 << 0) /* 0:SMI 1:IRQ */ 143 144 /* Misc */ 145 #define SB800_SMB_SIZE 0x11 /* SMBus I/O space size */ 146 147 /* 148 * Newer FCH registers in the PMIO space. 149 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 150 */ 151 #define AMDFCH41_PM_DECODE_EN0 0x00 152 #define AMDFCH41_SMBUS_EN 0x10 153 #define AMDFCH41_WDT_EN 0x80 154 #define AMDFCH41_PM_DECODE_EN1 0x01 155 #define AMDFCH41_PM_PORT_INDEX 0x02 156 #define AMDFCH41_SMBUS_PORTMASK 0x18 157 #define AMDFCH41_PM_DECODE_EN3 0x03 158 #define AMDFCH41_WDT_RES_MASK 0x03 159 #define AMDFCH41_WDT_RES_32US 0x00 160 #define AMDFCH41_WDT_RES_10MS 0x01 161 #define AMDFCH41_WDT_RES_100MS 0x02 162 #define AMDFCH41_WDT_RES_1S 0x03 163 #define AMDFCH41_WDT_EN_MASK 0x0c 164 #define AMDFCH41_WDT_ENABLE 0x00 165 #define AMDFCH41_PM_ISA_CTRL 0x04 166 #define AMDFCH41_MMIO_EN 0x02 167 168 #endif /* !_DEV_PCI_PIIXREG_H_ */ 169
Indexes created Tue Sep 30 06:09:59 GMT 2025