1 /* $NetBSD: pm2reg.h,v 1.12 2016/12/16 23:31:16 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * register definitions for Permedia 2 graphics controllers 30 */ 31 32 33 #ifndef PM2_REG_H 34 #define PM2_REG_H 35 36 /* all frequencies are in kHz */ 37 #define PM2_EXT_CLOCK_FREQ 14318 38 #define PM2_PLL_FREQ_MIN 150000 39 #define PM2_PLL_FREQ_MAX 300000 40 41 #define PM2_RESET 0x00000000 /* any write initiates a chip reset */ 42 #define PM2_RESET_BUSY 0x80000000 /* reset in progress */ 43 44 #define PM2_INPUT_FIFO_SPACE 0x00000018 45 #define PM2_OUTPUT_FIFO_WORDS 0x00000020 46 47 #define PM2_VCLKCTL 0x00000040 48 #define VCC_CLOCK_A 0x00000000 49 #define VCC_CLOCK_B 0x00000001 50 #define VCC_CLOCK_C 0x00000002 51 /* PCI clocks to wait between RAMDAC accesses */ 52 #define VCC_RAMDAC_WAIT_MASK 0x000003fc 53 54 #define PM2_APERTURE1_CONTROL 0x00000050 55 #define PM2_APERTURE2_CONTROL 0x00000058 56 #define PM2_AP_BYTESWAP 0x00000001 57 #define PM2_AP_HALFWORDSWAP 0x00000002 58 #define PM2_AP_PACKED16_EN 0x00000008 59 #define PM2_AP_PACKED16_READ_B 0x00000010 /* Buffer A otherwise */ 60 #define PM2_AP_PACKED16_WRITE_B 0x00000020 /* A otherwise */ 61 #define PM2_AP_PACKED16_WRT_DBL 0x00000040 62 #define PM2_AP_PACKED16_R31 0x00000080 /* read buffer selected by 63 * visibility bit in memory 64 */ 65 #define PM2_AP_SVGA 0x00000100 66 #define PM2_AP_ROM 0x00000200 67 68 #define PM2_CHIP_CONFIG 0x00000070 69 70 #define PM2_BYPASS_MASK 0x00001100 71 #define PM2_FB_WRITE_MASK 0x00001140 72 73 #define PM2_OUTPUT_FIFO 0x00002000 74 75 #define PM2_SCREEN_BASE 0x00003000 /* in 64bit units */ 76 #define PM2_SCREEN_STRIDE 0x00003008 /* in 64bit units */ 77 #define PM2_HTOTAL 0x00003010 78 #define PM2_HGATE_END 0x00003018 79 #define PM2_HBLANK_END 0x00003020 80 #define PM2_HSYNC_START 0x00003028 81 #define PM2_HSYNC_END 0x00003030 82 #define PM2_VTOTAL 0x00003038 83 #define PM2_VBLANK_END 0x00003040 84 #define PM2_VSYNC_START 0x00003048 85 #define PM2_VSYNC_END 0x00003050 86 #define PM2_VIDEO_CONTROL 0x00003058 87 #define PM2_VC_VIDEO_ENABLE 0x00000001 88 #define PM2_VC_BLANK_ACR_LOW 0x00000002 89 #define PM2_VC_LINE_DOUBLE 0x00000004 90 #define PM2_VC_HSYNC_FORCE_H 0x00000000 91 #define PM2_VC_HSYNC_ACT_HIGH 0x00000008 92 #define PM2_VC_HSYNC_FORCE_L 0x00000010 93 #define PM2_VC_HSYNC_ACT_LOW 0x00000018 94 #define PM2_VC_VSYNC_FORCE_H 0x00000000 95 #define PM2_VC_VSYNC_ACT_HIGH 0x00000020 96 #define PM2_VC_VSYNC_FORCE_L 0x00000040 97 #define PM2_VC_VSYNC_ACT_LOW 0x00000060 98 #define PM2_VC_BP_BASE_PENDING 0x00000080 99 #define PM2_VC_RE_BASE_PENDING 0x00000100 100 #define PM2_VC_SWAP_SYNC_BLANK 0x00000000 101 #define PM2_VC_SWAP_FREERUNNING 0x00000200 102 #define PM2_VC_SWAP_LIMIT_FR 0x00000400 103 #define PM2_VC_STEREO_ENABLE 0x00000800 104 #define PM2_VC_RIGHT_EYE_ACT_L 0x00001000 105 #define PM2_VC_DISP_RIGHT_FRAME 0x00002000 /* RO, left otherwise */ 106 #define PM2_VC_BP_RIGHT_PENDING 0x00004000 107 #define PM2_VC_RE_RIGHT_PENDING 0x00008000 108 #define PM2_VC_RAMDAC_64BIT 0x00010000 /* 32bit otherwise */ 109 110 #define PM2_DISPLAY_DATA 0x00003068 111 #define PM2_DD_SDA_IN 0x00000001 112 #define PM2_DD_SCL_IN 0x00000002 113 #define PM2_DD_SDA_OUT 0x00000004 114 #define PM2_DD_SCL_OUT 0x00000008 115 #define PM2_DD_LATCHED_DATA 0x00000010 116 #define PM2_DD_DATA_VALID 0x00000020 /* clear by 1 */ 117 #define PM2_DD_START 0x00000040 /* START detected */ 118 #define PM2_DD_STOP 0x00000080 /* STOP detected */ 119 #define PM2_DD_INSERT_WAITS 0x00000100 120 #define PM2_DD_USE_MONID 0x00000200 /* DDC2 otherwise */ 121 #define PM2_DD_MONID_IN_MASK 0x00001c00 122 #define PM2_DD_MONID_OUT_MASK 0x0000e000 123 124 /* RAMDAC */ 125 #define PM2_DAC_PAL_WRITE_IDX 0x00004000 126 #define PM2_DAC_DATA 0x00004008 127 #define PM2_DAC_MASK 0x00004010 128 #define PM2_DAC_PAL_READ_IDX 0x00004018 129 /* these are different on PM2V: */ 130 #define PM2_DAC_CURSOR_PAL 0x00004020 131 #define PM2_DAC_CURSOR_DATA 0x00004028 132 /* here we go: */ 133 #define PM2V_DAC_INDEX_LOW 0x00004020 134 #define PM2V_DAC_INDEX_HIGH 0x00004028 135 #define PM2V_DAC_INDEX_DATA 0x00004030 136 #define PM2V_DAC_INDEX_CONTROL 0x00004038 137 138 #define PM2_DAC_INDEX_DATA 0x00004050 139 #define PM2_DAC_CURSOR_RAM 0x00004058 140 #define PM2_DAC_CURSOR_X_LOW 0x00004060 141 #define PM2_DAC_CURSOR_X_HIGH 0x00004068 142 #define PM2_DAC_CURSOR_Y_LOW 0x00004070 143 #define PM2_DAC_CURSOR_Y_HIGH 0x00004078 144 145 /* RAMDAC registers ( through INDEX_DATA */ 146 #define PM2_DAC_COLOR_MODE 0x18 147 #define CM_PALETTE 0x00 148 #define CM_RGB332 0x01 149 #define CM_RGB232OFFSET 0x02 150 #define CM_RGBA2321 0x03 151 #define CM_RGBA5551 0x04 152 #define CM_RGBA4444 0x05 153 #define CM_RGB565 0x06 154 #define CM_RGBA8888 0x08 155 #define CM_RGB888 0x09 156 #define CM_GUI_ENABLE 0x10 157 #define CM_RGB 0x20 /* BGR otherwise */ 158 #define CM_TRUECOLOR 0x80 /* use palette for gamma correction */ 159 #define PM2_DAC_MODE_CONTROL 0x19 160 #define MOC_BUFFERFRONT 0x00 161 162 #define PM2_DAC_MISC_CONTROL 0x1e 163 #define MC_POWERDOWN 0x01 164 #define MC_PALETTE_8BIT 0x02 /* 6bit otherwise */ 165 #define MC_HSYNC_INV 0x04 166 #define MC_VSYNC_INV 0x08 167 #define MC_SYNCONGREEN 0x10 168 #define PM2_DAC_PIXELCLKA_M 0x20 169 #define PM2_DAC_PIXELCLKA_N 0x21 170 #define PM2_DAC_PIXELCLKA_P 0x22 171 #define PCLK_ENABLE 0x08 172 #define PM2_DAC_PIXELCLKB_M 0x23 173 #define PM2_DAC_PIXELCLKB_N 0x24 174 #define PM2_DAC_PIXELCLKB_P 0x25 175 #define PM2_DAC_PIXELCLKC_M 0x26 176 #define PM2_DAC_PIXELCLKC_N 0x27 177 #define PM2_DAC_PIXELCLKC_P 0x28 178 #define PM2_DAC_PIXELCLK_STATUS 0x29 179 #define PCLK_LOCKED 0x10 180 #define PM2_DAC_MEMCLK_M 0x30 181 #define PM2_DAC_MEMCLK_N 0x31 182 #define PM2_DAC_MEMCLK_P 0x32 183 #define PM2_DAC_MEMCLK_STATUS 0x33 184 185 /* PM2V RAMDAC */ 186 #define PM2V_DAC_MISC_CONTROL 0x000 187 #define PM2V_DAC_8BIT 0x01 /* 6bit otherwise */ 188 #define PM2V_DAC_BYPASS_CLUT 0x08 /* ??? guess from xorg */ 189 #define PM2V_DAC_8_24_OVERLAY 0x10 /* ??? guess from xorg */ 190 #define PM2V_DAC_SYNC_CONTROL 0x001 191 #define PM2V_DAC_HSYNC_INV 0x01 192 #define PM2V_DAC_VSYNC_INV 0x08 193 #define PM2V_DAC_CONTROL 0x002 194 #define PM2V_DAC_PIXEL_SIZE 0x003 195 #define PM2V_PS_8BIT 0x00 196 #define PM2V_PS_16BIT 0x01 197 #define PM2V_PS_32BIT 0x02 198 #define PM2V_PS_24BIT 0x04 199 #define PM2V_DAC_COLOR_FORMAT 0x004 200 #define PM2V_DAC_PALETTE 0x2e 201 #define PM2V_DAC_RGB555 0x61 202 #define PM2V_DAC_RGB565 0x70 203 #define PM2V_DAC_RGB888 0x60 204 #define PM2V_DAC_RGBA8888 0x20 205 206 #define PM2V_DAC_CHECK_CONTROL 0x018 207 #define PM2V_DAC_CLOCK_CONTROL 0x200 208 #define PM2V_DAC_CLOCK_A_M 0x201 209 #define PM2V_DAC_CLOCK_A_N 0x202 210 #define PM2V_DAC_CLOCK_A_P 0x203 211 #define PM2V_DAC_CLOCK_B_M 0x204 212 #define PM2V_DAC_CLOCK_B_N 0x205 213 #define PM2V_DAC_CLOCK_B_P 0x206 214 #define PM2V_DAC_MCLK_CONTROL 0x20D 215 #define PM2V_DAC_MCLK_M 0x20E 216 #define PM2V_DAC_MCLK_N 0x20F 217 #define PM2V_DAC_MCLK_P 0x210 218 219 /* drawing engine */ 220 #define PM2_RE_STARTXDOM 0x00008000 221 #define PM2_RE_DXDOM 0x00008008 222 #define PM2_RE_STARTXSUB 0x00008010 223 #define PM2_RE_STARTY 0x00008020 224 #define PM2_RE_DY 0x00008028 225 #define PM2_RE_COUNT 0x00008030 226 #define PM2_RE_BITMASK 0x00008068 /* for colour expansion */ 227 #define PM2_RE_COLOUR 0x000087f0 228 #define PM2_RE_CONFIG 0x00008d90 229 #define PM2RECFG_READ_SRC 0x00000001 230 #define PM2RECFG_READ_DST 0x00000002 231 #define PM2RECFG_PACKED 0x00000004 232 #define PM2RECFG_WRITE_EN 0x00000008 233 #define PM2RECFG_DDA_EN 0x00000010 234 #define PM2RECFG_ROP_EN 0x00000020 235 #define PM2RECFG_ROP_MASK 0x000003c0 236 #define PM2RECFG_ROP_SHIFT 6 237 238 #define PM2_RE_CONST_COLOUR 0x000087e8 239 #define PM2_RE_BUFFER_OFFSET 0x00008a90 /* distance between src and dst */ 240 #define PM2_RE_SOURCE_BASE 0x00008d80 /* write after windowbase */ 241 #define PM2_RE_SOURCE_DELTA 0x00008d88 /* offset in coordinates */ 242 #define PM2_RE_SOURCE_OFFSET 0x00008a88 /* same in pixels */ 243 #define PM2_RE_WINDOW_BASE 0x00008ab0 244 #define PM2_RE_WINDOW_ORIGIN 0x000081c8 245 #define PM2_RE_WRITE_MODE 0x00008ab8 246 #define PM2WM_WRITE_EN 0x00000001 247 #define PM2WM_TO_HOST 0x00000008 248 #define PM2_RE_PIXEL_SIZE 0x00008ad0 249 #define PM2PS_8BIT 0x00000000 250 #define PM2PS_16BIT 0x00000001 251 #define PM2PS_32BIT 0x00000002 252 #define PM2PS_24BIT 0x00000004 253 254 #define PM2_RE_MODE 0x000080a0 255 #define PM2RM_MASK_MIRROR 0x00000001 /* mask is right-to-left */ 256 #define PM2RM_MASK_INVERT 0x00000002 257 #define PM2RM_MASK_OPAQUE 0x00000040 /* BG in TEXEL0 */ 258 #define PM2RM_MASK_SWAP 0x00000180 259 #define PM2RM_MASK_PAD 0x00000200 /* new line new mask */ 260 #define PM2RM_MASK_OFFSET 0x00007c00 261 #define PM2RM_HOST_SWAP 0x00018000 262 #define PM2RM_LIMITS_EN 0x00040000 263 #define PM2RM_MASK_REL_X 0x00080000 264 265 #define PM2_RE_RECT_START 0x000080d0 266 #define PM2_RE_RECT_SIZE 0x000080d8 267 #define PM2_RE_RENDER 0x00008038 /* write starts command */ 268 #define PM2RE_STIPPLE 0x00000001 269 #define PM2RE_FASTFILL 0x00000008 270 #define PM2RE_LINE 0x00000000 271 #define PM2RE_TRAPEZOID 0x00000040 272 #define PM2RE_POINT 0x00000080 273 #define PM2RE_RECTANGLE 0x000000c0 274 #define PM2RE_SYNC_ON_MASK 0x00000800 /* wait for write to bitmask 275 register */ 276 #define PM2RE_SYNC_ON_HOST 0x00001000 /* wait for host data */ 277 #define PM2RE_TEXTURE_EN 0x00002000 278 #define PM2RE_INC_X 0x00200000 /* drawing direction */ 279 #define PM2RE_INC_Y 0x00400000 280 #define PM2_RE_TEXEL0 0x00008600 /* background colour */ 281 #define PM2_RE_STATUS 0x00000068 282 #define PM2ST_BUSY 0x80000000 283 #define PM2_RE_SYNC 0x00008c40 284 #define PM2_RE_FILTER_MODE 0x00008c00 285 #define PM2FLT_PASS_SYNC 0x00000400 286 #define PM2_RE_DDA_MODE 0x000087e0 287 #define PM2DDA_ENABLE 0x00000001 288 #define PM2DDA_GOURAUD 0x00000002 /* flat otherwise */ 289 #define PM2_RE_BLOCK_COLOUR 0x00008ac8 290 #define PM2_RE_STIPPLE_MODE 0x000081a0 291 #define PM2ST_ENABLE 0x00000001 292 #define PM2ST_XOFFSET_MASK 0x00000380 293 #define PM2ST_YOFFSET_MASK 0x00007000 294 #define PM2ST_INVERT 0x00020000 295 #define PM2ST_MIRROR_X 0x00040000 296 #define PM2ST_MIRROR_Y 0x00080000 297 #define PM2ST_OPAQUE 0x00100000 298 #define PM2_HW_WRITEMASK 0x00008ac0 299 #define PM2_SW_WRITEMASK 0x00008820 300 #define PM2_FB_READMODE 0x00008a80 301 #define PM2FB_PP0_MASK 0x00000007 302 #define PM2FB_PP1_MASK 0x00000038 303 #define PM2FB_PP2_MASK 0x000001c0 304 #define PM2FB_READ_SRC 0x00000200 305 #define PM2FB_READ_DST 0x00000400 306 #define PM2FB_FBCOLOR 0x00008000 /* for uploads */ 307 #define PM2FB_ORIGIN_BL 0x00010000 /* window origin, TL otherwise */ 308 #define PM2FB_PATCH_EN 0x00020000 309 #define PM2FB_PACKED 0x00040000 310 #define PM2FB_OFFSET_M 0x00380000 311 #define PM2FB_PM_PATCH 0x00000000 312 #define PM2FB_PM_SUB 0x02000000 313 #define PM2FB_PM_SUBP 0x04000000 314 315 #define PM2_RE_SCISSOR_MODE 0x00008180 316 #define PM2SC_USER_EN 0x00000001 /* from scissor reg */ 317 #define PM2SC_SCREEN_EN 0x00000002 /* screensize reg */ 318 #define PM2_RE_SCREENSIZE 0x00008198 319 #define PM2_RE_SCISSOR_MINYX 0x00008188 320 #define PM2_RE_SCISSOR_MAXYX 0x00008190 321 #define PM2_RE_TEXMAP_FORMAT 0x00008588 322 /* format to write into the framebuffer */ 323 #define PM2_RE_DITHER_MODE 0x00008818 324 #define PM2DM_ENABLE 0x00000001 325 #define PM2DM_DITHER_ENABLE 0x00000002 326 #define PM2DM_COLOUR_FORMAT_M 0x0000003c 327 #define PM2DM_8888 0x00000000 328 #define PM2DM_5551F 0x00000004 329 #define PM2DM_4444 0x00000008 330 #define PM2DM_332F 0x00000014 331 #define PM2DM_332B 0x00000018 332 #define PM2DM_2321F 0x00000024 333 #define PM2DM_2321B 0x00000028 334 #define PM2DM_232FO 0x0000002c 335 #define PM2DM_232BO 0x00000030 336 #define PM2DM_5551B 0x00000034 337 #define PM2DM_CI8 0x00000038 338 #define PM2DM_565F 0x00010000 /* XXX */ 339 #define PM2DM_565B 0x00010004 /* XXX */ 340 #define PM2DM_X_OFFSET_M 0x000000c0 341 #define PM2DM_Y_OFFSET_M 0x00000300 342 #define PM2DM_RGB 0x00000400 /* BGR otherwise */ 343 #define PM2DM_LINE 0x00000800 /* ordered otherw. */ 344 #define PM2DM_FORCE_ALPHA_0 0x00001000 345 #define PM2DM_FORCE_ALPHA_F8 0x00002000 346 #define PM2DM_COLOUR_FORMAT_X 0x00010000 /* upper bit */ 347 348 #define PM2_RE_ALPHA_MODE 0x00008810 349 #define PM2AL_ENABLE 0x00000001 350 #define PM2AL_OPERATION_MASK 0x000000fe 351 #define PM2AL_OP_SRC_IS_ZERO 0x00000000 352 #define PM2AL_OP_SRC_IS_ONE 0x00000002 353 #define PM2AL_OP_SRC_IS_DST_COLOR 0x00000004 354 #define PM2AL_OP_SRC_IS_ONE_MINUS_DST_COLOR 0x00000006 355 #define PM2AL_OP_SRC_IS_SRC_ALPHA 0x00000008 356 #define PM2AL_OP_SRC_IS_ONE_MINUS_SRC_ALPHA 0x0000000a 357 #define PM2AL_OP_SRC_IS_DST_ALPHA 0x0000000c 358 #define PM2AL_OP_SRC_IS_ONE_MINUS_DST_ALPHA 0x0000000e 359 #define PM2AL_OP_SRC_IS_SRC_ALPHA_SATURATE 0x00000010 360 #define PM2AL_OP_DST_IS_ZERO 0x00000000 361 #define PM2AL_OP_DST_IS_ONE 0x00000020 362 #define PM2AL_OP_DST_IS_SRC_COLOR 0x00000040 363 #define PM2AL_OP_DST_IS_ONE_MINUS_SRC_COLOR 0x00000060 364 #define PM2AL_OP_DST_IS_SRC_ALPHA 0x00000080 365 #define PM2AL_OP_DST_IS_ONE_MINUS_SRC_ALPHA 0x000000a0 366 #define PM2AL_OP_DST_IS_DST_ALPHA 0x000000c0 367 #define PM2AL_OP_DST_IS_ONE_MINUS_DST_ALPHA 0x000000e0 368 /* 369 * XXX 370 * format of incoming data 371 * the 5th bit is in bit 16 372 */ 373 #define PM2AL_COLOUR_FORMAT_M 0x00000f00 374 #define PM2AL_8888 0x00000000 375 #define PM2AL_5551F 0x00000100 376 #define PM2AL_4444 0x00000200 377 #define PM2AL_332F 0x00000500 378 #define PM2AL_332B 0x00000600 379 #define PM2AL_2321F 0x00000900 380 #define PM2AL_2321B 0x00000a00 381 #define PM2AL_232FO 0x00000b00 382 #define PM2AL_232BO 0x00000c00 383 #define PM2AL_5551B 0x00000d00 384 #define PM2AL_CI8 0x00000e00 385 #define PM2AL_565F 0x00010000 /* XXX */ 386 #define PM2AL_565B 0x00010100 /* XXX */ 387 #define PM2AL_NO_ALPHA 0x00001000 /* XXX */ 388 #define PM2AL_RGB 0x00002000 /* BGR otherwise */ 389 #define PM2AL_RAMP 0x00004000 /* RGB otherwise */ 390 #define PM2AL_COLOUR_FORMAT_X 0x00010000 391 #define PM2AL_COLOUR_CONV_SHIFT 0x00020000 /* scale otherwise */ 392 #define PM2AL_ALPHA_CONV_SHIFT 0x00040000 /* scale otherwise */ 393 #define PM2_RE_TEX_COLOUR_MODE 0x00008680 394 #define PM2_RE_TEX_READ_MODE 0x00008670 395 #define PM2_RE_TEX_LUT_MODE 0x00008678 396 #define PM2_RE_TEX_ADDRESS_MODE 0x00008380 397 #define PM2_RE_YUV_MODE 0x00008f00 398 #define PM2_RE_DEPTH_MODE 0x000089a0 399 #define PM2_RE_DEPTH 0x000089a8 400 #define PM2_RE_STENCIL_MODE 0x00008988 401 #define PM2_RE_ROP_MODE 0x00008828 402 #define PM2_RE_PACKEDDATA_LIMIT 0x00008150 403 #define PM2_RE_DATA 0x00008aa0 /* pixel data */ 404 #define PM2_RE_SOURCEDATA 0x00008aa8 /* raw data */ 405 406 #define PM2_SYNC_TAG 0x188 407 #endif /* PM2_REG_H */ 408
Indexes created Tue Sep 23 23:09:58 GMT 2025