pm2reg.h revision 1.1
1 /* $NetBSD: pm2reg.h,v 1.1 2009/10/28 02:10:27 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * register definitions for Permedia 2 graphics controllers 30 */ 31 32 33 #ifndef PM2_REG_H 34 #define PM2_REG_H 35 36 #define PM2_RESET 0x00000000 /* any write initiates a chip reset */ 37 #define PM2_RESET_BUSY 0x80000000 /* reset in progress */ 38 39 #define PM2_INPUT_FIFO_SPACE 0x00000018 40 #define PM2_OUTPUT_FIFO_WORDS 0x00000020 41 42 #define PM2_APERTURE1_CONTROL 0x00000050 43 #define PM2_APERTURE2_CONTROL 0x00000058 44 #define PM2_AP_BYTESWAP 0x00000001 45 #define PM2_AP_HALFWORDSWAP 0x00000002 46 #define PM2_AP_PACKED16_EN 0x00000008 47 #define PM2_AP_PACKED16_READ_B 0x00000010 /* Buffer A otherwise */ 48 #define PM2_AP_PACKED16_WRITE_B 0x00000020 /* A otherwise */ 49 #define PM2_AP_PACKED16_WRT_DBL 0x00000040 50 #define PM2_AP_PACKED16_R31 0x00000080 /* read buffer selected by 51 * visibility bit in memory 52 */ 53 #define PM2_AP_SVGA 0x00000100 54 #define PM2_AP_ROM 0x00000200 55 56 #define PM2_BYPASS_MASK 0x00001100 57 #define PM2_FB_WRITE_MASK 0x00001140 58 59 #define PM2_OUTPUT_FIFO 0x00002000 60 61 #define PM2_SCREEN_BASE 0x00003000 /* in 64bit units */ 62 #define PM2_SCREEN_STRIDE 0x00003008 /* in 64bit units */ 63 64 /* RAMDAC */ 65 #define PM2_DAC_PAL_WRITE_IDX 0x00004000 66 #define PM2_DAC_DATA 0x00004008 67 #define PM2_DAC_MASK 0x00004010 68 #define PM2_DAC_PAL_READ 0x00004018 69 #define PM2_DAC_CURSOR_PAL 0x00004020 70 #define PM2_DAC_CURSOR_DATA 0x00004028 71 #define PM2_DAC_INDEX_DATA 0x00004050 72 #define PM2_DAC_CURSOR_RAM 0x00004058 73 #define PM2_DAC_CURSOR_X_LOW 0x00004060 74 #define PM2_DAC_CURSOR_X_HIGH 0x00004068 75 #define PM2_DAC_CURSOR_Y_LOW 0x00004070 76 #define PM2_DAC_CURSOR_Y_HIGH 0x00004078 77 78 /* drawing engine */ 79 #define PM2_RE_BITMASK 0x00008068 /* for colour expansion */ 80 #define PM2_RE_COLOUR 0x000087f0 81 #define PM2_RE_CONFIG 0x00008d90 82 #define PM2RECFG_READ_SRC 0x00000001 83 #define PM2RECFG_READ_DST 0x00000002 84 #define PM2RECFG_PACKED 0x00000004 85 #define PM2RECFG_WRITE_EN 0x00000008 86 #define PM2RECFG_DDA_EN 0x00000010 87 #define PM2RECFG_ROP_EN 0x00000020 88 #define PM2RECFG_ROP_MASK 0x000003c0 89 #define PM2RECFG_ROP_SHIFT 6 90 91 #define PM2_RE_CONST_COLOUR 0x000087e8 92 #define PM2_RE_BUFFER_OFFSET 0x00008a90 /* distance between src and dst */ 93 #define PM2_RE_SOURCE_BASE 0x00008d80 /* write after windowbase */ 94 #define PM2_RE_SOURCE_DELTA 0x00008d88 /* offset in coordinates */ 95 #define PM2_RE_SOURCE_OFFSET 0x00008a88 /* same in pixels */ 96 #define PM2_RE_WINDOW_BASE 0x00008ab0 97 #define PM2_RE_WRITE_MODE 0x00008ab8 98 #define PM2WM_WRITE_EN 0x00000001 99 #define PM2WM_TO_HOST 0x00000008 100 101 #define PM2_RE_MODE 0x000080a0 102 #define PM2RM_MASK_MIRROR 0x00000001 /* mask is right-to-left */ 103 #define PM2RM_MASK_INVERT 104 #define PM2RM_MASK_OPAQUE 0x00000040 /* BG in TEXEL0 */ 105 #define PM2RM_MASK_SWAP 0x00000180 106 #define PM2RM_MASK_PAD 0x00000200 /* new line new mask */ 107 #define PM2RM_MASK_OFFSET 0x00007c00 108 #define PM2RM_HOST_SWAP 0x00018000 109 #define PM2RM_LIMITS_EN 0x00040000 110 #define PM2RM_MASK_REL_X 0x00080000 111 112 #define PM2_RE_RECT_START 0x000080d0 113 #define PM2_RE_RECT_SIZE 0x000080d8 114 #define PM2_RE_RENDER 0x00008038 /* write starts command */ 115 #define PM2RE_STIPPLE 0x00000001 116 #define PM2RE_FASTFILL 0x00000008 117 #define PM2RE_LINE 0x00000000 118 #define PM2RE_TRAPEZOID 0x00000040 119 #define PM2RE_POINT 0x00000080 120 #define PM2RE_RECTANGLE 0x000000c0 121 #define PM2RE_SYNC_ON_MASK 0x00000800 /* wait for write to bitmask 122 register */ 123 #define PM2RE_SYNC_ON_HOST 0x00001000 /* wait for host data */ 124 #define PM2RE_TEXTURE_EN 0x00002000 125 #define PM2RE_INC_X 0x00200000 /* drawing direction */ 126 #define PM2RE_INC_Y 0x00400000 127 #define PM2_RE_TEXEL0 0x00008600 /* background colour */ 128 #define PM2_RE_STATUS 0x00000068 129 #define PM2ST_BUSY 0x80000000 130 #define PM2_RE_SYNC 0x00008c40 131 #define PM2_RE_FILTER_MODE 0x00008c00 132 #define PM2FLT_PASS_SYNC 0x00000400 133 #endif /* PM2_REG_H */ 134
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