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ppb.c revision 1.51
      1  1.51      yamt /*	$NetBSD: ppb.c,v 1.51 2013/03/06 11:50:32 yamt Exp $	*/
      2   1.1       cgd 
      3   1.1       cgd /*
      4  1.17       cgd  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
      5   1.1       cgd  *
      6   1.1       cgd  * Redistribution and use in source and binary forms, with or without
      7   1.1       cgd  * modification, are permitted provided that the following conditions
      8   1.1       cgd  * are met:
      9   1.1       cgd  * 1. Redistributions of source code must retain the above copyright
     10   1.1       cgd  *    notice, this list of conditions and the following disclaimer.
     11   1.1       cgd  * 2. Redistributions in binary form must reproduce the above copyright
     12   1.1       cgd  *    notice, this list of conditions and the following disclaimer in the
     13   1.1       cgd  *    documentation and/or other materials provided with the distribution.
     14   1.1       cgd  * 3. All advertising materials mentioning features or use of this software
     15   1.1       cgd  *    must display the following acknowledgement:
     16   1.1       cgd  *      This product includes software developed by Christopher G. Demetriou
     17   1.1       cgd  *	for the NetBSD Project.
     18   1.1       cgd  * 4. The name of the author may not be used to endorse or promote products
     19   1.1       cgd  *    derived from this software without specific prior written permission
     20   1.1       cgd  *
     21   1.1       cgd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22   1.1       cgd  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23   1.1       cgd  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24   1.1       cgd  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25   1.1       cgd  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26   1.1       cgd  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27   1.1       cgd  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28   1.1       cgd  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29   1.1       cgd  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30   1.1       cgd  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31   1.1       cgd  */
     32  1.20     lukem 
     33  1.20     lukem #include <sys/cdefs.h>
     34  1.51      yamt __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.51 2013/03/06 11:50:32 yamt Exp $");
     35   1.1       cgd 
     36   1.1       cgd #include <sys/param.h>
     37   1.1       cgd #include <sys/systm.h>
     38   1.1       cgd #include <sys/kernel.h>
     39   1.1       cgd #include <sys/device.h>
     40   1.1       cgd 
     41   1.1       cgd #include <dev/pci/pcireg.h>
     42   1.1       cgd #include <dev/pci/pcivar.h>
     43   1.1       cgd #include <dev/pci/ppbreg.h>
     44  1.36  jmcneill #include <dev/pci/pcidevs.h>
     45   1.1       cgd 
     46  1.44  jmcneill #define	PCI_PCIE_SLCSR_NOTIFY_MASK					\
     47  1.44  jmcneill 	(PCI_PCIE_SLCSR_ABE | PCI_PCIE_SLCSR_PFE | PCI_PCIE_SLCSR_MSE |	\
     48  1.44  jmcneill 	 PCI_PCIE_SLCSR_PDE | PCI_PCIE_SLCSR_CCE | PCI_PCIE_SLCSR_HPE)
     49  1.44  jmcneill 
     50  1.21   thorpej struct ppb_softc {
     51  1.39    cegger 	device_t sc_dev;		/* generic device glue */
     52  1.21   thorpej 	pci_chipset_tag_t sc_pc;	/* our PCI chipset... */
     53  1.21   thorpej 	pcitag_t sc_tag;		/* ...and tag. */
     54  1.36  jmcneill 
     55  1.36  jmcneill 	pcireg_t sc_pciconfext[48];
     56  1.21   thorpej };
     57  1.21   thorpej 
     58  1.50      matt static const char pcie_linkspeed_strings[4][5] = {
     59  1.50      matt 	"1.25", "2.5", "5.0", "8.0",
     60  1.50      matt };
     61  1.50      matt 
     62  1.42    dyoung static bool		ppb_resume(device_t, const pmf_qual_t *);
     63  1.42    dyoung static bool		ppb_suspend(device_t, const pmf_qual_t *);
     64  1.36  jmcneill 
     65  1.31   thorpej static int
     66  1.39    cegger ppbmatch(device_t parent, cfdata_t match, void *aux)
     67   1.1       cgd {
     68   1.1       cgd 	struct pci_attach_args *pa = aux;
     69   1.1       cgd 
     70   1.1       cgd 	/*
     71   1.1       cgd 	 * Check the ID register to see that it's a PCI bridge.
     72   1.1       cgd 	 * If it is, we assume that we can deal with it; it _should_
     73   1.1       cgd 	 * work in a standardized way...
     74   1.1       cgd 	 */
     75   1.1       cgd 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
     76   1.1       cgd 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI)
     77  1.39    cegger 		return 1;
     78   1.1       cgd 
     79  1.43      matt #ifdef __powerpc__
     80  1.43      matt 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PROCESSOR &&
     81  1.43      matt 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PROCESSOR_POWERPC) {
     82  1.43      matt 		pcireg_t bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag,
     83  1.43      matt 		    PCI_BHLC_REG);
     84  1.43      matt 		if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_FREESCALE
     85  1.43      matt 		    && PCI_HDRTYPE(bhlc) == PCI_HDRTYPE_RC)
     86  1.43      matt 		return 1;
     87  1.43      matt 	}
     88  1.43      matt #endif
     89  1.43      matt 
     90  1.50      matt #ifdef _MIPS_PADDR_T_64BIT
     91  1.50      matt 	/* The LDT HB acts just like a PPB.  */
     92  1.50      matt 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIBYTE
     93  1.50      matt 	    && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIBYTE_BCM1250_LDTHB)
     94  1.50      matt 		return 1;
     95  1.50      matt #endif
     96  1.50      matt 
     97  1.39    cegger 	return 0;
     98   1.1       cgd }
     99   1.1       cgd 
    100  1.31   thorpej static void
    101  1.44  jmcneill ppb_fix_pcie(device_t self)
    102  1.35     joerg {
    103  1.36  jmcneill 	struct ppb_softc *sc = device_private(self);
    104  1.35     joerg 	pcireg_t reg;
    105  1.35     joerg 	int off;
    106  1.35     joerg 
    107  1.36  jmcneill 	if (!pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS,
    108  1.35     joerg 				&off, &reg))
    109  1.35     joerg 		return; /* Not a PCIe device */
    110  1.35     joerg 
    111  1.44  jmcneill 	aprint_normal_dev(self, "PCI Express ");
    112  1.44  jmcneill 	switch (reg & PCI_PCIE_XCAP_VER_MASK) {
    113  1.44  jmcneill 	case PCI_PCIE_XCAP_VER_1_0:
    114  1.44  jmcneill 		aprint_normal("1.0");
    115  1.45    cegger 		break;
    116  1.44  jmcneill 	case PCI_PCIE_XCAP_VER_2_0:
    117  1.44  jmcneill 		aprint_normal("2.0");
    118  1.44  jmcneill 		break;
    119  1.44  jmcneill 	default:
    120  1.46    dyoung 		aprint_normal_dev(self,
    121  1.46    dyoung 		    "version unsupported (0x%" PRIxMAX ")\n",
    122  1.46    dyoung 		    __SHIFTOUT(reg, PCI_PCIE_XCAP_VER_MASK));
    123  1.35     joerg 		return;
    124  1.35     joerg 	}
    125  1.44  jmcneill 	aprint_normal(" <");
    126  1.44  jmcneill 	switch (reg & PCI_PCIE_XCAP_TYPE_MASK) {
    127  1.44  jmcneill 	case PCI_PCIE_XCAP_TYPE_PCIE_DEV:
    128  1.44  jmcneill 		aprint_normal("PCI-E Endpoint device");
    129  1.44  jmcneill 		break;
    130  1.44  jmcneill 	case PCI_PCIE_XCAP_TYPE_PCI_DEV:
    131  1.44  jmcneill 		aprint_normal("Legacy PCI-E Endpoint device");
    132  1.44  jmcneill 		break;
    133  1.44  jmcneill 	case PCI_PCIE_XCAP_TYPE_ROOT:
    134  1.44  jmcneill 		aprint_normal("Root Port of PCI-E Root Complex");
    135  1.44  jmcneill 		break;
    136  1.44  jmcneill 	case PCI_PCIE_XCAP_TYPE_UP:
    137  1.44  jmcneill 		aprint_normal("Upstream Port of PCI-E Switch");
    138  1.44  jmcneill 		break;
    139  1.44  jmcneill 	case PCI_PCIE_XCAP_TYPE_DOWN:
    140  1.44  jmcneill 		aprint_normal("Downstream Port of PCI-E Switch");
    141  1.44  jmcneill 		break;
    142  1.44  jmcneill 	case PCI_PCIE_XCAP_TYPE_PCIE2PCI:
    143  1.44  jmcneill 		aprint_normal("PCI-E to PCI/PCI-X Bridge");
    144  1.44  jmcneill 		break;
    145  1.44  jmcneill 	case PCI_PCIE_XCAP_TYPE_PCI2PCIE:
    146  1.44  jmcneill 		aprint_normal("PCI/PCI-X to PCI-E Bridge");
    147  1.44  jmcneill 		break;
    148  1.44  jmcneill 	default:
    149  1.46    dyoung 		aprint_normal("Device/Port Type 0x%" PRIxMAX,
    150  1.46    dyoung 		    __SHIFTOUT(reg, PCI_PCIE_XCAP_TYPE_MASK));
    151  1.44  jmcneill 		break;
    152  1.44  jmcneill 	}
    153  1.50      matt 
    154  1.50      matt 	switch (reg & PCI_PCIE_XCAP_TYPE_MASK) {
    155  1.50      matt 	case PCI_PCIE_XCAP_TYPE_ROOT:
    156  1.50      matt 	case PCI_PCIE_XCAP_TYPE_DOWN:
    157  1.50      matt 	case PCI_PCIE_XCAP_TYPE_PCI2PCIE:
    158  1.50      matt 		reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x0c);
    159  1.50      matt 		u_int mlw = (reg >> 4) & 0x1f;
    160  1.50      matt 		u_int mls = (reg >> 0) & 0x0f;
    161  1.50      matt 		if (mls < __arraycount(pcie_linkspeed_strings)) {
    162  1.50      matt 			aprint_normal("> x%d @ %sGb/s\n",
    163  1.50      matt 			    mlw, pcie_linkspeed_strings[mls]);
    164  1.50      matt 		} else {
    165  1.50      matt 			aprint_normal("> x%d @ %d.%dGb/s\n",
    166  1.50      matt 			    mlw, (mls * 25) / 10, (mls * 25) % 10);
    167  1.50      matt 		}
    168  1.50      matt 
    169  1.50      matt 		reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x10);
    170  1.50      matt 		if (reg & __BIT(29)) {	/* DLLA */
    171  1.50      matt 			u_int lw = (reg >> 20) & 0x1f;
    172  1.50      matt 			u_int ls = (reg >> 16) & 0x0f;
    173  1.50      matt 			if (lw != mlw || ls != mls) {
    174  1.50      matt 				if (ls < __arraycount(pcie_linkspeed_strings)) {
    175  1.51      yamt 					aprint_normal_dev(self,
    176  1.51      yamt 					    "link is x%d @ %sGb/s\n",
    177  1.50      matt 					    lw, pcie_linkspeed_strings[ls]);
    178  1.50      matt 				} else {
    179  1.50      matt 					aprint_normal_dev(self,
    180  1.50      matt 					    "link is x%d @ %d.%dGb/s\n",
    181  1.50      matt 					    lw, (ls * 25) / 10, (ls * 25) % 10);
    182  1.50      matt 				}
    183  1.50      matt 			}
    184  1.50      matt 		}
    185  1.50      matt 		break;
    186  1.50      matt 	default:
    187  1.50      matt 		aprint_normal(">\n");
    188  1.50      matt 		break;
    189  1.50      matt 	}
    190  1.44  jmcneill 
    191  1.44  jmcneill 	reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCI_PCIE_SLCSR);
    192  1.44  jmcneill 	if (reg & PCI_PCIE_SLCSR_NOTIFY_MASK) {
    193  1.44  jmcneill 		aprint_debug_dev(self, "disabling notification events\n");
    194  1.44  jmcneill 		reg &= ~PCI_PCIE_SLCSR_NOTIFY_MASK;
    195  1.44  jmcneill 		pci_conf_write(sc->sc_pc, sc->sc_tag,
    196  1.44  jmcneill 		    off + PCI_PCIE_SLCSR, reg);
    197  1.35     joerg 	}
    198  1.35     joerg }
    199  1.35     joerg 
    200  1.35     joerg static void
    201  1.37    dyoung ppbattach(device_t parent, device_t self, void *aux)
    202   1.1       cgd {
    203  1.37    dyoung 	struct ppb_softc *sc = device_private(self);
    204   1.1       cgd 	struct pci_attach_args *pa = aux;
    205   1.7       cgd 	pci_chipset_tag_t pc = pa->pa_pc;
    206   1.1       cgd 	struct pcibus_attach_args pba;
    207   1.7       cgd 	pcireg_t busdata;
    208   1.1       cgd 
    209  1.49  drochner 	pci_aprint_devinfo(pa, NULL);
    210   1.1       cgd 
    211  1.21   thorpej 	sc->sc_pc = pc;
    212  1.21   thorpej 	sc->sc_tag = pa->pa_tag;
    213  1.39    cegger 	sc->sc_dev = self;
    214  1.21   thorpej 
    215   1.7       cgd 	busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
    216   1.1       cgd 
    217   1.7       cgd 	if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
    218  1.37    dyoung 		aprint_normal_dev(self, "not configured by system firmware\n");
    219   1.1       cgd 		return;
    220   1.1       cgd 	}
    221   1.1       cgd 
    222  1.44  jmcneill 	ppb_fix_pcie(self);
    223  1.35     joerg 
    224   1.1       cgd #if 0
    225   1.1       cgd 	/*
    226   1.1       cgd 	 * XXX can't do this, because we're not given our bus number
    227   1.7       cgd 	 * (we shouldn't need it), and because we've no way to
    228   1.7       cgd 	 * decompose our tag.
    229   1.1       cgd 	 */
    230   1.1       cgd 	/* sanity check. */
    231   1.7       cgd 	if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
    232   1.1       cgd 		panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
    233   1.7       cgd 		    pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
    234   1.1       cgd #endif
    235   1.1       cgd 
    236  1.36  jmcneill 	if (!pmf_device_register(self, ppb_suspend, ppb_resume))
    237  1.36  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
    238  1.36  jmcneill 
    239   1.1       cgd 	/*
    240   1.1       cgd 	 * Attach the PCI bus than hangs off of it.
    241  1.19   thorpej 	 *
    242  1.19   thorpej 	 * XXX Don't pass-through Memory Read Multiple.  Should we?
    243  1.19   thorpej 	 * XXX Consult the spec...
    244   1.1       cgd 	 */
    245  1.12   thorpej 	pba.pba_iot = pa->pa_iot;
    246  1.12   thorpej 	pba.pba_memt = pa->pa_memt;
    247  1.15   mycroft 	pba.pba_dmat = pa->pa_dmat;
    248  1.26      fvdl 	pba.pba_dmat64 = pa->pa_dmat64;
    249   1.7       cgd 	pba.pba_pc = pc;
    250  1.19   thorpej 	pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
    251   1.7       cgd 	pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
    252  1.47    dyoung 	pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata);
    253  1.21   thorpej 	pba.pba_bridgetag = &sc->sc_tag;
    254   1.7       cgd 	pba.pba_intrswiz = pa->pa_intrswiz;
    255   1.7       cgd 	pba.pba_intrtag = pa->pa_intrtag;
    256   1.1       cgd 
    257  1.29  drochner 	config_found_ia(self, "pcibus", &pba, pcibusprint);
    258   1.1       cgd }
    259  1.31   thorpej 
    260  1.37    dyoung static int
    261  1.37    dyoung ppbdetach(device_t self, int flags)
    262  1.37    dyoung {
    263  1.37    dyoung 	int rc;
    264  1.37    dyoung 
    265  1.37    dyoung 	if ((rc = config_detach_children(self, flags)) != 0)
    266  1.37    dyoung 		return rc;
    267  1.37    dyoung 	pmf_device_deregister(self);
    268  1.37    dyoung 	return 0;
    269  1.37    dyoung }
    270  1.37    dyoung 
    271  1.36  jmcneill static bool
    272  1.42    dyoung ppb_resume(device_t dv, const pmf_qual_t *qual)
    273  1.36  jmcneill {
    274  1.36  jmcneill 	struct ppb_softc *sc = device_private(dv);
    275  1.36  jmcneill 	int off;
    276  1.36  jmcneill 	pcireg_t val;
    277  1.36  jmcneill 
    278  1.36  jmcneill         for (off = 0x40; off <= 0xff; off += 4) {
    279  1.36  jmcneill 		val = pci_conf_read(sc->sc_pc, sc->sc_tag, off);
    280  1.36  jmcneill 		if (val != sc->sc_pciconfext[(off - 0x40) / 4])
    281  1.36  jmcneill 			pci_conf_write(sc->sc_pc, sc->sc_tag, off,
    282  1.36  jmcneill 			    sc->sc_pciconfext[(off - 0x40)/4]);
    283  1.36  jmcneill 	}
    284  1.36  jmcneill 
    285  1.44  jmcneill 	ppb_fix_pcie(dv);
    286  1.36  jmcneill 
    287  1.36  jmcneill 	return true;
    288  1.36  jmcneill }
    289  1.36  jmcneill 
    290  1.36  jmcneill static bool
    291  1.42    dyoung ppb_suspend(device_t dv, const pmf_qual_t *qual)
    292  1.36  jmcneill {
    293  1.36  jmcneill 	struct ppb_softc *sc = device_private(dv);
    294  1.36  jmcneill 	int off;
    295  1.36  jmcneill 
    296  1.36  jmcneill 	for (off = 0x40; off <= 0xff; off += 4)
    297  1.36  jmcneill 		sc->sc_pciconfext[(off - 0x40) / 4] =
    298  1.36  jmcneill 		    pci_conf_read(sc->sc_pc, sc->sc_tag, off);
    299  1.36  jmcneill 
    300  1.36  jmcneill 	return true;
    301  1.36  jmcneill }
    302  1.36  jmcneill 
    303  1.37    dyoung static void
    304  1.37    dyoung ppbchilddet(device_t self, device_t child)
    305  1.37    dyoung {
    306  1.37    dyoung 	/* we keep no references to child devices, so do nothing */
    307  1.37    dyoung }
    308  1.37    dyoung 
    309  1.40    dyoung CFATTACH_DECL3_NEW(ppb, sizeof(struct ppb_softc),
    310  1.40    dyoung     ppbmatch, ppbattach, ppbdetach, NULL, NULL, ppbchilddet,
    311  1.40    dyoung     DVF_DETACH_SHUTDOWN);
    312