ppb.c revision 1.34.22.5
1 /* $NetBSD: ppb.c,v 1.34.22.5 2007/10/01 05:37:55 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.34.22.5 2007/10/01 05:37:55 joerg Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/ppbreg.h> 44 #include <dev/pci/pcidevs.h> 45 46 struct ppb_softc { 47 struct device sc_dev; /* generic device glue */ 48 pci_chipset_tag_t sc_pc; /* our PCI chipset... */ 49 pcitag_t sc_tag; /* ...and tag. */ 50 51 pcireg_t sc_pciconfext[48]; 52 }; 53 54 static void ppb_resume(device_t); 55 static void ppb_suspend(device_t); 56 57 static int 58 ppbmatch(struct device *parent, struct cfdata *match, 59 void *aux) 60 { 61 struct pci_attach_args *pa = aux; 62 63 /* 64 * Check the ID register to see that it's a PCI bridge. 65 * If it is, we assume that we can deal with it; it _should_ 66 * work in a standardized way... 67 */ 68 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 69 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 70 return (1); 71 72 return (0); 73 } 74 75 static void 76 ich_disable_sci(struct device *self, pci_chipset_tag_t pc, pcitag_t tag) 77 { 78 pcireg_t val; 79 80 /* 81 * Intel I/O Controller Hub 6 Family Datasheet 82 * Section 19.1.44 83 * 84 * Intel I/O Controller Hub 7 Family Datasheet 85 * Section 18.1.44 86 * 87 * Intel I/O Controller Hub 8 Family Datasheet 88 * Section 20.1.45 89 * 90 * Intel I/O Controller Hub 9 Family Datasheet 91 * Section 20.1.46 92 * 93 * Address Offset: D8 94 * 95 * Bit 31: Power Management SCI Enable 96 * Bit 30: Hot Plug SCI Enable 97 * 98 * Disable both as NetBSD currently can't deal with the interrupts. 99 */ 100 101 val = pci_conf_read(pc, tag, 0xd8); 102 if ((val & 0xc000000) != 0) { 103 aprint_normal("%s: disabling unsupported PM and Hot Plug SCI\n", 104 self->dv_xname); 105 106 val &= ~(0xc000000); 107 pci_conf_write(pc, tag, 0xd8, val); 108 } 109 } 110 111 static void 112 ppbattach(struct device *parent, struct device *self, void *aux) 113 { 114 struct ppb_softc *sc = (void *) self; 115 struct pci_attach_args *pa = aux; 116 pci_chipset_tag_t pc = pa->pa_pc; 117 struct pcibus_attach_args pba; 118 pcireg_t busdata; 119 char devinfo[256]; 120 pnp_status_t pnp_status; 121 122 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 123 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 124 PCI_REVISION(pa->pa_class)); 125 aprint_naive("\n"); 126 127 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 128 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_EXP_0 || 129 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_EXP_1 || 130 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801FB_EXP_2 || 131 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801G_EXP_1 || 132 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801G_EXP_2 || 133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801G_EXP_3 || 134 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801G_EXP_4 || 135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801G_EXP_5 || 136 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801G_EXP_6 || 137 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801H_EXP_1 || 138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801H_EXP_2 || 139 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801H_EXP_3 || 140 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801H_EXP_4 || 141 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801H_EXP_5 || 142 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801H_EXP_6 || 143 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801I_EXP_1 || 144 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801I_EXP_2 || 145 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801I_EXP_3 || 146 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801I_EXP_4 || 147 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801I_EXP_5 || 148 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82801I_EXP_6)) 149 ich_disable_sci(self, pc, pa->pa_tag); 150 151 sc->sc_pc = pc; 152 sc->sc_tag = pa->pa_tag; 153 154 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 155 156 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 157 aprint_normal("%s: not configured by system firmware\n", 158 self->dv_xname); 159 return; 160 } 161 162 #if 0 163 /* 164 * XXX can't do this, because we're not given our bus number 165 * (we shouldn't need it), and because we've no way to 166 * decompose our tag. 167 */ 168 /* sanity check. */ 169 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 170 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 171 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 172 #endif 173 174 pnp_status = pci_generic_power_register(self, pa->pa_pc, pa->pa_tag, 175 ppb_suspend, ppb_resume); 176 if (pnp_status != PNP_STATUS_SUCCESS) { 177 aprint_error("%s: couldn't establish power handler\n", 178 device_xname(self)); 179 } 180 181 /* 182 * Attach the PCI bus than hangs off of it. 183 * 184 * XXX Don't pass-through Memory Read Multiple. Should we? 185 * XXX Consult the spec... 186 */ 187 pba.pba_iot = pa->pa_iot; 188 pba.pba_memt = pa->pa_memt; 189 pba.pba_dmat = pa->pa_dmat; 190 pba.pba_dmat64 = pa->pa_dmat64; 191 pba.pba_pc = pc; 192 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 193 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 194 pba.pba_bridgetag = &sc->sc_tag; 195 pba.pba_intrswiz = pa->pa_intrswiz; 196 pba.pba_intrtag = pa->pa_intrtag; 197 198 config_found_ia(self, "pcibus", &pba, pcibusprint); 199 } 200 201 static void 202 ppb_resume(device_t dv) 203 { 204 struct ppb_softc *sc = device_private(dv); 205 int off; 206 pcireg_t val; 207 208 for (off = 0x40; off <= 0xff; off += 4) { 209 val = pci_conf_read(sc->sc_pc, sc->sc_tag, off); 210 if (val != sc->sc_pciconfext[(off - 0x40) / 4]) 211 pci_conf_write(sc->sc_pc, sc->sc_tag, off, 212 sc->sc_pciconfext[(off - 0x40)/4]); 213 } 214 } 215 216 static void 217 ppb_suspend(device_t dv) 218 { 219 struct ppb_softc *sc = device_private(dv); 220 int off; 221 222 for (off = 0x40; off <= 0xff; off += 4) 223 sc->sc_pciconfext[(off - 0x40) / 4] = 224 pci_conf_read(sc->sc_pc, sc->sc_tag, off); 225 } 226 227 CFATTACH_DECL(ppb, sizeof(struct ppb_softc), 228 ppbmatch, ppbattach, NULL, NULL); 229
Indexes created Mon Oct 13 16:09:52 GMT 2025