ppb.c revision 1.39.18.4
1 /* $NetBSD: ppb.c,v 1.39.18.4 2014/02/15 03:22:27 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.39.18.4 2014/02/15 03:22:27 matt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/ppbreg.h> 44 #include <dev/pci/pcidevs.h> 45 46 #define PCIE_SLCSR_NOTIFY_MASK \ 47 (PCIE_SLCSR_ABE | PCIE_SLCSR_PFE | PCIE_SLCSR_MSE | \ 48 PCIE_SLCSR_PDE | PCIE_SLCSR_CCE | PCIE_SLCSR_HPE) 49 50 struct ppb_softc { 51 device_t sc_dev; /* generic device glue */ 52 pci_chipset_tag_t sc_pc; /* our PCI chipset... */ 53 pcitag_t sc_tag; /* ...and tag. */ 54 55 pcireg_t sc_pciconfext[48]; 56 }; 57 58 static bool ppb_resume(device_t PMF_FN_PROTO); 59 static bool ppb_suspend(device_t PMF_FN_PROTO); 60 61 static int 62 ppbmatch(device_t parent, cfdata_t match, void *aux) 63 { 64 struct pci_attach_args *pa = aux; 65 66 /* 67 * Check the ID register to see that it's a PCI bridge. 68 * If it is, we assume that we can deal with it; it _should_ 69 * work in a standardized way... 70 */ 71 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 72 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 73 return 1; 74 75 #ifdef _MIPS_PADDR_T_64BIT 76 /* The LDT HB acts just like a PPB. */ 77 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIBYTE && 78 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIBYTE_BCM1250_LDTHB) 79 return 1; 80 #endif 81 82 return 0; 83 } 84 85 static void 86 ppb_fix_pcie(device_t self) 87 { 88 struct ppb_softc *sc = device_private(self); 89 pcireg_t reg; 90 int off; 91 92 if (!pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 93 &off, ®)) 94 return; /* Not a PCIe device */ 95 96 aprint_normal_dev(self, "PCI Express "); 97 switch (reg & PCIE_XCAP_VER_MASK) { 98 case PCIE_XCAP_VER_1_0: 99 aprint_normal("1.0"); 100 break; 101 case PCIE_XCAP_VER_2_0: 102 aprint_normal("2.0"); 103 break; 104 default: 105 aprint_normal_dev(self, 106 "version unsupported (0x%" PRIxMAX ")\n", 107 __SHIFTOUT(reg, PCIE_XCAP_VER_MASK)); 108 return; 109 } 110 aprint_normal(" <"); 111 switch (reg & PCIE_XCAP_TYPE_MASK) { 112 case PCIE_XCAP_TYPE_PCIE_DEV: 113 aprint_normal("PCI-E Endpoint device"); 114 break; 115 case PCIE_XCAP_TYPE_PCI_DEV: 116 aprint_normal("Legacy PCI-E Endpoint device"); 117 break; 118 case PCIE_XCAP_TYPE_ROOT: 119 aprint_normal("Root Port of PCI-E Root Complex"); 120 break; 121 case PCIE_XCAP_TYPE_UP: 122 aprint_normal("Upstream Port of PCI-E Switch"); 123 break; 124 case PCIE_XCAP_TYPE_DOWN: 125 aprint_normal("Downstream Port of PCI-E Switch"); 126 break; 127 case PCIE_XCAP_TYPE_PCIE2PCI: 128 aprint_normal("PCI-E to PCI/PCI-X Bridge"); 129 break; 130 case PCIE_XCAP_TYPE_PCI2PCIE: 131 aprint_normal("PCI/PCI-X to PCI-E Bridge"); 132 break; 133 default: 134 aprint_normal("Device/Port Type 0x%" PRIxMAX, 135 __SHIFTOUT(reg, PCIE_XCAP_TYPE_MASK)); 136 break; 137 } 138 139 switch (reg & PCIE_XCAP_TYPE_MASK) { 140 case PCIE_XCAP_TYPE_ROOT: 141 case PCIE_XCAP_TYPE_DOWN: 142 case PCIE_XCAP_TYPE_PCI2PCIE: 143 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x0c); 144 u_int mlw = (reg >> 4) & 0x1f; 145 u_int mls = (reg >> 0) & 0x0f; 146 aprint_normal("> x%d @ %d.%dGb/s\n", 147 mlw, (mls * 25) / 10, (mls * 25) % 10); 148 149 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x10); 150 if (reg & __BIT(29)) { /* DLLA */ 151 u_int lw = (reg >> 20) & 0x1f; 152 u_int ls = (reg >> 16) & 0x0f; 153 if (lw != mlw || ls != mls) { 154 aprint_normal_dev(self, 155 "link is x%d @ %d.%dGb/s\n", 156 lw, (ls * 25) / 10, (ls * 25) % 10); 157 } 158 } 159 break; 160 default: 161 aprint_normal(">\n"); 162 break; 163 } 164 165 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_SLCSR); 166 if (reg & PCIE_SLCSR_NOTIFY_MASK) { 167 aprint_debug_dev(self, "disabling notification events\n"); 168 reg &= ~PCIE_SLCSR_NOTIFY_MASK; 169 pci_conf_write(sc->sc_pc, sc->sc_tag, 170 off + PCIE_SLCSR, reg); 171 } 172 } 173 174 static void 175 ppbattach(device_t parent, device_t self, void *aux) 176 { 177 struct ppb_softc *sc = device_private(self); 178 struct pci_attach_args *pa = aux; 179 pci_chipset_tag_t pc = pa->pa_pc; 180 struct pcibus_attach_args pba; 181 pcireg_t busdata; 182 char devinfo[256]; 183 184 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 185 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 186 PCI_REVISION(pa->pa_class)); 187 aprint_naive("\n"); 188 189 sc->sc_pc = pc; 190 sc->sc_tag = pa->pa_tag; 191 sc->sc_dev = self; 192 193 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 194 195 ppb_fix_pcie(self); 196 197 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 198 aprint_normal_dev(self, "not configured by system firmware\n"); 199 return; 200 } 201 202 #if 0 203 /* 204 * XXX can't do this, because we're not given our bus number 205 * (we shouldn't need it), and because we've no way to 206 * decompose our tag. 207 */ 208 /* sanity check. */ 209 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 210 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 211 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 212 #endif 213 214 if (!pmf_device_register(self, ppb_suspend, ppb_resume)) 215 aprint_error_dev(self, "couldn't establish power handler\n"); 216 217 /* 218 * Attach the PCI bus than hangs off of it. 219 * 220 * XXX Don't pass-through Memory Read Multiple. Should we? 221 * XXX Consult the spec... 222 */ 223 pba.pba_iot = pa->pa_iot; 224 pba.pba_memt = pa->pa_memt; 225 pba.pba_dmat = pa->pa_dmat; 226 pba.pba_dmat64 = pa->pa_dmat64; 227 pba.pba_pc = pc; 228 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 229 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 230 pba.pba_bridgetag = &sc->sc_tag; 231 pba.pba_intrswiz = pa->pa_intrswiz; 232 pba.pba_intrtag = pa->pa_intrtag; 233 234 config_found_ia(self, "pcibus", &pba, pcibusprint); 235 } 236 237 static int 238 ppbdetach(device_t self, int flags) 239 { 240 int rc; 241 242 if ((rc = config_detach_children(self, flags)) != 0) 243 return rc; 244 pmf_device_deregister(self); 245 return 0; 246 } 247 248 static bool 249 ppb_resume(device_t dv PMF_FN_ARGS) 250 { 251 struct ppb_softc *sc = device_private(dv); 252 int off; 253 pcireg_t val; 254 255 for (off = 0x40; off <= 0xff; off += 4) { 256 val = pci_conf_read(sc->sc_pc, sc->sc_tag, off); 257 if (val != sc->sc_pciconfext[(off - 0x40) / 4]) 258 pci_conf_write(sc->sc_pc, sc->sc_tag, off, 259 sc->sc_pciconfext[(off - 0x40)/4]); 260 } 261 262 ppb_fix_pcie(dv); 263 264 return true; 265 } 266 267 static bool 268 ppb_suspend(device_t dv PMF_FN_ARGS) 269 { 270 struct ppb_softc *sc = device_private(dv); 271 int off; 272 273 for (off = 0x40; off <= 0xff; off += 4) 274 sc->sc_pciconfext[(off - 0x40) / 4] = 275 pci_conf_read(sc->sc_pc, sc->sc_tag, off); 276 277 return true; 278 } 279 280 static void 281 ppbchilddet(device_t self, device_t child) 282 { 283 /* we keep no references to child devices, so do nothing */ 284 } 285 286 CFATTACH_DECL2_NEW(ppb, sizeof(struct ppb_softc), 287 ppbmatch, ppbattach, ppbdetach, NULL, NULL, ppbchilddet); 288
Indexes created Mon Oct 13 14:09:54 GMT 2025