ppb.c revision 1.63.2.3
1 /* $NetBSD: ppb.c,v 1.63.2.3 2021/12/03 19:45:13 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.63.2.3 2021/12/03 19:45:13 martin Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 #include <sys/evcnt.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/ppbreg.h> 45 #include <dev/pci/ppbvar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #define PCIE_SLCSR_ENABLE_MASK \ 49 (PCIE_SLCSR_ABE | PCIE_SLCSR_PFE | PCIE_SLCSR_MSE | \ 50 PCIE_SLCSR_PDE | PCIE_SLCSR_CCE | PCIE_SLCSR_HPE | \ 51 PCIE_SLCSR_DLLSCE) 52 53 #define PCIE_SLCSR_STATCHG_MASK \ 54 (PCIE_SLCSR_ABP | PCIE_SLCSR_PFD | PCIE_SLCSR_MSC | \ 55 PCIE_SLCSR_PDC | PCIE_SLCSR_CC | PCIE_SLCSR_LACS) 56 57 static const char pcie_linkspeed_strings[5][5] = { 58 "1.25", "2.5", "5.0", "8.0", "16.0" 59 }; 60 61 int ppb_printevent = 0; /* Print event type if the value is not 0 */ 62 63 static int ppbmatch(device_t, cfdata_t, void *); 64 static void ppbattach(device_t, device_t, void *); 65 static int ppbdetach(device_t, int); 66 static void ppbchilddet(device_t, device_t); 67 #ifdef PPB_USEINTR 68 static int ppb_intr(void *); 69 #endif 70 static bool ppb_resume(device_t, const pmf_qual_t *); 71 static bool ppb_suspend(device_t, const pmf_qual_t *); 72 73 CFATTACH_DECL3_NEW(ppb, sizeof(struct ppb_softc), 74 ppbmatch, ppbattach, ppbdetach, NULL, NULL, ppbchilddet, 75 DVF_DETACH_SHUTDOWN); 76 77 static int 78 ppbmatch(device_t parent, cfdata_t match, void *aux) 79 { 80 struct pci_attach_args *pa = aux; 81 82 /* 83 * Check the ID register to see that it's a PCI bridge. 84 * If it is, we assume that we can deal with it; it _should_ 85 * work in a standardized way... 86 */ 87 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 88 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 89 return 1; 90 91 #ifdef __powerpc__ 92 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PROCESSOR && 93 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PROCESSOR_POWERPC) { 94 pcireg_t bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag, 95 PCI_BHLC_REG); 96 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_FREESCALE 97 && PCI_HDRTYPE(bhlc) == PCI_HDRTYPE_RC) 98 return 1; 99 } 100 #endif 101 102 #ifdef _MIPS_PADDR_T_64BIT 103 /* The LDT HB acts just like a PPB. */ 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIBYTE 105 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIBYTE_BCM1250_LDTHB) 106 return 1; 107 #endif 108 109 return 0; 110 } 111 112 static void 113 ppb_print_pcie(device_t self) 114 { 115 struct ppb_softc *sc = device_private(self); 116 pcireg_t reg; 117 int off, capversion, devtype; 118 119 if (!pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 120 &off, ®)) 121 return; /* Not a PCIe device */ 122 123 capversion = PCIE_XCAP_VER(reg); 124 devtype = PCIE_XCAP_TYPE(reg); 125 aprint_normal_dev(self, "PCI Express capability version "); 126 switch (capversion) { 127 case PCIE_XCAP_VER_1: 128 aprint_normal("1"); 129 break; 130 case PCIE_XCAP_VER_2: 131 aprint_normal("2"); 132 break; 133 default: 134 aprint_normal_dev(self, "unsupported (%d)\n", capversion); 135 return; 136 } 137 aprint_normal(" <"); 138 switch (devtype) { 139 case PCIE_XCAP_TYPE_PCIE_DEV: 140 aprint_normal("PCI-E Endpoint device"); 141 break; 142 case PCIE_XCAP_TYPE_PCI_DEV: 143 aprint_normal("Legacy PCI-E Endpoint device"); 144 break; 145 case PCIE_XCAP_TYPE_RP: 146 aprint_normal("Root Port of PCI-E Root Complex"); 147 break; 148 case PCIE_XCAP_TYPE_UP: 149 aprint_normal("Upstream Port of PCI-E Switch"); 150 break; 151 case PCIE_XCAP_TYPE_DOWN: 152 aprint_normal("Downstream Port of PCI-E Switch"); 153 break; 154 case PCIE_XCAP_TYPE_PCIE2PCI: 155 aprint_normal("PCI-E to PCI/PCI-X Bridge"); 156 break; 157 case PCIE_XCAP_TYPE_PCI2PCIE: 158 aprint_normal("PCI/PCI-X to PCI-E Bridge"); 159 break; 160 default: 161 aprint_normal("Device/Port Type %x", devtype); 162 break; 163 } 164 165 switch (devtype) { 166 case PCIE_XCAP_TYPE_RP: 167 case PCIE_XCAP_TYPE_DOWN: 168 case PCIE_XCAP_TYPE_PCI2PCIE: 169 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP); 170 u_int mlw = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 171 u_int mls = __SHIFTOUT(reg, PCIE_LCAP_MAX_SPEED); 172 173 if (mls < __arraycount(pcie_linkspeed_strings)) { 174 aprint_normal("> x%d @ %sGT/s\n", 175 mlw, pcie_linkspeed_strings[mls]); 176 } else { 177 aprint_normal("> x%d @ %d.%dGT/s\n", 178 mlw, (mls * 25) / 10, (mls * 25) % 10); 179 } 180 181 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCSR); 182 if (reg & PCIE_LCSR_DLACTIVE) { /* DLLA */ 183 u_int lw = __SHIFTOUT(reg, PCIE_LCSR_NLW); 184 u_int ls = __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED); 185 186 if (lw != mlw || ls != mls) { 187 if (ls < __arraycount(pcie_linkspeed_strings)) { 188 aprint_normal_dev(self, 189 "link is x%d @ %sGT/s\n", 190 lw, pcie_linkspeed_strings[ls]); 191 } else { 192 aprint_normal_dev(self, 193 "link is x%d @ %d.%dGT/s\n", 194 lw, (ls * 25) / 10, (ls * 25) % 10); 195 } 196 } 197 } 198 break; 199 default: 200 aprint_normal(">\n"); 201 break; 202 } 203 } 204 205 static void 206 ppbattach(device_t parent, device_t self, void *aux) 207 { 208 struct ppb_softc *sc = device_private(self); 209 struct pci_attach_args *pa = aux; 210 pci_chipset_tag_t pc = pa->pa_pc; 211 struct pcibus_attach_args pba; 212 #ifdef PPB_USEINTR 213 char const *intrstr; 214 char intrbuf[PCI_INTRSTR_LEN]; 215 #endif 216 pcireg_t busdata, reg; 217 bool second_configured = false; 218 219 pci_aprint_devinfo(pa, NULL); 220 221 sc->sc_pc = pc; 222 sc->sc_tag = pa->pa_tag; 223 sc->sc_dev = self; 224 225 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 226 227 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 228 aprint_normal_dev(self, "not configured by system firmware\n"); 229 return; 230 } 231 232 ppb_print_pcie(self); 233 234 #if 0 235 /* 236 * XXX can't do this, because we're not given our bus number 237 * (we shouldn't need it), and because we've no way to 238 * decompose our tag. 239 */ 240 /* sanity check. */ 241 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 242 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 243 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 244 #endif 245 246 /* Check for PCI Express capabilities and setup hotplug support. */ 247 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 248 &sc->sc_pciecapoff, ®) && (reg & PCIE_XCAP_SI)) { 249 /* 250 * First, disable all interrupts because BIOS might 251 * enable them. 252 */ 253 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 254 sc->sc_pciecapoff + PCIE_SLCSR); 255 if (reg & PCIE_SLCSR_ENABLE_MASK) { 256 reg &= ~PCIE_SLCSR_ENABLE_MASK; 257 pci_conf_write(sc->sc_pc, sc->sc_tag, 258 sc->sc_pciecapoff + PCIE_SLCSR, reg); 259 } 260 #ifdef PPB_USEINTR 261 #if 0 /* notyet */ 262 /* 263 * XXX Initialize workqueue or something else for 264 * HotPlug support. 265 */ 266 #endif 267 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) 268 sc->sc_intrhand = pci_intr_establish_xname(pc, 269 sc->sc_pihp[0], IPL_BIO, ppb_intr, sc, 270 device_xname(sc->sc_dev)); 271 #endif 272 } 273 274 #ifdef PPB_USEINTR 275 if (sc->sc_intrhand != NULL) { 276 pcireg_t slcap, slcsr, val; 277 278 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, 279 sizeof(intrbuf)); 280 aprint_normal_dev(self, "%s\n", intrstr); 281 282 /* Clear any pending events */ 283 slcsr = pci_conf_read(pc, pa->pa_tag, 284 sc->sc_pciecapoff + PCIE_SLCSR); 285 pci_conf_write(pc, pa->pa_tag, 286 sc->sc_pciecapoff + PCIE_SLCSR, slcsr); 287 288 /* Enable interrupt. */ 289 val = 0; 290 slcap = pci_conf_read(pc, pa->pa_tag, 291 sc->sc_pciecapoff + PCIE_SLCAP); 292 if (slcap & PCIE_SLCAP_ABP) 293 val |= PCIE_SLCSR_ABE; 294 if (slcap & PCIE_SLCAP_PCP) 295 val |= PCIE_SLCSR_PFE; 296 if (slcap & PCIE_SLCAP_MSP) 297 val |= PCIE_SLCSR_MSE; 298 #if 0 299 /* 300 * XXX Disable for a while because setting 301 * PCIE_SLCSR_CCE makes break device access on 302 * some environment. 303 */ 304 if ((slcap & PCIE_SLCAP_NCCS) == 0) 305 val |= PCIE_SLCSR_CCE; 306 #endif 307 /* Attention indicator off by default */ 308 if (slcap & PCIE_SLCAP_AIP) { 309 val |= __SHIFTIN(PCIE_SLCSR_IND_OFF, 310 PCIE_SLCSR_AIC); 311 } 312 /* Power indicator */ 313 if (slcap & PCIE_SLCAP_PIP) { 314 /* 315 * Indicator off: 316 * a) card not present 317 * b) power fault 318 * c) MRL sensor off 319 */ 320 if (((slcsr & PCIE_SLCSR_PDS) == 0) 321 || ((slcsr & PCIE_SLCSR_PFD) != 0) 322 || (((slcap & PCIE_SLCAP_MSP) != 0) 323 && ((slcsr & PCIE_SLCSR_MS) != 0))) 324 val |= __SHIFTIN(PCIE_SLCSR_IND_OFF, 325 PCIE_SLCSR_PIC); 326 else 327 val |= __SHIFTIN(PCIE_SLCSR_IND_ON, 328 PCIE_SLCSR_PIC); 329 } 330 331 val |= PCIE_SLCSR_DLLSCE | PCIE_SLCSR_HPE | PCIE_SLCSR_PDE; 332 slcsr = val; 333 pci_conf_write(pc, pa->pa_tag, 334 sc->sc_pciecapoff + PCIE_SLCSR, slcsr); 335 336 /* Attach event counters */ 337 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, NULL, 338 device_xname(sc->sc_dev), "Interrupt"); 339 evcnt_attach_dynamic(&sc->sc_ev_abp, EVCNT_TYPE_MISC, NULL, 340 device_xname(sc->sc_dev), "Attention Button Pressed"); 341 evcnt_attach_dynamic(&sc->sc_ev_pfd, EVCNT_TYPE_MISC, NULL, 342 device_xname(sc->sc_dev), "Power Fault Detected"); 343 evcnt_attach_dynamic(&sc->sc_ev_msc, EVCNT_TYPE_MISC, NULL, 344 device_xname(sc->sc_dev), "MRL Sensor Changed"); 345 evcnt_attach_dynamic(&sc->sc_ev_pdc, EVCNT_TYPE_MISC, NULL, 346 device_xname(sc->sc_dev), "Presence Detect Changed"); 347 evcnt_attach_dynamic(&sc->sc_ev_cc, EVCNT_TYPE_MISC, NULL, 348 device_xname(sc->sc_dev), "Command Completed"); 349 evcnt_attach_dynamic(&sc->sc_ev_lacs, EVCNT_TYPE_MISC, NULL, 350 device_xname(sc->sc_dev), "Data Link Layer State Changed"); 351 } 352 #endif /* PPB_USEINTR */ 353 354 /* Configuration test */ 355 if (PPB_BUSINFO_SECONDARY(busdata) != 0) { 356 uint32_t base, limit; 357 358 /* I/O region test */ 359 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_STATIO_REG); 360 base = (reg & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 361 limit = ((reg >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 362 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 363 limit |= 0x00000fff; 364 if (PCI_BRIDGE_IO_32BITS(reg)) { 365 reg = pci_conf_read(pc, pa->pa_tag, 366 PCI_BRIDGE_IOHIGH_REG); 367 base |= ((reg >> PCI_BRIDGE_IOHIGH_BASE_SHIFT) 368 & 0xffff) << 16; 369 limit |= ((reg >> PCI_BRIDGE_IOHIGH_LIMIT_SHIFT) 370 & 0xffff) << 16; 371 } 372 if (base < limit) { 373 second_configured = true; 374 goto configure; 375 } 376 377 /* Non-prefetchable memory region test */ 378 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_MEMORY_REG); 379 base = ((reg >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 380 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 381 limit = (((reg >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 382 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 383 if (base < limit) { 384 second_configured = true; 385 goto configure; 386 } 387 388 /* Prefetchable memory region test */ 389 reg = pci_conf_read(pc, pa->pa_tag, 390 PCI_BRIDGE_PREFETCHMEM_REG); 391 base = ((reg >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 392 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 393 limit = (((reg >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 394 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 395 if (PCI_BRIDGE_PREFETCHMEM_64BITS(reg)) { 396 reg = pci_conf_read(pc, pa->pa_tag, 397 PCI_BRIDGE_IOHIGH_REG); 398 base |= (uint64_t)pci_conf_read(pc, pa->pa_tag, 399 PCI_BRIDGE_PREFETCHBASE32_REG) << 32; 400 limit |= (uint64_t)pci_conf_read(pc, pa->pa_tag, 401 PCI_BRIDGE_PREFETCHLIMIT32_REG) << 32; 402 } 403 if (base < limit) { 404 second_configured = true; 405 goto configure; 406 } 407 } 408 409 configure: 410 /* 411 * If the secondary bus is configured and the bus mastering is not 412 * enabled, enable it. 413 */ 414 if (second_configured) { 415 reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 416 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) 417 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 418 reg | PCI_COMMAND_MASTER_ENABLE); 419 } 420 421 if (!pmf_device_register(self, ppb_suspend, ppb_resume)) 422 aprint_error_dev(self, "couldn't establish power handler\n"); 423 424 /* 425 * Attach the PCI bus that hangs off of it. 426 * 427 * XXX Don't pass-through Memory Read Multiple. Should we? 428 * XXX Consult the spec... 429 */ 430 pba.pba_iot = pa->pa_iot; 431 pba.pba_memt = pa->pa_memt; 432 pba.pba_dmat = pa->pa_dmat; 433 pba.pba_dmat64 = pa->pa_dmat64; 434 pba.pba_pc = pc; 435 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 436 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 437 pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata); 438 pba.pba_bridgetag = &sc->sc_tag; 439 pba.pba_intrswiz = pa->pa_intrswiz; 440 pba.pba_intrtag = pa->pa_intrtag; 441 442 config_found_ia(self, "pcibus", &pba, pcibusprint); 443 } 444 445 static int 446 ppbdetach(device_t self, int flags) 447 { 448 #ifdef PPB_USEINTR 449 struct ppb_softc *sc = device_private(self); 450 pcireg_t slcsr; 451 #endif 452 int rc; 453 454 if ((rc = config_detach_children(self, flags)) != 0) 455 return rc; 456 457 #ifdef PPB_USEINTR 458 if (sc->sc_intrhand != NULL) { 459 /* Detach event counters */ 460 evcnt_detach(&sc->sc_ev_intr); 461 evcnt_detach(&sc->sc_ev_abp); 462 evcnt_detach(&sc->sc_ev_pfd); 463 evcnt_detach(&sc->sc_ev_msc); 464 evcnt_detach(&sc->sc_ev_pdc); 465 evcnt_detach(&sc->sc_ev_cc); 466 evcnt_detach(&sc->sc_ev_lacs); 467 468 /* Clear any pending events and disable interrupt */ 469 slcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 470 sc->sc_pciecapoff + PCIE_SLCSR); 471 slcsr &= ~PCIE_SLCSR_ENABLE_MASK; 472 pci_conf_write(sc->sc_pc, sc->sc_tag, 473 sc->sc_pciecapoff + PCIE_SLCSR, slcsr); 474 475 /* Disestablish the interrupt handler */ 476 pci_intr_disestablish(sc->sc_pc, sc->sc_intrhand); 477 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 478 } 479 #endif 480 481 pmf_device_deregister(self); 482 return 0; 483 } 484 485 static bool 486 ppb_resume(device_t dv, const pmf_qual_t *qual) 487 { 488 struct ppb_softc *sc = device_private(dv); 489 int off; 490 pcireg_t val; 491 492 for (off = 0x40; off <= 0xff; off += 4) { 493 val = pci_conf_read(sc->sc_pc, sc->sc_tag, off); 494 if (val != sc->sc_pciconfext[(off - 0x40) / 4]) 495 pci_conf_write(sc->sc_pc, sc->sc_tag, off, 496 sc->sc_pciconfext[(off - 0x40)/4]); 497 } 498 499 return true; 500 } 501 502 static bool 503 ppb_suspend(device_t dv, const pmf_qual_t *qual) 504 { 505 struct ppb_softc *sc = device_private(dv); 506 int off; 507 508 for (off = 0x40; off <= 0xff; off += 4) 509 sc->sc_pciconfext[(off - 0x40) / 4] = 510 pci_conf_read(sc->sc_pc, sc->sc_tag, off); 511 512 return true; 513 } 514 515 static void 516 ppbchilddet(device_t self, device_t child) 517 { 518 /* we keep no references to child devices, so do nothing */ 519 } 520 521 #ifdef PPB_USEINTR 522 static int 523 ppb_intr(void *arg) 524 { 525 struct ppb_softc *sc = arg; 526 device_t dev = sc->sc_dev; 527 pcireg_t reg; 528 529 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 530 sc->sc_pciecapoff + PCIE_SLCSR); 531 532 /* 533 * Not me. This check is only required for INTx. 534 * ppb_intr() would be spilted int ppb_intr_legacy() and ppb_intr_msi() 535 */ 536 if ((reg & PCIE_SLCSR_STATCHG_MASK) == 0) 537 return 0; 538 539 /* Clear interrupts. */ 540 pci_conf_write(sc->sc_pc, sc->sc_tag, 541 sc->sc_pciecapoff + PCIE_SLCSR, reg); 542 543 sc->sc_ev_intr.ev_count++; 544 545 /* Attention Button Pressed */ 546 if (reg & PCIE_SLCSR_ABP) { 547 sc->sc_ev_abp.ev_count++; 548 if (ppb_printevent) 549 device_printf(dev, "Attention Button Pressed\n"); 550 } 551 552 /* Power Fault Detected */ 553 if (reg & PCIE_SLCSR_PFD) { 554 sc->sc_ev_pfd.ev_count++; 555 if (ppb_printevent) 556 device_printf(dev, "Power Fault Detected\n"); 557 } 558 559 /* MRL Sensor Changed */ 560 if (reg & PCIE_SLCSR_MSC) { 561 sc->sc_ev_msc.ev_count++; 562 if (ppb_printevent) 563 device_printf(dev, "MRL Sensor Changed\n"); 564 } 565 566 /* Presence Detect Changed */ 567 if (reg & PCIE_SLCSR_PDC) { 568 sc->sc_ev_pdc.ev_count++; 569 if (ppb_printevent) 570 device_printf(dev, "Presence Detect Changed\n"); 571 if (reg & PCIE_SLCSR_PDS) { 572 /* XXX Insert */ 573 } else { 574 /* XXX Remove */ 575 } 576 } 577 578 /* Command Completed */ 579 if (reg & PCIE_SLCSR_CC) { 580 sc->sc_ev_cc.ev_count++; 581 if (ppb_printevent) 582 device_printf(dev, "Command Completed\n"); 583 } 584 585 /* Data Link Layer State Changed */ 586 if (reg & PCIE_SLCSR_LACS) { 587 sc->sc_ev_lacs.ev_count++; 588 if (ppb_printevent) 589 device_printf(dev, "Data Link Layer State Changed\n"); 590 } 591 592 return 1; 593 } 594 #endif /* PPB_USEINTR */ 595
Indexes created Tue Oct 14 01:09:49 GMT 2025