ppb.c revision 1.67
1 /* $NetBSD: ppb.c,v 1.67 2019/01/29 09:25:52 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.67 2019/01/29 09:25:52 msaitoh Exp $"); 35 36 #ifdef _KERNEL_OPT 37 #include "opt_ppb.h" 38 #endif 39 40 #ifdef _KERNEL_OPT 41 #include "opt_ppb.h" 42 #endif 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/evcnt.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/ppbreg.h> 53 #include <dev/pci/ppbvar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #define PCIE_SLCSR_ENABLE_MASK \ 57 (PCIE_SLCSR_ABE | PCIE_SLCSR_PFE | PCIE_SLCSR_MSE | \ 58 PCIE_SLCSR_PDE | PCIE_SLCSR_CCE | PCIE_SLCSR_HPE | \ 59 PCIE_SLCSR_DLLSCE) 60 61 #define PCIE_SLCSR_STATCHG_MASK \ 62 (PCIE_SLCSR_ABP | PCIE_SLCSR_PFD | PCIE_SLCSR_MSC | \ 63 PCIE_SLCSR_PDC | PCIE_SLCSR_CC | PCIE_SLCSR_LACS) 64 65 static const char pcie_linkspeed_strings[4][5] = { 66 "1.25", "2.5", "5.0", "8.0", 67 }; 68 69 int ppb_printevent = 0; /* Print event type if the value is not 0 */ 70 71 static int ppbmatch(device_t, cfdata_t, void *); 72 static void ppbattach(device_t, device_t, void *); 73 static int ppbdetach(device_t, int); 74 static void ppbchilddet(device_t, device_t); 75 #ifdef PPB_USEINTR 76 static int ppb_intr(void *); 77 #endif 78 static bool ppb_resume(device_t, const pmf_qual_t *); 79 static bool ppb_suspend(device_t, const pmf_qual_t *); 80 81 CFATTACH_DECL3_NEW(ppb, sizeof(struct ppb_softc), 82 ppbmatch, ppbattach, ppbdetach, NULL, NULL, ppbchilddet, 83 DVF_DETACH_SHUTDOWN); 84 85 static int 86 ppbmatch(device_t parent, cfdata_t match, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 90 /* 91 * Check the ID register to see that it's a PCI bridge. 92 * If it is, we assume that we can deal with it; it _should_ 93 * work in a standardized way... 94 */ 95 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 96 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI) 97 return 1; 98 99 #ifdef __powerpc__ 100 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PROCESSOR && 101 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PROCESSOR_POWERPC) { 102 pcireg_t bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag, 103 PCI_BHLC_REG); 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_FREESCALE 105 && PCI_HDRTYPE(bhlc) == PCI_HDRTYPE_RC) 106 return 1; 107 } 108 #endif 109 110 #ifdef _MIPS_PADDR_T_64BIT 111 /* The LDT HB acts just like a PPB. */ 112 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIBYTE 113 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIBYTE_BCM1250_LDTHB) 114 return 1; 115 #endif 116 117 return 0; 118 } 119 120 static void 121 ppb_print_pcie(device_t self) 122 { 123 struct ppb_softc *sc = device_private(self); 124 pcireg_t reg; 125 int off, capversion, devtype; 126 127 if (!pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 128 &off, ®)) 129 return; /* Not a PCIe device */ 130 131 capversion = PCIE_XCAP_VER(reg); 132 devtype = PCIE_XCAP_TYPE(reg); 133 aprint_normal_dev(self, "PCI Express capability version "); 134 switch (capversion) { 135 case PCIE_XCAP_VER_1: 136 aprint_normal("1"); 137 break; 138 case PCIE_XCAP_VER_2: 139 aprint_normal("2"); 140 break; 141 default: 142 aprint_normal_dev(self, "unsupported (%d)\n", capversion); 143 return; 144 } 145 aprint_normal(" <"); 146 switch (devtype) { 147 case PCIE_XCAP_TYPE_PCIE_DEV: 148 aprint_normal("PCI-E Endpoint device"); 149 break; 150 case PCIE_XCAP_TYPE_PCI_DEV: 151 aprint_normal("Legacy PCI-E Endpoint device"); 152 break; 153 case PCIE_XCAP_TYPE_ROOT: 154 aprint_normal("Root Port of PCI-E Root Complex"); 155 break; 156 case PCIE_XCAP_TYPE_UP: 157 aprint_normal("Upstream Port of PCI-E Switch"); 158 break; 159 case PCIE_XCAP_TYPE_DOWN: 160 aprint_normal("Downstream Port of PCI-E Switch"); 161 break; 162 case PCIE_XCAP_TYPE_PCIE2PCI: 163 aprint_normal("PCI-E to PCI/PCI-X Bridge"); 164 break; 165 case PCIE_XCAP_TYPE_PCI2PCIE: 166 aprint_normal("PCI/PCI-X to PCI-E Bridge"); 167 break; 168 default: 169 aprint_normal("Device/Port Type %x", devtype); 170 break; 171 } 172 173 switch (devtype) { 174 case PCIE_XCAP_TYPE_ROOT: 175 case PCIE_XCAP_TYPE_DOWN: 176 case PCIE_XCAP_TYPE_PCI2PCIE: 177 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP); 178 u_int mlw = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 179 u_int mls = __SHIFTOUT(reg, PCIE_LCAP_MAX_SPEED); 180 181 if (mls < __arraycount(pcie_linkspeed_strings)) { 182 aprint_normal("> x%d @ %sGT/s\n", 183 mlw, pcie_linkspeed_strings[mls]); 184 } else { 185 aprint_normal("> x%d @ %d.%dGT/s\n", 186 mlw, (mls * 25) / 10, (mls * 25) % 10); 187 } 188 189 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCSR); 190 if (reg & PCIE_LCSR_DLACTIVE) { /* DLLA */ 191 u_int lw = __SHIFTOUT(reg, PCIE_LCSR_NLW); 192 u_int ls = __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED); 193 194 if (lw != mlw || ls != mls) { 195 if (ls < __arraycount(pcie_linkspeed_strings)) { 196 aprint_normal_dev(self, 197 "link is x%d @ %sGT/s\n", 198 lw, pcie_linkspeed_strings[ls]); 199 } else { 200 aprint_normal_dev(self, 201 "link is x%d @ %d.%dGT/s\n", 202 lw, (ls * 25) / 10, (ls * 25) % 10); 203 } 204 } 205 } 206 break; 207 default: 208 aprint_normal(">\n"); 209 break; 210 } 211 } 212 213 static void 214 ppbattach(device_t parent, device_t self, void *aux) 215 { 216 struct ppb_softc *sc = device_private(self); 217 struct pci_attach_args *pa = aux; 218 pci_chipset_tag_t pc = pa->pa_pc; 219 struct pcibus_attach_args pba; 220 #ifdef PPB_USEINTR 221 char const *intrstr; 222 char intrbuf[PCI_INTRSTR_LEN]; 223 #endif 224 pcireg_t busdata, reg; 225 bool second_configured = false; 226 227 pci_aprint_devinfo(pa, NULL); 228 229 sc->sc_pc = pc; 230 sc->sc_tag = pa->pa_tag; 231 sc->sc_dev = self; 232 233 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO); 234 235 if (PPB_BUSINFO_SECONDARY(busdata) == 0) { 236 aprint_normal_dev(self, "not configured by system firmware\n"); 237 return; 238 } 239 240 ppb_print_pcie(self); 241 242 #if 0 243 /* 244 * XXX can't do this, because we're not given our bus number 245 * (we shouldn't need it), and because we've no way to 246 * decompose our tag. 247 */ 248 /* sanity check. */ 249 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata)) 250 panic("ppbattach: bus in tag (%d) != bus in reg (%d)", 251 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata)); 252 #endif 253 254 /* Check for PCI Express capabilities and setup hotplug support. */ 255 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 256 &sc->sc_pciecapoff, ®) && (reg & PCIE_XCAP_SI)) { 257 /* 258 * First, disable all interrupts because BIOS might 259 * enable them. 260 */ 261 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 262 sc->sc_pciecapoff + PCIE_SLCSR); 263 if (reg & PCIE_SLCSR_ENABLE_MASK) { 264 reg &= ~PCIE_SLCSR_ENABLE_MASK; 265 pci_conf_write(sc->sc_pc, sc->sc_tag, 266 sc->sc_pciecapoff + PCIE_SLCSR, reg); 267 } 268 #ifdef PPB_USEINTR 269 #if 0 /* notyet */ 270 /* 271 * XXX Initialize workqueue or something else for 272 * HotPlug support. 273 */ 274 #endif 275 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) == 0) 276 sc->sc_intrhand = pci_intr_establish_xname(pc, 277 sc->sc_pihp[0], IPL_BIO, ppb_intr, sc, 278 device_xname(sc->sc_dev)); 279 #endif 280 } 281 282 #ifdef PPB_USEINTR 283 if (sc->sc_intrhand != NULL) { 284 pcireg_t slcap, slcsr, val; 285 286 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, 287 sizeof(intrbuf)); 288 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 289 290 /* Clear any pending events */ 291 slcsr = pci_conf_read(pc, pa->pa_tag, 292 sc->sc_pciecapoff + PCIE_SLCSR); 293 pci_conf_write(pc, pa->pa_tag, 294 sc->sc_pciecapoff + PCIE_SLCSR, slcsr); 295 296 /* Enable interrupt. */ 297 val = 0; 298 slcap = pci_conf_read(pc, pa->pa_tag, 299 sc->sc_pciecapoff + PCIE_SLCAP); 300 if (slcap & PCIE_SLCAP_ABP) 301 val |= PCIE_SLCSR_ABE; 302 if (slcap & PCIE_SLCAP_PCP) 303 val |= PCIE_SLCSR_PFE; 304 if (slcap & PCIE_SLCAP_MSP) 305 val |= PCIE_SLCSR_MSE; 306 #if 0 307 /* 308 * XXX Disable for a while because setting 309 * PCIE_SLCSR_CCE makes break device access on 310 * some environment. 311 */ 312 if ((slcap & PCIE_SLCAP_NCCS) == 0) 313 val |= PCIE_SLCSR_CCE; 314 #endif 315 /* Attention indicator off by default */ 316 if (slcap & PCIE_SLCAP_AIP) { 317 val |= __SHIFTIN(PCIE_SLCSR_IND_OFF, 318 PCIE_SLCSR_AIC); 319 } 320 /* Power indicator */ 321 if (slcap & PCIE_SLCAP_PIP) { 322 /* 323 * Indicator off: 324 * a) card not present 325 * b) power fault 326 * c) MRL sensor off 327 */ 328 if (((slcsr & PCIE_SLCSR_PDS) == 0) 329 || ((slcsr & PCIE_SLCSR_PFD) != 0) 330 || (((slcap & PCIE_SLCAP_MSP) != 0) 331 && ((slcsr & PCIE_SLCSR_MS) != 0))) 332 val |= __SHIFTIN(PCIE_SLCSR_IND_OFF, 333 PCIE_SLCSR_PIC); 334 else 335 val |= __SHIFTIN(PCIE_SLCSR_IND_ON, 336 PCIE_SLCSR_PIC); 337 } 338 339 val |= PCIE_SLCSR_DLLSCE | PCIE_SLCSR_HPE | PCIE_SLCSR_PDE; 340 slcsr = val; 341 pci_conf_write(pc, pa->pa_tag, 342 sc->sc_pciecapoff + PCIE_SLCSR, slcsr); 343 344 /* Attach event counters */ 345 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, NULL, 346 device_xname(sc->sc_dev), "Interrupt"); 347 evcnt_attach_dynamic(&sc->sc_ev_abp, EVCNT_TYPE_MISC, NULL, 348 device_xname(sc->sc_dev), "Attention Button Pressed"); 349 evcnt_attach_dynamic(&sc->sc_ev_pfd, EVCNT_TYPE_MISC, NULL, 350 device_xname(sc->sc_dev), "Power Fault Detected"); 351 evcnt_attach_dynamic(&sc->sc_ev_msc, EVCNT_TYPE_MISC, NULL, 352 device_xname(sc->sc_dev), "MRL Sensor Changed"); 353 evcnt_attach_dynamic(&sc->sc_ev_pdc, EVCNT_TYPE_MISC, NULL, 354 device_xname(sc->sc_dev), "Presence Detect Changed"); 355 evcnt_attach_dynamic(&sc->sc_ev_cc, EVCNT_TYPE_MISC, NULL, 356 device_xname(sc->sc_dev), "Command Completed"); 357 evcnt_attach_dynamic(&sc->sc_ev_lacs, EVCNT_TYPE_MISC, NULL, 358 device_xname(sc->sc_dev), "Data Link Layer State Changed"); 359 } 360 #endif /* PPB_USEINTR */ 361 362 /* Configuration test */ 363 if (PPB_BUSINFO_SECONDARY(busdata) != 0) { 364 uint32_t base, limit; 365 366 /* I/O region test */ 367 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_STATIO_REG); 368 base = (reg & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 369 limit = ((reg >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 370 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 371 limit |= 0x00000fff; 372 if (PCI_BRIDGE_IO_32BITS(reg)) { 373 reg = pci_conf_read(pc, pa->pa_tag, 374 PCI_BRIDGE_IOHIGH_REG); 375 base |= ((reg >> PCI_BRIDGE_IOHIGH_BASE_SHIFT) 376 & 0xffff) << 16; 377 limit |= ((reg >> PCI_BRIDGE_IOHIGH_LIMIT_SHIFT) 378 & 0xffff) << 16; 379 } 380 if (base < limit) { 381 second_configured = true; 382 goto configure; 383 } 384 385 /* Non-prefetchable memory region test */ 386 reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_MEMORY_REG); 387 base = ((reg >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 388 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 389 limit = (((reg >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 390 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 391 if (base < limit) { 392 second_configured = true; 393 goto configure; 394 } 395 396 /* Prefetchable memory region test */ 397 reg = pci_conf_read(pc, pa->pa_tag, 398 PCI_BRIDGE_PREFETCHMEM_REG); 399 base = ((reg >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 400 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 401 limit = (((reg >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 402 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 403 if (PCI_BRIDGE_PREFETCHMEM_64BITS(reg)) { 404 reg = pci_conf_read(pc, pa->pa_tag, 405 PCI_BRIDGE_IOHIGH_REG); 406 base |= (uint64_t)pci_conf_read(pc, pa->pa_tag, 407 PCI_BRIDGE_PREFETCHBASE32_REG) << 32; 408 limit |= (uint64_t)pci_conf_read(pc, pa->pa_tag, 409 PCI_BRIDGE_PREFETCHLIMIT32_REG) << 32; 410 } 411 if (base < limit) { 412 second_configured = true; 413 goto configure; 414 } 415 } 416 417 configure: 418 /* 419 * If the secondary bus is configured and the bus mastering is not 420 * enabled, enable it. 421 */ 422 if (second_configured) { 423 reg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 424 if ((reg & PCI_COMMAND_MASTER_ENABLE) == 0) 425 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 426 reg | PCI_COMMAND_MASTER_ENABLE); 427 } 428 429 if (!pmf_device_register(self, ppb_suspend, ppb_resume)) 430 aprint_error_dev(self, "couldn't establish power handler\n"); 431 432 /* 433 * Attach the PCI bus that hangs off of it. 434 * 435 * XXX Don't pass-through Memory Read Multiple. Should we? 436 * XXX Consult the spec... 437 */ 438 pba.pba_iot = pa->pa_iot; 439 pba.pba_memt = pa->pa_memt; 440 pba.pba_dmat = pa->pa_dmat; 441 pba.pba_dmat64 = pa->pa_dmat64; 442 pba.pba_pc = pc; 443 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY; 444 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata); 445 pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata); 446 pba.pba_bridgetag = &sc->sc_tag; 447 pba.pba_intrswiz = pa->pa_intrswiz; 448 pba.pba_intrtag = pa->pa_intrtag; 449 450 config_found_ia(self, "pcibus", &pba, pcibusprint); 451 } 452 453 static int 454 ppbdetach(device_t self, int flags) 455 { 456 #ifdef PPB_USEINTR 457 struct ppb_softc *sc = device_private(self); 458 pcireg_t slcsr; 459 #endif 460 int rc; 461 462 if ((rc = config_detach_children(self, flags)) != 0) 463 return rc; 464 465 #ifdef PPB_USEINTR 466 if (sc->sc_intrhand != NULL) { 467 /* Detach event counters */ 468 evcnt_detach(&sc->sc_ev_intr); 469 evcnt_detach(&sc->sc_ev_abp); 470 evcnt_detach(&sc->sc_ev_pfd); 471 evcnt_detach(&sc->sc_ev_msc); 472 evcnt_detach(&sc->sc_ev_pdc); 473 evcnt_detach(&sc->sc_ev_cc); 474 evcnt_detach(&sc->sc_ev_lacs); 475 476 /* Clear any pending events and disable interrupt */ 477 slcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 478 sc->sc_pciecapoff + PCIE_SLCSR); 479 slcsr &= ~PCIE_SLCSR_ENABLE_MASK; 480 pci_conf_write(sc->sc_pc, sc->sc_tag, 481 sc->sc_pciecapoff + PCIE_SLCSR, slcsr); 482 483 /* Disestablish the interrupt handler */ 484 pci_intr_disestablish(sc->sc_pc, sc->sc_intrhand); 485 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 486 } 487 #endif 488 489 pmf_device_deregister(self); 490 return 0; 491 } 492 493 static bool 494 ppb_resume(device_t dv, const pmf_qual_t *qual) 495 { 496 struct ppb_softc *sc = device_private(dv); 497 int off; 498 pcireg_t val; 499 500 for (off = 0x40; off <= 0xff; off += 4) { 501 val = pci_conf_read(sc->sc_pc, sc->sc_tag, off); 502 if (val != sc->sc_pciconfext[(off - 0x40) / 4]) 503 pci_conf_write(sc->sc_pc, sc->sc_tag, off, 504 sc->sc_pciconfext[(off - 0x40)/4]); 505 } 506 507 return true; 508 } 509 510 static bool 511 ppb_suspend(device_t dv, const pmf_qual_t *qual) 512 { 513 struct ppb_softc *sc = device_private(dv); 514 int off; 515 516 for (off = 0x40; off <= 0xff; off += 4) 517 sc->sc_pciconfext[(off - 0x40) / 4] = 518 pci_conf_read(sc->sc_pc, sc->sc_tag, off); 519 520 return true; 521 } 522 523 static void 524 ppbchilddet(device_t self, device_t child) 525 { 526 /* we keep no references to child devices, so do nothing */ 527 } 528 529 #ifdef PPB_USEINTR 530 static int 531 ppb_intr(void *arg) 532 { 533 struct ppb_softc *sc = arg; 534 device_t dev = sc->sc_dev; 535 pcireg_t reg; 536 537 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, 538 sc->sc_pciecapoff + PCIE_SLCSR); 539 540 /* 541 * Not me. This check is only required for INTx. 542 * ppb_intr() would be spilted int ppb_intr_legacy() and ppb_intr_msi() 543 */ 544 if ((reg & PCIE_SLCSR_STATCHG_MASK) == 0) 545 return 0; 546 547 /* Clear interrupts. */ 548 pci_conf_write(sc->sc_pc, sc->sc_tag, 549 sc->sc_pciecapoff + PCIE_SLCSR, reg); 550 551 sc->sc_ev_intr.ev_count++; 552 553 /* Attention Button Pressed */ 554 if (reg & PCIE_SLCSR_ABP) { 555 sc->sc_ev_abp.ev_count++; 556 if (ppb_printevent) 557 device_printf(dev, "Attention Button Pressed\n"); 558 } 559 560 /* Power Fault Detected */ 561 if (reg & PCIE_SLCSR_PFD) { 562 sc->sc_ev_pfd.ev_count++; 563 if (ppb_printevent) 564 device_printf(dev, "Power Fault Detected\n"); 565 } 566 567 /* MRL Sensor Changed */ 568 if (reg & PCIE_SLCSR_MSC) { 569 sc->sc_ev_msc.ev_count++; 570 if (ppb_printevent) 571 device_printf(dev, "MRL Sensor Changed\n"); 572 } 573 574 /* Presence Detect Changed */ 575 if (reg & PCIE_SLCSR_PDC) { 576 sc->sc_ev_pdc.ev_count++; 577 if (ppb_printevent) 578 device_printf(dev, "Presence Detect Changed\n"); 579 if (reg & PCIE_SLCSR_PDS) { 580 /* XXX Insert */ 581 } else { 582 /* XXX Remove */ 583 } 584 } 585 586 /* Command Completed */ 587 if (reg & PCIE_SLCSR_CC) { 588 sc->sc_ev_cc.ev_count++; 589 if (ppb_printevent) 590 device_printf(dev, "Command Completed\n"); 591 } 592 593 /* Data Link Layer State Changed */ 594 if (reg & PCIE_SLCSR_LACS) { 595 sc->sc_ev_lacs.ev_count++; 596 if (ppb_printevent) 597 device_printf(dev, "Data Link Layer State Changed\n"); 598 } 599 600 return 1; 601 } 602 #endif /* PPB_USEINTR */ 603
Indexes created Fri Sep 26 20:09:58 GMT 2025