1 /* $NetBSD: svreg.h,v 1.4 2005/12/11 12:22:50 christos Exp $ */ 2 /* 3 * Copyright (c) 1998 Constantine Paul Sapuntzakis 4 * All rights reserved 5 * 6 * Author: Constantine Paul Sapuntzakis (csapuntz (at) cvs.openbsd.org) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The author's name or those of the contributors may be used to 17 * endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI BIOS Configuration area ports 35 */ 36 37 enum { 38 SV_SB_PORTBASE_SLOT = 0x10, 39 SV_ENHANCED_PORTBASE_SLOT = 0x14, 40 SV_FM_PORTBASE_SLOT = 0x18, 41 SV_MIDI_PORTBASE_SLOT = 0x1c, 42 SV_GAME_PORTBASE_SLOT = 0x20 43 }; 44 45 /* 46 * Enhanced CODEC registers 47 * These are offset from the base specified in the PCI configuration area 48 */ 49 enum { 50 SV_CODEC_CONTROL = 0, 51 SV_CODEC_INTMASK = 1, 52 SV_CODEC_STATUS = 2, 53 SV_CODEC_IADDR = 4, 54 SV_CODEC_IDATA = 5 55 }; 56 57 /* 58 * DMA Configuration register 59 */ 60 61 enum { 62 SV_DMAA_CONFIG_OFF = 0x40, 63 SV_DMAC_CONFIG_OFF = 0x48 64 }; 65 #define SV_DMAA_SIZE 0x10 66 #define SV_DMAA_ALIGN 0x10 67 #define SV_DMAC_SIZE 0x10 68 #define SV_DMAC_ALIGN 0x10 69 70 enum { 71 SV_DMA_CHANNEL_ENABLE = 0x1, 72 SV_DMAA_EXTENDED_ADDR = 0x8, 73 SV_DMA_PORTBASE_MASK = 0xFFFFFFF0 74 }; 75 76 77 enum { 78 SV_DMA_ADDR0 = 0, 79 SV_DMA_ADDR1 = 1, 80 SV_DMA_ADDR2 = 2, 81 SV_DMA_ADDR3 = 3, 82 SV_DMA_COUNT0 = 4, 83 SV_DMA_COUNT1 = 5, 84 SV_DMA_COUNT2 = 6, 85 SV_DMA_CMDSTATUS = 8, 86 SV_DMA_MODE = 0xB, 87 SV_DMA_MASTERCLEAR = 0xD, 88 SV_DMA_MASK = 0xF 89 }; 90 91 92 /* 93 * DMA Mode (see reg 0xB) 94 */ 95 96 enum { 97 SV_DMA_MODE_IOR_MASK = 0x0C, 98 SV_DMA_MODE_IOW_MASK = 0x0C, 99 SV_DMA_MODE_IOR = 0x04, 100 SV_DMA_MODE_IOW = 0x08, 101 SV_DMA_MODE_AUTOINIT = 0x10 102 }; 103 104 enum { 105 SV_CTL_ENHANCED = 0x01, 106 SV_CTL_MD1 = 0x04, 107 SV_CTL_FWS = 0x08, 108 SV_CTL_INTA = 0x20, 109 SV_CTL_RESET = 0x80 110 }; 111 112 enum { 113 SV_INTMASK_DMAA = 0x1, 114 SV_INTMASK_DMAC = 0x4, 115 SV_INTMASK_SINT = 0x8, 116 SV_INTMASK_UD = 0x40, 117 SV_INTMASK_MIDI = 0x80 118 }; 119 120 enum { 121 SV_INTSTATUS_DMAA = 0x1, 122 SV_INTSTATUS_DMAC = 0x4, 123 SV_INTSTATUS_SINT = 0x8, 124 SV_INTSTATUS_UD = 0x40, 125 SV_INTSTATUS_MIDI = 0x80 126 }; 127 128 enum { 129 SV_IADDR_MASK = 0x3f, 130 SV_IADDR_MCE = 0x40, 131 /* TRD = DMA Transfer request disable */ 132 SV_IADDR_TRD = 0x80 133 }; 134 135 136 enum { 137 SV_LEFT_ADC_INPUT_CONTROL = 0x0, 138 SV_RIGHT_ADC_INPUT_CONTROL = 0x1, 139 SV_LEFT_AUX1_INPUT_CONTROL = 0x2, 140 SV_RIGHT_AUX1_INPUT_CONTROL = 0x3, 141 SV_LEFT_CD_INPUT_CONTROL = 0x4, 142 SV_RIGHT_CD_INPUT_CONTROL = 0x5, 143 SV_LEFT_LINE_IN_INPUT_CONTROL = 0x6, 144 SV_RIGHT_LINE_IN_INPUT_CONTROL = 0x7, 145 SV_MIC_INPUT_CONTROL = 0x8, 146 SV_GAME_PORT_CONTROL = 0x9, 147 SV_LEFT_SYNTH_INPUT_CONTROL = 0x0A, 148 SV_RIGHT_SYNTH_INPUT_CONTROL = 0x0B, 149 SV_LEFT_AUX2_INPUT_CONTROL = 0x0C, 150 SV_RIGHT_AUX2_INPUT_CONTROL = 0x0D, 151 SV_LEFT_MIXER_OUTPUT_CONTROL = 0x0E, 152 SV_RIGHT_MIXER_OUTPUT_CONTROL = 0x0F, 153 SV_LEFT_PCM_INPUT_CONTROL = 0x10, 154 SV_RIGHT_PCM_INPUT_CONTROL = 0x11, 155 SV_DMA_DATA_FORMAT = 0x12, 156 SV_PLAY_RECORD_ENABLE = 0x13, 157 SV_UP_DOWN_CONTROL = 0x14, 158 SV_REVISION_LEVEL = 0x15, 159 SV_MONITOR_CONTROL = 0x16, 160 SV_DMAA_COUNT1 = 0x18, 161 SV_DMAA_COUNT0 = 0x19, 162 SV_DMAC_COUNT1 = 0x1C, 163 SV_DMAC_COUNT0 = 0x1d, 164 SV_PCM_SAMPLE_RATE_0 = 0x1e, 165 SV_PCM_SAMPLE_RATE_1 = 0x1f, 166 SV_SYNTH_SAMPLE_RATE_0 = 0x20, 167 SV_SYNTH_SAMPLE_RATE_1 = 0x21, 168 SV_ADC_CLOCK_SOURCE = 0x22, 169 SV_ADC_ALT_SAMPLE_RATE = 0x23, 170 SV_ADC_PLL_M = 0x24, 171 SV_ADC_PLL_N = 0x25, 172 SV_SYNTH_PLL_M = 0x26, 173 SV_SYNTH_PLL_N = 0x27, 174 SV_MPU401 = 0x2A, 175 SV_DRIVE_CONTROL = 0x2B, 176 SV_SRS_SPACE_CONTROL = 0x2c, 177 SV_SRS_CENTER_CONTROL = 0x2d, 178 SV_WAVETABLE_SOURCE_SELECT = 0x2e, 179 SV_ANALOG_POWER_DOWN_CONTROL = 0x30, 180 SV_DIGITAL_POWER_DOWN_CONTROL = 0x31 181 }; 182 183 enum { 184 SV_MUTE_BIT = 0x80, 185 SV_AUX1_MASK = 0x1F, 186 SV_CD_MASK = 0x1F, 187 SV_LINE_IN_MASK = 0x1F, 188 SV_MIC_MASK = 0x0F, 189 SV_SYNTH_MASK = 0x1F, 190 SV_AUX2_MASK = 0x1F, 191 SV_MIXER_OUT_MASK = 0x1F, 192 SV_PCM_MASK = 0x3F 193 }; 194 195 enum { 196 SV_DMAA_STEREO = 0x1, 197 SV_DMAA_FORMAT16 = 0x2, 198 SV_DMAC_STEREO = 0x10, 199 SV_DMAC_FORMAT16 = 0x20 200 }; 201 202 enum { 203 SV_PLAY_ENABLE = 0x1, 204 SV_RECORD_ENABLE = 0x2 205 }; 206 207 enum { 208 SV_PLL_R_SHIFT = 5 209 }; 210 211 /* ADC input source (registers 0 & 1) */ 212 enum { 213 SV_REC_SOURCE_MASK = 0xE0, 214 SV_REC_SOURCE_SHIFT = 5, 215 SV_MIC_BOOST_BIT = 0x10, 216 SV_REC_GAIN_MASK = 0x0F, 217 SV_REC_CD = 1, 218 SV_REC_DAC = 2, 219 SV_REC_AUX2 = 3, 220 SV_REC_LINE = 4, 221 SV_REC_AUX1 = 5, 222 SV_REC_MIC = 6, 223 SV_REC_MIXER = 7 224 }; 225 226 /* SRS Space control register (reg 0x2C) */ 227 228 enum { 229 SV_SRS_SPACE_ONOFF = 0x80 230 }; 231 232 enum { 233 SV_WSS_WT0 = 0x01, 234 SV_WSS_WT1 = 0x02, 235 }; 236
Indexes created Wed Oct 01 19:09:53 GMT 2025