1 /* $NetBSD: unichromeaccel.h,v 1.1 2006/08/13 20:26:55 jmcneill Exp $ */ 2 3 /* 4 * Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved. 5 * Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sub license, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 */ 26 27 #ifndef _DEV_PCI_UNICHROMEACCEL_H 28 #define _DEV_PCI_UNICHROMEACCEL_H 29 30 /* To be included in fb.h */ 31 #ifndef FB_ACCEL_VIA_UNICHROME 32 #define FB_ACCEL_VIA_UNICHROME 50 33 #endif 34 35 /* MMIO Base Address Definition */ 36 #define MMIO_VGABASE 0x8000 37 #define MMIO_CR_READ MMIO_VGABASE + 0x3D4 38 #define MMIO_CR_WRITE MMIO_VGABASE + 0x3D5 39 #define MMIO_SR_READ MMIO_VGABASE + 0x3C4 40 #define MMIO_SR_WRITE MMIO_VGABASE + 0x3C5 41 42 #define MMIO_OUT8(reg, val) \ 43 bus_space_write_1(sc->sc_memt, sc->sc_memh, reg, val) 44 #define MMIO_OUT16(reg, val) \ 45 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, val) 46 #define MMIO_OUT32(reg, val) \ 47 bus_space_write_4(sc->sc_memt, sc->sc_memh, reg, val) 48 #define MMIO_IN8(reg) \ 49 bus_space_read_1(sc->sc_memt, sc->sc_memh, reg) 50 #define MMIO_IN16(reg) \ 51 bus_space_read_2(sc->sc_memt, sc->sc_memh, reg) 52 #define MMIO_IN32(reg) \ 53 bus_space_read_4(sc->sc_memt, sc->sc_memh, reg) 54 55 /* HW Cursor Status Define */ 56 #define HW_Cursor_ON 0 57 #define HW_Cursor_OFF 1 58 59 /* Initial HW cursor flag */ 60 #if 0 61 static int MAX_CURS = 32; 62 static int HW_Cursor_Init = 1; 63 #endif 64 65 #define CURSOR_SIZE (8 * 1024) 66 #define VQ_SIZE (256 * 1024) 67 68 #define VIA_MMIO_BLTBASE 0x200000 69 #define VIA_MMIO_BLTSIZE 0x200000 70 71 /* Defines for 2D registers */ 72 #define VIA_REG_GECMD 0x000 73 #define VIA_REG_GEMODE 0x004 74 #define VIA_REG_SRCPOS 0x008 75 #define VIA_REG_DSTPOS 0x00C 76 #define VIA_REG_DIMENSION 0x010 /* width and height */ 77 #define VIA_REG_PATADDR 0x014 78 #define VIA_REG_FGCOLOR 0x018 79 #define VIA_REG_BGCOLOR 0x01C 80 #define VIA_REG_CLIPTL 0x020 /* top and left of clipping */ 81 #define VIA_REG_CLIPBR 0x024 /* bottom and right of clipping */ 82 #define VIA_REG_OFFSET 0x028 83 #define VIA_REG_KEYCONTROL 0x02C /* color key control */ 84 #define VIA_REG_SRCBASE 0x030 85 #define VIA_REG_DSTBASE 0x034 86 #define VIA_REG_PITCH 0x038 /* pitch of src and dst */ 87 #define VIA_REG_MONOPAT0 0x03C 88 #define VIA_REG_MONOPAT1 0x040 89 #define VIA_REG_COLORPAT 0x100 /* from 0x100 to 0x1ff */ 90 91 /* VIA_REG_PITCH(0x38): Pitch Setting */ 92 #define VIA_PITCH_ENABLE 0x80000000 93 94 /* defines for VIA HW cursor registers */ 95 #define VIA_REG_CURSOR_MODE 0x2D0 96 #define VIA_REG_CURSOR_POS 0x2D4 97 #define VIA_REG_CURSOR_ORG 0x2D8 98 #define VIA_REG_CURSOR_BG 0x2DC 99 #define VIA_REG_CURSOR_FG 0x2E0 100 101 /* VIA_REG_GEMODE(0x04): GE mode */ 102 #define VIA_GEM_8bpp 0x00000000 103 #define VIA_GEM_16bpp 0x00000100 104 #define VIA_GEM_32bpp 0x00000300 105 106 /* defines for VIA 3D registers */ 107 #define VIA_REG_STATUS 0x400 108 #define VIA_REG_TRANSET 0x43C 109 #define VIA_REG_TRANSPACE 0x440 110 111 /* VIA_REG_STATUS(0x400): Engine Status */ 112 #define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ 113 #define VIA_2D_ENG_BUSY 0x00000001 /* 2D Engine is busy */ 114 #define VIA_3D_ENG_BUSY 0x00000002 /* 3D Engine is busy */ 115 #define VIA_VR_QUEUE_BUSY 0x00020000 /* Virtual Queue is busy */ 116 117 #define MAXLOOP 0xFFFFFF 118 119 #endif /* _DEV_PCI_UNICHROMEACCEL_H */ 120
Indexes created Mon Sep 22 05:09:51 GMT 2025