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viaide.c revision 1.41.4.1
      1  1.41.4.1     skrll /*	$NetBSD: viaide.c,v 1.41.4.1 2007/09/03 10:21:09 skrll Exp $	*/
      2       1.1    bouyer 
      3       1.1    bouyer /*
      4       1.1    bouyer  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
      5       1.1    bouyer  *
      6       1.1    bouyer  * Redistribution and use in source and binary forms, with or without
      7       1.1    bouyer  * modification, are permitted provided that the following conditions
      8       1.1    bouyer  * are met:
      9       1.1    bouyer  * 1. Redistributions of source code must retain the above copyright
     10       1.1    bouyer  *    notice, this list of conditions and the following disclaimer.
     11       1.1    bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     12       1.1    bouyer  *    notice, this list of conditions and the following disclaimer in the
     13       1.1    bouyer  *    documentation and/or other materials provided with the distribution.
     14       1.1    bouyer  * 3. All advertising materials mentioning features or use of this software
     15       1.1    bouyer  *    must display the following acknowledgement:
     16       1.1    bouyer  *	This product includes software developed by Manuel Bouyer.
     17       1.1    bouyer  * 4. The name of the author may not be used to endorse or promote products
     18       1.1    bouyer  *    derived from this software without specific prior written permission.
     19       1.1    bouyer  *
     20       1.1    bouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21       1.1    bouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22       1.1    bouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23      1.24     perry  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24       1.1    bouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25       1.1    bouyer  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26       1.1    bouyer  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27       1.1    bouyer  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28       1.1    bouyer  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29       1.1    bouyer  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30       1.1    bouyer  *
     31       1.1    bouyer  */
     32       1.1    bouyer 
     33      1.25     lukem #include <sys/cdefs.h>
     34  1.41.4.1     skrll __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.41.4.1 2007/09/03 10:21:09 skrll Exp $");
     35      1.25     lukem 
     36       1.1    bouyer #include <sys/param.h>
     37       1.1    bouyer #include <sys/systm.h>
     38       1.1    bouyer 
     39       1.1    bouyer #include <dev/pci/pcivar.h>
     40       1.1    bouyer #include <dev/pci/pcidevs.h>
     41       1.1    bouyer #include <dev/pci/pciidereg.h>
     42       1.1    bouyer #include <dev/pci/pciidevar.h>
     43       1.1    bouyer #include <dev/pci/pciide_apollo_reg.h>
     44       1.1    bouyer 
     45       1.5      fvdl static int	via_pcib_match(struct pci_attach_args *);
     46       1.4     enami static void	via_chip_map(struct pciide_softc *, struct pci_attach_args *);
     47      1.35    bouyer static int	via_sata_chip_map_common(struct pciide_softc *,
     48      1.35    bouyer 		    struct pci_attach_args *);
     49       1.4     enami static void	via_sata_chip_map(struct pciide_softc *,
     50      1.35    bouyer 		    struct pci_attach_args *, int);
     51      1.35    bouyer static void	via_sata_chip_map_0(struct pciide_softc *,
     52      1.35    bouyer 		    struct pci_attach_args *);
     53      1.35    bouyer static void	via_sata_chip_map_6(struct pciide_softc *,
     54      1.35    bouyer 		    struct pci_attach_args *);
     55      1.35    bouyer static void	via_sata_chip_map_7(struct pciide_softc *,
     56      1.35    bouyer 		    struct pci_attach_args *);
     57      1.35    bouyer static void	via_sata_chip_map_new(struct pciide_softc *,
     58       1.4     enami 		    struct pci_attach_args *);
     59      1.15   thorpej static void	via_setup_channel(struct ata_channel *);
     60       1.4     enami 
     61       1.4     enami static int	viaide_match(struct device *, struct cfdata *, void *);
     62       1.4     enami static void	viaide_attach(struct device *, struct device *, void *);
     63       1.4     enami static const struct pciide_product_desc *
     64       1.4     enami 		viaide_lookup(pcireg_t);
     65       1.1    bouyer 
     66       1.1    bouyer CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
     67       1.1    bouyer     viaide_match, viaide_attach, NULL, NULL);
     68       1.1    bouyer 
     69       1.2   thorpej static const struct pciide_product_desc pciide_amd_products[] =  {
     70       1.1    bouyer 	{ PCI_PRODUCT_AMD_PBC756_IDE,
     71       1.1    bouyer 	  0,
     72       1.1    bouyer 	  "Advanced Micro Devices AMD756 IDE Controller",
     73       1.1    bouyer 	  via_chip_map
     74       1.1    bouyer 	},
     75       1.1    bouyer 	{ PCI_PRODUCT_AMD_PBC766_IDE,
     76       1.1    bouyer 	  0,
     77       1.1    bouyer 	  "Advanced Micro Devices AMD766 IDE Controller",
     78       1.1    bouyer 	  via_chip_map
     79       1.1    bouyer 	},
     80       1.1    bouyer 	{ PCI_PRODUCT_AMD_PBC768_IDE,
     81       1.1    bouyer 	  0,
     82       1.1    bouyer 	  "Advanced Micro Devices AMD768 IDE Controller",
     83       1.1    bouyer 	  via_chip_map
     84       1.1    bouyer 	},
     85       1.1    bouyer 	{ PCI_PRODUCT_AMD_PBC8111_IDE,
     86       1.1    bouyer 	  0,
     87       1.1    bouyer 	  "Advanced Micro Devices AMD8111 IDE Controller",
     88       1.1    bouyer 	  via_chip_map
     89       1.1    bouyer 	},
     90      1.38     isaki 	{ PCI_PRODUCT_AMD_CS5536_IDE,
     91      1.38     isaki 	  0,
     92      1.38     isaki 	  "Advanced Micro Devices CS5536 IDE Controller",
     93      1.38     isaki 	  via_chip_map
     94      1.38     isaki 	},
     95       1.1    bouyer 	{ 0,
     96       1.1    bouyer 	  0,
     97       1.1    bouyer 	  NULL,
     98       1.1    bouyer 	  NULL
     99       1.1    bouyer 	}
    100       1.1    bouyer };
    101       1.1    bouyer 
    102       1.2   thorpej static const struct pciide_product_desc pciide_nvidia_products[] = {
    103       1.1    bouyer 	{ PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
    104       1.1    bouyer 	  0,
    105       1.1    bouyer 	  "NVIDIA nForce IDE Controller",
    106       1.1    bouyer 	  via_chip_map
    107       1.1    bouyer 	},
    108       1.1    bouyer 	{ PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
    109       1.1    bouyer 	  0,
    110       1.1    bouyer 	  "NVIDIA nForce2 IDE Controller",
    111       1.1    bouyer 	  via_chip_map
    112       1.1    bouyer 	},
    113      1.20  jdolecek 	{ PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
    114      1.20  jdolecek 	  0,
    115      1.20  jdolecek 	  "NVIDIA nForce2 Ultra 400 IDE Controller",
    116      1.20  jdolecek 	  via_chip_map
    117      1.20  jdolecek 	},
    118      1.20  jdolecek 	{ PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
    119      1.20  jdolecek 	  0,
    120      1.20  jdolecek 	  "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
    121      1.35    bouyer 	  via_sata_chip_map_6
    122      1.20  jdolecek 	},
    123      1.10      fvdl 	{ PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
    124      1.10      fvdl 	  0,
    125      1.10      fvdl 	  "NVIDIA nForce3 IDE Controller",
    126      1.10      fvdl 	  via_chip_map
    127      1.10      fvdl 	},
    128      1.19   xtraeme 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
    129      1.19   xtraeme 	  0,
    130      1.19   xtraeme 	  "NVIDIA nForce3 250 IDE Controller",
    131      1.19   xtraeme 	  via_chip_map
    132      1.19   xtraeme 	},
    133      1.19   xtraeme 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
    134      1.19   xtraeme 	  0,
    135      1.19   xtraeme 	  "NVIDIA nForce3 250 Serial ATA Controller",
    136      1.35    bouyer 	  via_sata_chip_map_6
    137      1.19   xtraeme 	},
    138      1.32   xtraeme 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
    139      1.32   xtraeme 	  0,
    140      1.32   xtraeme 	  "NVIDIA nForce3 250 Serial ATA Controller",
    141      1.35    bouyer 	  via_sata_chip_map_6
    142      1.32   xtraeme 	},
    143      1.21      kent 	{ PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
    144      1.21      kent 	  0,
    145      1.21      kent 	  "NVIDIA nForce4 IDE Controller",
    146      1.21      kent 	  via_chip_map
    147      1.21      kent 	},
    148      1.21      kent 	{ PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
    149      1.21      kent 	  0,
    150      1.21      kent 	  "NVIDIA nForce4 Serial ATA Controller",
    151      1.35    bouyer 	  via_sata_chip_map_6
    152      1.21      kent 	},
    153      1.21      kent 	{ PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
    154      1.21      kent 	  0,
    155      1.21      kent 	  "NVIDIA nForce4 Serial ATA Controller",
    156      1.35    bouyer 	  via_sata_chip_map_6
    157      1.21      kent 	},
    158      1.27      manu 	{ PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
    159      1.27      manu 	  0,
    160      1.27      manu 	  "NVIDIA nForce430 IDE Controller",
    161      1.27      manu 	  via_chip_map
    162      1.27      manu 	},
    163      1.27      manu 	{ PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
    164      1.27      manu 	  0,
    165      1.27      manu 	  "NVIDIA nForce430 Serial ATA Controller",
    166      1.35    bouyer 	  via_sata_chip_map_6
    167      1.27      manu 	},
    168      1.27      manu 	{ PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
    169      1.27      manu 	  0,
    170      1.27      manu 	  "NVIDIA nForce430 Serial ATA Controller",
    171      1.35    bouyer 	  via_sata_chip_map_6
    172      1.27      manu 	},
    173      1.30   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP04_IDE,
    174      1.30   xtraeme 	  0,
    175      1.30   xtraeme 	  "NVIDIA MCP04 IDE Controller",
    176      1.30   xtraeme 	  via_chip_map
    177      1.30   xtraeme 	},
    178      1.30   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP04_SATA,
    179      1.30   xtraeme 	  0,
    180      1.31   xtraeme 	  "NVIDIA MCP04 Serial ATA Controller",
    181      1.35    bouyer 	  via_sata_chip_map_6
    182      1.30   xtraeme 	},
    183      1.30   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP04_SATA2,
    184      1.30   xtraeme 	  0,
    185      1.31   xtraeme 	  "NVIDIA MCP04 Serial ATA Controller",
    186      1.35    bouyer 	  via_sata_chip_map_6
    187      1.30   xtraeme 	},
    188      1.30   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP55_IDE,
    189      1.30   xtraeme 	  0,
    190      1.30   xtraeme 	  "NVIDIA MCP55 IDE Controller",
    191      1.30   xtraeme 	  via_chip_map
    192      1.30   xtraeme 	},
    193      1.30   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP55_SATA,
    194      1.30   xtraeme 	  0,
    195      1.31   xtraeme 	  "NVIDIA MCP55 Serial ATA Controller",
    196      1.35    bouyer 	  via_sata_chip_map_6
    197      1.30   xtraeme 	},
    198      1.30   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP55_SATA2,
    199      1.30   xtraeme 	  0,
    200      1.31   xtraeme 	  "NVIDIA MCP55 Serial ATA Controller",
    201      1.35    bouyer 	  via_sata_chip_map_6
    202      1.30   xtraeme 	},
    203      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP61_IDE,
    204      1.33   xtraeme 	  0,
    205      1.33   xtraeme 	  "NVIDIA MCP61 IDE Controller",
    206      1.33   xtraeme 	  via_chip_map
    207      1.33   xtraeme 	},
    208      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP65_IDE,
    209      1.33   xtraeme 	  0,
    210      1.33   xtraeme 	  "NVIDIA MCP65 IDE Controller",
    211      1.33   xtraeme 	  via_chip_map
    212      1.33   xtraeme 	},
    213      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA,
    214      1.33   xtraeme 	  0,
    215      1.33   xtraeme 	  "NVIDIA MCP61 Serial ATA Controller",
    216      1.35    bouyer 	  via_sata_chip_map_6
    217      1.33   xtraeme 	},
    218      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA2,
    219      1.33   xtraeme 	  0,
    220      1.33   xtraeme 	  "NVIDIA MCP61 Serial ATA Controller",
    221      1.35    bouyer 	  via_sata_chip_map_6
    222      1.33   xtraeme 	},
    223      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA3,
    224      1.33   xtraeme 	  0,
    225      1.33   xtraeme 	  "NVIDIA MCP61 Serial ATA Controller",
    226      1.35    bouyer 	  via_sata_chip_map_6
    227      1.33   xtraeme 	},
    228      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA,
    229      1.33   xtraeme 	  0,
    230      1.33   xtraeme 	  "NVIDIA MCP65 Serial ATA Controller",
    231      1.35    bouyer 	  via_sata_chip_map_6
    232      1.33   xtraeme 	},
    233      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA2,
    234      1.33   xtraeme 	  0,
    235      1.33   xtraeme 	  "NVIDIA MCP65 Serial ATA Controller",
    236      1.35    bouyer 	  via_sata_chip_map_6
    237      1.33   xtraeme 	},
    238      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA3,
    239      1.33   xtraeme 	  0,
    240      1.33   xtraeme 	  "NVIDIA MCP65 Serial ATA Controller",
    241      1.35    bouyer 	  via_sata_chip_map_6
    242      1.33   xtraeme 	},
    243      1.33   xtraeme 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA4,
    244      1.33   xtraeme 	  0,
    245      1.33   xtraeme 	  "NVIDIA MCP65 Serial ATA Controller",
    246      1.35    bouyer 	  via_sata_chip_map_6
    247      1.33   xtraeme 	},
    248  1.41.4.1     skrll 	{ PCI_PRODUCT_NVIDIA_MCP67_IDE,
    249  1.41.4.1     skrll 	  0,
    250  1.41.4.1     skrll 	  "NVIDIA MCP67 IDE Controller",
    251  1.41.4.1     skrll 	  via_chip_map,
    252  1.41.4.1     skrll 	},
    253  1.41.4.1     skrll 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA,
    254  1.41.4.1     skrll 	  0,
    255  1.41.4.1     skrll 	  "NVIDIA MCP67 Serial ATA Controller",
    256  1.41.4.1     skrll 	  via_sata_chip_map_6,
    257  1.41.4.1     skrll 	},
    258  1.41.4.1     skrll 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA2,
    259  1.41.4.1     skrll 	  0,
    260  1.41.4.1     skrll 	  "NVIDIA MCP67 Serial ATA Controller",
    261  1.41.4.1     skrll 	  via_sata_chip_map_6,
    262  1.41.4.1     skrll 	},
    263  1.41.4.1     skrll 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA3,
    264  1.41.4.1     skrll 	  0,
    265  1.41.4.1     skrll 	  "NVIDIA MCP67 Serial ATA Controller",
    266  1.41.4.1     skrll 	  via_sata_chip_map_6,
    267  1.41.4.1     skrll 	},
    268  1.41.4.1     skrll 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA4,
    269  1.41.4.1     skrll 	  0,
    270  1.41.4.1     skrll 	  "NVIDIA MCP67 Serial ATA Controller",
    271  1.41.4.1     skrll 	  via_sata_chip_map_6,
    272  1.41.4.1     skrll 	},
    273       1.1    bouyer 	{ 0,
    274       1.1    bouyer 	  0,
    275       1.1    bouyer 	  NULL,
    276       1.1    bouyer 	  NULL
    277       1.1    bouyer 	}
    278       1.1    bouyer };
    279       1.1    bouyer 
    280       1.2   thorpej static const struct pciide_product_desc pciide_via_products[] =  {
    281       1.1    bouyer 	{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
    282       1.1    bouyer 	  0,
    283       1.1    bouyer 	  NULL,
    284       1.1    bouyer 	  via_chip_map,
    285       1.1    bouyer 	 },
    286       1.1    bouyer 	{ PCI_PRODUCT_VIATECH_VT82C586A_IDE,
    287       1.1    bouyer 	  0,
    288       1.1    bouyer 	  NULL,
    289       1.1    bouyer 	  via_chip_map,
    290       1.1    bouyer 	},
    291  1.41.4.1     skrll 	{ PCI_PRODUCT_VIATECH_CX700_IDE,
    292  1.41.4.1     skrll 	  0,
    293  1.41.4.1     skrll 	  NULL,
    294  1.41.4.1     skrll 	  via_chip_map,
    295  1.41.4.1     skrll 	},
    296      1.23       abs 	{ PCI_PRODUCT_VIATECH_VT6421_RAID,
    297      1.22       abs 	  0,
    298      1.23       abs 	  "VIA Technologies VT6421 Serial RAID Controller",
    299      1.35    bouyer 	  via_sata_chip_map_new,
    300      1.22       abs 	},
    301       1.1    bouyer 	{ PCI_PRODUCT_VIATECH_VT8237_SATA,
    302       1.6   mycroft 	  0,
    303       1.1    bouyer 	  "VIA Technologies VT8237 SATA Controller",
    304      1.35    bouyer 	  via_sata_chip_map_7,
    305      1.35    bouyer 	},
    306      1.35    bouyer 	{ PCI_PRODUCT_VIATECH_VT8237A_SATA,
    307      1.35    bouyer 	  0,
    308      1.35    bouyer 	  "VIA Technologies VT8237A SATA Controller",
    309      1.41   garbled 	  via_sata_chip_map_7,
    310       1.1    bouyer 	},
    311      1.29   xtraeme 	{ PCI_PRODUCT_VIATECH_VT8237R_SATA,
    312      1.29   xtraeme 	  0,
    313      1.29   xtraeme 	  "VIA Technologies VT8237R SATA Controller",
    314      1.35    bouyer 	  via_sata_chip_map_0,
    315      1.29   xtraeme 	},
    316       1.1    bouyer 	{ 0,
    317       1.1    bouyer 	  0,
    318       1.1    bouyer 	  NULL,
    319       1.1    bouyer 	  NULL
    320       1.1    bouyer 	}
    321       1.1    bouyer };
    322       1.1    bouyer 
    323       1.4     enami static const struct pciide_product_desc *
    324       1.4     enami viaide_lookup(pcireg_t id)
    325       1.4     enami {
    326       1.4     enami 
    327       1.4     enami 	switch (PCI_VENDOR(id)) {
    328       1.4     enami 	case PCI_VENDOR_VIATECH:
    329       1.4     enami 		return (pciide_lookup_product(id, pciide_via_products));
    330       1.4     enami 
    331       1.4     enami 	case PCI_VENDOR_AMD:
    332       1.4     enami 		return (pciide_lookup_product(id, pciide_amd_products));
    333       1.4     enami 
    334       1.4     enami 	case PCI_VENDOR_NVIDIA:
    335       1.4     enami 		return (pciide_lookup_product(id, pciide_nvidia_products));
    336       1.4     enami 	}
    337       1.4     enami 	return (NULL);
    338       1.4     enami }
    339       1.4     enami 
    340       1.2   thorpej static int
    341      1.37  christos viaide_match(struct device *parent, struct cfdata *match,
    342      1.34  christos     void *aux)
    343       1.1    bouyer {
    344       1.1    bouyer 	struct pci_attach_args *pa = aux;
    345       1.1    bouyer 
    346       1.4     enami 	if (viaide_lookup(pa->pa_id) != NULL)
    347       1.4     enami 		return (2);
    348       1.1    bouyer 	return (0);
    349       1.1    bouyer }
    350       1.1    bouyer 
    351       1.2   thorpej static void
    352      1.37  christos viaide_attach(struct device *parent, struct device *self, void *aux)
    353       1.1    bouyer {
    354       1.1    bouyer 	struct pci_attach_args *pa = aux;
    355       1.1    bouyer 	struct pciide_softc *sc = (struct pciide_softc *)self;
    356       1.4     enami 	const struct pciide_product_desc *pp;
    357       1.1    bouyer 
    358       1.4     enami 	pp = viaide_lookup(pa->pa_id);
    359       1.1    bouyer 	if (pp == NULL)
    360       1.1    bouyer 		panic("viaide_attach");
    361       1.1    bouyer 	pciide_common_attach(sc, pa, pp);
    362       1.1    bouyer }
    363       1.1    bouyer 
    364       1.5      fvdl static int
    365       1.5      fvdl via_pcib_match(struct pci_attach_args *pa)
    366       1.5      fvdl {
    367       1.5      fvdl 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
    368       1.5      fvdl 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
    369       1.5      fvdl 	    PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
    370       1.5      fvdl 		return (1);
    371       1.5      fvdl 	return 0;
    372       1.5      fvdl }
    373       1.5      fvdl 
    374       1.2   thorpej static void
    375       1.2   thorpej via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    376       1.1    bouyer {
    377       1.1    bouyer 	struct pciide_channel *cp;
    378       1.1    bouyer 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    379       1.1    bouyer 	pcireg_t vendor = PCI_VENDOR(pa->pa_id);
    380       1.1    bouyer 	int channel;
    381       1.1    bouyer 	u_int32_t ideconf;
    382       1.1    bouyer 	bus_size_t cmdsize, ctlsize;
    383       1.1    bouyer 	pcireg_t pcib_id, pcib_class;
    384       1.5      fvdl 	struct pci_attach_args pcib_pa;
    385       1.1    bouyer 
    386       1.1    bouyer 	if (pciide_chipen(sc, pa) == 0)
    387       1.1    bouyer 		return;
    388       1.1    bouyer 
    389       1.3     enami 	switch (vendor) {
    390       1.1    bouyer 	case PCI_VENDOR_VIATECH:
    391       1.1    bouyer 		/*
    392       1.5      fvdl 		 * get a PCI tag for the ISA bridge.
    393       1.1    bouyer 		 */
    394      1.12  drochner 		if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
    395       1.5      fvdl 			goto unknown;
    396       1.5      fvdl 		pcib_id = pcib_pa.pa_id;
    397       1.5      fvdl 		pcib_class = pcib_pa.pa_class;
    398       1.1    bouyer 		aprint_normal("%s: VIA Technologies ",
    399      1.17   thorpej 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    400       1.1    bouyer 		switch (PCI_PRODUCT(pcib_id)) {
    401       1.1    bouyer 		case PCI_PRODUCT_VIATECH_VT82C586_ISA:
    402       1.1    bouyer 			aprint_normal("VT82C586 (Apollo VP) ");
    403       1.1    bouyer 			if(PCI_REVISION(pcib_class) >= 0x02) {
    404       1.1    bouyer 				aprint_normal("ATA33 controller\n");
    405      1.17   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    406       1.1    bouyer 			} else {
    407       1.1    bouyer 				aprint_normal("controller\n");
    408      1.17   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
    409       1.1    bouyer 			}
    410       1.1    bouyer 			break;
    411       1.1    bouyer 		case PCI_PRODUCT_VIATECH_VT82C596A:
    412       1.1    bouyer 			aprint_normal("VT82C596A (Apollo Pro) ");
    413       1.1    bouyer 			if (PCI_REVISION(pcib_class) >= 0x12) {
    414       1.1    bouyer 				aprint_normal("ATA66 controller\n");
    415      1.17   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    416       1.1    bouyer 			} else {
    417       1.1    bouyer 				aprint_normal("ATA33 controller\n");
    418      1.17   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    419       1.1    bouyer 			}
    420       1.1    bouyer 			break;
    421       1.1    bouyer 		case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
    422       1.1    bouyer 			aprint_normal("VT82C686A (Apollo KX133) ");
    423       1.1    bouyer 			if (PCI_REVISION(pcib_class) >= 0x40) {
    424       1.1    bouyer 				aprint_normal("ATA100 controller\n");
    425      1.17   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    426       1.1    bouyer 			} else {
    427       1.1    bouyer 				aprint_normal("ATA66 controller\n");
    428      1.17   thorpej 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    429       1.1    bouyer 			}
    430       1.1    bouyer 			break;
    431       1.1    bouyer 		case PCI_PRODUCT_VIATECH_VT8231:
    432       1.1    bouyer 			aprint_normal("VT8231 ATA100 controller\n");
    433      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    434       1.1    bouyer 			break;
    435       1.1    bouyer 		case PCI_PRODUCT_VIATECH_VT8233:
    436       1.1    bouyer 			aprint_normal("VT8233 ATA100 controller\n");
    437      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    438       1.1    bouyer 			break;
    439       1.1    bouyer 		case PCI_PRODUCT_VIATECH_VT8233A:
    440       1.1    bouyer 			aprint_normal("VT8233A ATA133 controller\n");
    441      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    442       1.1    bouyer 			break;
    443       1.1    bouyer 		case PCI_PRODUCT_VIATECH_VT8235:
    444       1.1    bouyer 			aprint_normal("VT8235 ATA133 controller\n");
    445      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    446       1.1    bouyer 			break;
    447       1.5      fvdl 		case PCI_PRODUCT_VIATECH_VT8237:
    448       1.1    bouyer 			aprint_normal("VT8237 ATA133 controller\n");
    449      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    450       1.1    bouyer 			break;
    451      1.40   mlelstv 		case PCI_PRODUCT_VIATECH_VT8237A_ISA:
    452      1.40   mlelstv 			aprint_normal("VT8237A ATA133 controller\n");
    453      1.40   mlelstv 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    454      1.40   mlelstv 			break;
    455  1.41.4.1     skrll 		case PCI_PRODUCT_VIATECH_CX700_IDE:
    456  1.41.4.1     skrll 			aprint_normal("CX700 ATA133 controller\n");
    457  1.41.4.1     skrll 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    458  1.41.4.1     skrll 			break;
    459       1.1    bouyer 		default:
    460       1.5      fvdl unknown:
    461       1.1    bouyer 			aprint_normal("unknown VIA ATA controller\n");
    462      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
    463       1.1    bouyer 		}
    464       1.1    bouyer 		sc->sc_apo_regbase = APO_VIA_REGBASE;
    465       1.1    bouyer 		break;
    466       1.1    bouyer 	case PCI_VENDOR_AMD:
    467       1.1    bouyer 		switch (sc->sc_pp->ide_product) {
    468      1.11    bouyer 		case PCI_PRODUCT_AMD_PBC8111_IDE:
    469      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    470      1.11    bouyer 			break;
    471       1.1    bouyer 		case PCI_PRODUCT_AMD_PBC766_IDE:
    472       1.1    bouyer 		case PCI_PRODUCT_AMD_PBC768_IDE:
    473      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    474       1.1    bouyer 			break;
    475       1.1    bouyer 		default:
    476      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    477       1.1    bouyer 		}
    478       1.1    bouyer 		sc->sc_apo_regbase = APO_AMD_REGBASE;
    479       1.1    bouyer 		break;
    480       1.1    bouyer 	case PCI_VENDOR_NVIDIA:
    481       1.1    bouyer 		switch (sc->sc_pp->ide_product) {
    482       1.1    bouyer 		case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
    483      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    484       1.1    bouyer 			break;
    485       1.1    bouyer 		case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
    486      1.20  jdolecek 		case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
    487       1.5      fvdl 		case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
    488      1.19   xtraeme 		case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
    489      1.21      kent 		case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
    490      1.28   xtraeme 		case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
    491      1.30   xtraeme 		case PCI_PRODUCT_NVIDIA_MCP04_IDE:
    492      1.30   xtraeme 		case PCI_PRODUCT_NVIDIA_MCP55_IDE:
    493      1.33   xtraeme 		case PCI_PRODUCT_NVIDIA_MCP61_IDE:
    494      1.33   xtraeme 		case PCI_PRODUCT_NVIDIA_MCP65_IDE:
    495  1.41.4.1     skrll 		case PCI_PRODUCT_NVIDIA_MCP67_IDE:
    496      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    497       1.1    bouyer 			break;
    498       1.1    bouyer 		}
    499       1.1    bouyer 		sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
    500       1.1    bouyer 		break;
    501       1.1    bouyer 	default:
    502       1.1    bouyer 		panic("via_chip_map: unknown vendor");
    503       1.1    bouyer 	}
    504       1.3     enami 
    505      1.39        ad 	aprint_verbose("%s: bus-master DMA support present",
    506      1.17   thorpej 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    507       1.1    bouyer 	pciide_mapreg_dma(sc, pa);
    508      1.39        ad 	aprint_verbose("\n");
    509      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    510       1.1    bouyer 	if (sc->sc_dma_ok) {
    511      1.17   thorpej 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
    512       1.1    bouyer 		sc->sc_wdcdev.irqack = pciide_irqack;
    513      1.17   thorpej 		if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
    514      1.17   thorpej 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    515       1.1    bouyer 	}
    516      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    517      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    518      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
    519      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    520      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    521       1.1    bouyer 
    522      1.41   garbled 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
    523      1.41   garbled 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
    524      1.41   garbled 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
    525      1.41   garbled 
    526      1.15   thorpej 	wdc_allocate_regs(&sc->sc_wdcdev);
    527      1.15   thorpej 
    528      1.14   thorpej 	ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
    529       1.1    bouyer 	    "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
    530       1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
    531       1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
    532       1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
    533       1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
    534       1.1    bouyer 	    DEBUG_PROBE);
    535       1.1    bouyer 
    536       1.1    bouyer 	ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
    537      1.17   thorpej 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    538      1.17   thorpej 	     channel++) {
    539       1.1    bouyer 		cp = &sc->pciide_channels[channel];
    540       1.1    bouyer 		if (pciide_chansetup(sc, channel, interface) == 0)
    541       1.1    bouyer 			continue;
    542       1.1    bouyer 
    543       1.1    bouyer 		if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
    544       1.1    bouyer 			aprint_normal("%s: %s channel ignored (disabled)\n",
    545      1.17   thorpej 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
    546      1.15   thorpej 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
    547       1.1    bouyer 			continue;
    548       1.1    bouyer 		}
    549       1.1    bouyer 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
    550       1.1    bouyer 		    pciide_pci_intr);
    551       1.1    bouyer 	}
    552       1.1    bouyer }
    553       1.1    bouyer 
    554       1.2   thorpej static void
    555      1.15   thorpej via_setup_channel(struct ata_channel *chp)
    556       1.1    bouyer {
    557       1.1    bouyer 	u_int32_t udmatim_reg, datatim_reg;
    558       1.1    bouyer 	u_int8_t idedma_ctl;
    559      1.18   thorpej 	int mode, drive, s;
    560       1.1    bouyer 	struct ata_drive_datas *drvp;
    561      1.17   thorpej 	struct atac_softc *atac = chp->ch_atac;
    562      1.16   thorpej 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    563      1.16   thorpej 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    564       1.1    bouyer #ifndef PCIIDE_AMD756_ENABLEDMA
    565       1.1    bouyer 	int rev = PCI_REVISION(
    566       1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
    567       1.1    bouyer #endif
    568       1.1    bouyer 
    569       1.1    bouyer 	idedma_ctl = 0;
    570       1.1    bouyer 	datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
    571       1.1    bouyer 	udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
    572       1.9   thorpej 	datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
    573       1.9   thorpej 	udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
    574       1.1    bouyer 
    575       1.1    bouyer 	/* setup DMA if needed */
    576       1.1    bouyer 	pciide_channel_dma_setup(cp);
    577       1.1    bouyer 
    578       1.1    bouyer 	for (drive = 0; drive < 2; drive++) {
    579       1.1    bouyer 		drvp = &chp->ch_drive[drive];
    580       1.1    bouyer 		/* If no drive, skip */
    581       1.1    bouyer 		if ((drvp->drive_flags & DRIVE) == 0)
    582       1.1    bouyer 			continue;
    583       1.1    bouyer 		/* add timing values, setup DMA if needed */
    584       1.1    bouyer 		if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
    585       1.1    bouyer 		    (drvp->drive_flags & DRIVE_UDMA) == 0)) {
    586       1.1    bouyer 			mode = drvp->PIO_mode;
    587       1.1    bouyer 			goto pio;
    588       1.1    bouyer 		}
    589      1.17   thorpej 		if ((atac->atac_cap & ATAC_CAP_UDMA) &&
    590       1.1    bouyer 		    (drvp->drive_flags & DRIVE_UDMA)) {
    591       1.1    bouyer 			/* use Ultra/DMA */
    592      1.18   thorpej 			s = splbio();
    593       1.1    bouyer 			drvp->drive_flags &= ~DRIVE_DMA;
    594      1.18   thorpej 			splx(s);
    595       1.9   thorpej 			udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
    596       1.9   thorpej 			    APO_UDMA_EN_MTH(chp->ch_channel, drive);
    597       1.3     enami 			switch (PCI_VENDOR(sc->sc_pci_id)) {
    598       1.1    bouyer 			case PCI_VENDOR_VIATECH:
    599      1.17   thorpej 				if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
    600       1.1    bouyer 					/* 8233a */
    601       1.1    bouyer 					udmatim_reg |= APO_UDMA_TIME(
    602       1.9   thorpej 					    chp->ch_channel,
    603       1.1    bouyer 					    drive,
    604       1.1    bouyer 					    via_udma133_tim[drvp->UDMA_mode]);
    605      1.17   thorpej 				} else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
    606       1.1    bouyer 					/* 686b */
    607       1.1    bouyer 					udmatim_reg |= APO_UDMA_TIME(
    608       1.9   thorpej 					    chp->ch_channel,
    609       1.1    bouyer 					    drive,
    610       1.1    bouyer 					    via_udma100_tim[drvp->UDMA_mode]);
    611      1.17   thorpej 				} else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
    612       1.1    bouyer 					/* 596b or 686a */
    613       1.1    bouyer 					udmatim_reg |= APO_UDMA_CLK66(
    614       1.9   thorpej 					    chp->ch_channel);
    615       1.1    bouyer 					udmatim_reg |= APO_UDMA_TIME(
    616       1.9   thorpej 					    chp->ch_channel,
    617       1.1    bouyer 					    drive,
    618       1.1    bouyer 					    via_udma66_tim[drvp->UDMA_mode]);
    619       1.1    bouyer 				} else {
    620       1.1    bouyer 					/* 596a or 586b */
    621       1.1    bouyer 					udmatim_reg |= APO_UDMA_TIME(
    622       1.9   thorpej 					    chp->ch_channel,
    623       1.1    bouyer 					    drive,
    624       1.1    bouyer 					    via_udma33_tim[drvp->UDMA_mode]);
    625       1.1    bouyer 				}
    626       1.1    bouyer 				break;
    627       1.1    bouyer 			case PCI_VENDOR_AMD:
    628       1.1    bouyer 			case PCI_VENDOR_NVIDIA:
    629       1.9   thorpej 				udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
    630       1.1    bouyer 				    drive, amd7x6_udma_tim[drvp->UDMA_mode]);
    631       1.1    bouyer 				 break;
    632       1.1    bouyer 			}
    633       1.1    bouyer 			/* can use PIO timings, MW DMA unused */
    634       1.1    bouyer 			mode = drvp->PIO_mode;
    635       1.1    bouyer 		} else {
    636       1.1    bouyer 			/* use Multiword DMA, but only if revision is OK */
    637      1.18   thorpej 			s = splbio();
    638       1.1    bouyer 			drvp->drive_flags &= ~DRIVE_UDMA;
    639      1.18   thorpej 			splx(s);
    640       1.1    bouyer #ifndef PCIIDE_AMD756_ENABLEDMA
    641       1.1    bouyer 			/*
    642       1.1    bouyer 			 * The workaround doesn't seem to be necessary
    643       1.1    bouyer 			 * with all drives, so it can be disabled by
    644       1.1    bouyer 			 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
    645       1.1    bouyer 			 * triggered.
    646       1.1    bouyer 			 */
    647       1.1    bouyer 			if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
    648       1.1    bouyer 			    sc->sc_pp->ide_product ==
    649       1.3     enami 			    PCI_PRODUCT_AMD_PBC756_IDE &&
    650       1.1    bouyer 			    AMD756_CHIPREV_DISABLEDMA(rev)) {
    651       1.1    bouyer 				aprint_normal(
    652       1.1    bouyer 				    "%s:%d:%d: multi-word DMA disabled due "
    653       1.1    bouyer 				    "to chip revision\n",
    654      1.17   thorpej 				    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    655       1.9   thorpej 				    chp->ch_channel, drive);
    656       1.1    bouyer 				mode = drvp->PIO_mode;
    657      1.18   thorpej 				s = splbio();
    658       1.1    bouyer 				drvp->drive_flags &= ~DRIVE_DMA;
    659      1.18   thorpej 				splx(s);
    660       1.1    bouyer 				goto pio;
    661       1.1    bouyer 			}
    662       1.1    bouyer #endif
    663       1.1    bouyer 			/* mode = min(pio, dma+2) */
    664       1.3     enami 			if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
    665       1.1    bouyer 				mode = drvp->PIO_mode;
    666       1.1    bouyer 			else
    667       1.1    bouyer 				mode = drvp->DMA_mode + 2;
    668       1.1    bouyer 		}
    669       1.1    bouyer 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    670       1.1    bouyer 
    671       1.1    bouyer pio:		/* setup PIO mode */
    672       1.1    bouyer 		if (mode <= 2) {
    673       1.1    bouyer 			drvp->DMA_mode = 0;
    674       1.1    bouyer 			drvp->PIO_mode = 0;
    675       1.1    bouyer 			mode = 0;
    676       1.1    bouyer 		} else {
    677       1.1    bouyer 			drvp->PIO_mode = mode;
    678       1.1    bouyer 			drvp->DMA_mode = mode - 2;
    679       1.1    bouyer 		}
    680       1.1    bouyer 		datatim_reg |=
    681       1.9   thorpej 		    APO_DATATIM_PULSE(chp->ch_channel, drive,
    682       1.1    bouyer 			apollo_pio_set[mode]) |
    683       1.9   thorpej 		    APO_DATATIM_RECOV(chp->ch_channel, drive,
    684       1.1    bouyer 			apollo_pio_rec[mode]);
    685       1.1    bouyer 	}
    686       1.1    bouyer 	if (idedma_ctl != 0) {
    687       1.1    bouyer 		/* Add software bits in status register */
    688       1.7      fvdl 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    689       1.1    bouyer 		    idedma_ctl);
    690       1.1    bouyer 	}
    691       1.1    bouyer 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
    692       1.1    bouyer 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
    693      1.14   thorpej 	ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
    694       1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
    695       1.1    bouyer 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
    696       1.1    bouyer }
    697       1.1    bouyer 
    698      1.35    bouyer static int
    699      1.35    bouyer via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa)
    700       1.1    bouyer {
    701      1.35    bouyer 	bus_size_t satasize;
    702      1.36    bouyer 	int maptype, ret;
    703       1.1    bouyer 
    704       1.1    bouyer 	if (pciide_chipen(sc, pa) == 0)
    705      1.35    bouyer 		return 0;
    706       1.1    bouyer 
    707      1.39        ad 	aprint_verbose("%s: bus-master DMA support present",
    708      1.17   thorpej 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    709       1.1    bouyer 	pciide_mapreg_dma(sc, pa);
    710      1.39        ad 	aprint_verbose("\n");
    711       1.1    bouyer 
    712       1.1    bouyer 	if (sc->sc_dma_ok) {
    713      1.17   thorpej 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
    714       1.1    bouyer 		sc->sc_wdcdev.irqack = pciide_irqack;
    715       1.1    bouyer 	}
    716      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    717      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    718      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    719      1.17   thorpej 
    720      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    721      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    722      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    723      1.17   thorpej 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
    724       1.1    bouyer 
    725      1.41   garbled 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
    726      1.41   garbled 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
    727      1.41   garbled 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
    728      1.41   garbled 
    729      1.15   thorpej 	wdc_allocate_regs(&sc->sc_wdcdev);
    730      1.36    bouyer 	maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
    731      1.36    bouyer 	    PCI_MAPREG_START + 0x14);
    732      1.36    bouyer 	switch(maptype) {
    733      1.36    bouyer 	case PCI_MAPREG_TYPE_IO:
    734      1.36    bouyer 		ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
    735      1.36    bouyer 		    PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
    736      1.36    bouyer 		    NULL, &satasize);
    737      1.36    bouyer 		break;
    738      1.36    bouyer 	case PCI_MAPREG_MEM_TYPE_32BIT:
    739      1.36    bouyer 		ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
    740      1.35    bouyer 		    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
    741      1.35    bouyer 		    0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
    742      1.36    bouyer 		    NULL, &satasize);
    743      1.36    bouyer 		break;
    744      1.36    bouyer 	default:
    745      1.36    bouyer 		aprint_error("%s: couldn't map sata regs, unsupported"
    746      1.36    bouyer 		    "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    747      1.36    bouyer 		    maptype);
    748      1.36    bouyer 		return 0;
    749      1.36    bouyer 	}
    750      1.36    bouyer 	if (ret != 0) {
    751      1.36    bouyer 		aprint_error("%s: couldn't map sata regs\n",
    752      1.36    bouyer 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    753      1.36    bouyer 		return 0;
    754      1.35    bouyer 	}
    755      1.35    bouyer 	return 1;
    756      1.35    bouyer }
    757      1.35    bouyer 
    758      1.35    bouyer static void
    759      1.35    bouyer via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa,
    760      1.35    bouyer     int satareg_shift)
    761      1.35    bouyer {
    762      1.35    bouyer 	struct pciide_channel *cp;
    763      1.35    bouyer 	struct ata_channel *wdc_cp;
    764      1.35    bouyer 	struct wdc_regs *wdr;
    765      1.35    bouyer 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    766      1.35    bouyer 	int channel;
    767      1.35    bouyer 	bus_size_t cmdsize, ctlsize;
    768      1.35    bouyer 
    769      1.35    bouyer 	if (via_sata_chip_map_common(sc, pa) == 0)
    770      1.35    bouyer 		return;
    771      1.35    bouyer 
    772      1.35    bouyer 	if (interface == 0) {
    773      1.35    bouyer 		ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
    774      1.35    bouyer 		    DEBUG_PROBE);
    775      1.35    bouyer 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    776      1.35    bouyer 		    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    777      1.35    bouyer 	}
    778      1.15   thorpej 
    779      1.17   thorpej 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    780      1.17   thorpej 	     channel++) {
    781       1.1    bouyer 		cp = &sc->pciide_channels[channel];
    782       1.1    bouyer 		if (pciide_chansetup(sc, channel, interface) == 0)
    783       1.1    bouyer 			continue;
    784      1.35    bouyer 		wdc_cp = &cp->ata_channel;
    785      1.35    bouyer 		wdr = CHAN_TO_WDC_REGS(wdc_cp);
    786      1.35    bouyer 		wdr->sata_iot = sc->sc_ba5_st;
    787      1.35    bouyer 		wdr->sata_baseioh = sc->sc_ba5_sh;
    788      1.35    bouyer 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    789      1.35    bouyer 		    (wdc_cp->ch_channel << satareg_shift) + 0x0, 1,
    790      1.35    bouyer 		    &wdr->sata_status) != 0) {
    791      1.35    bouyer 			aprint_error("%s: couldn't map channel %d "
    792      1.35    bouyer 			    "sata_status regs\n",
    793      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    794      1.35    bouyer 			    wdc_cp->ch_channel);
    795      1.35    bouyer 			continue;
    796      1.35    bouyer 		}
    797      1.35    bouyer 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    798      1.35    bouyer 		    (wdc_cp->ch_channel << satareg_shift) + 0x4, 1,
    799      1.35    bouyer 		    &wdr->sata_error) != 0) {
    800      1.35    bouyer 			aprint_error("%s: couldn't map channel %d "
    801      1.35    bouyer 			    "sata_error regs\n",
    802      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    803      1.35    bouyer 			    wdc_cp->ch_channel);
    804      1.35    bouyer 			continue;
    805      1.35    bouyer 		}
    806      1.35    bouyer 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    807      1.35    bouyer 		    (wdc_cp->ch_channel << satareg_shift) + 0x8, 1,
    808      1.35    bouyer 		    &wdr->sata_control) != 0) {
    809      1.35    bouyer 			aprint_error("%s: couldn't map channel %d "
    810      1.35    bouyer 			    "sata_control regs\n",
    811      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    812      1.35    bouyer 			    wdc_cp->ch_channel);
    813      1.35    bouyer 			continue;
    814      1.35    bouyer 		}
    815      1.35    bouyer 		sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
    816       1.1    bouyer 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
    817       1.3     enami 		    pciide_pci_intr);
    818       1.1    bouyer 	}
    819       1.1    bouyer }
    820      1.35    bouyer 
    821      1.35    bouyer static void
    822      1.35    bouyer via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa)
    823      1.35    bouyer {
    824      1.35    bouyer 	via_sata_chip_map(sc, pa, 0);
    825      1.35    bouyer }
    826      1.35    bouyer 
    827      1.35    bouyer static void
    828      1.35    bouyer via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa)
    829      1.35    bouyer {
    830      1.35    bouyer 	via_sata_chip_map(sc, pa, 6);
    831      1.35    bouyer }
    832      1.35    bouyer 
    833      1.35    bouyer static void
    834      1.35    bouyer via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa)
    835      1.35    bouyer {
    836      1.35    bouyer 	via_sata_chip_map(sc, pa, 7);
    837      1.35    bouyer }
    838      1.35    bouyer 
    839      1.35    bouyer static void
    840      1.35    bouyer via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa)
    841      1.35    bouyer {
    842      1.35    bouyer 	struct pciide_channel *cp;
    843      1.35    bouyer 	struct ata_channel *wdc_cp;
    844      1.35    bouyer 	struct wdc_regs *wdr;
    845      1.35    bouyer 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    846      1.35    bouyer 	int channel;
    847      1.35    bouyer 	bus_size_t cmdsize;
    848      1.35    bouyer 	pci_intr_handle_t intrhandle;
    849      1.35    bouyer 	const char *intrstr;
    850      1.35    bouyer 	int i;
    851      1.35    bouyer 
    852      1.35    bouyer 	if (via_sata_chip_map_common(sc, pa) == 0)
    853      1.35    bouyer 		return;
    854      1.35    bouyer 
    855      1.35    bouyer 	if (interface == 0) {
    856      1.35    bouyer 		ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
    857      1.35    bouyer 		    DEBUG_PROBE);
    858      1.35    bouyer 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    859      1.35    bouyer 		    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    860      1.35    bouyer 	}
    861      1.35    bouyer 
    862      1.35    bouyer 	if (pci_intr_map(pa, &intrhandle) != 0) {
    863      1.35    bouyer 		aprint_error("%s: couldn't map native-PCI interrupt\n",
    864      1.35    bouyer 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    865      1.35    bouyer 		return;
    866      1.35    bouyer 	}
    867      1.35    bouyer 	intrstr = pci_intr_string(pa->pa_pc, intrhandle);
    868      1.35    bouyer 	sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
    869      1.35    bouyer 	    intrhandle, IPL_BIO, pciide_pci_intr, sc);
    870      1.35    bouyer 	if (sc->sc_pci_ih == NULL) {
    871      1.35    bouyer 		aprint_error(
    872      1.35    bouyer 		    "%s: couldn't establish native-PCI interrupt",
    873      1.35    bouyer 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    874      1.35    bouyer 		if (intrstr != NULL)
    875      1.35    bouyer 		    aprint_error(" at %s", intrstr);
    876      1.35    bouyer 		aprint_error("\n");
    877      1.35    bouyer 		return;
    878      1.35    bouyer 	}
    879      1.35    bouyer 	aprint_normal("%s: using %s for native-PCI interrupt\n",
    880      1.35    bouyer 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    881      1.35    bouyer 	    intrstr ? intrstr : "unknown interrupt");
    882      1.35    bouyer 
    883      1.35    bouyer 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    884      1.35    bouyer 	     channel++) {
    885      1.35    bouyer 		cp = &sc->pciide_channels[channel];
    886      1.35    bouyer 		if (pciide_chansetup(sc, channel, interface) == 0)
    887      1.35    bouyer 			continue;
    888      1.35    bouyer 		cp->ata_channel.ch_ndrive = 1;
    889      1.35    bouyer 		wdc_cp = &cp->ata_channel;
    890      1.35    bouyer 		wdr = CHAN_TO_WDC_REGS(wdc_cp);
    891      1.35    bouyer 
    892      1.35    bouyer 		wdr->sata_iot = sc->sc_ba5_st;
    893      1.35    bouyer 		wdr->sata_baseioh = sc->sc_ba5_sh;
    894      1.35    bouyer 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    895      1.35    bouyer 		    (wdc_cp->ch_channel << 6) + 0x0, 1,
    896      1.35    bouyer 		    &wdr->sata_status) != 0) {
    897      1.35    bouyer 			aprint_error("%s: couldn't map channel %d "
    898      1.35    bouyer 			    "sata_status regs\n",
    899      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    900      1.35    bouyer 			    wdc_cp->ch_channel);
    901      1.35    bouyer 			continue;
    902      1.35    bouyer 		}
    903      1.35    bouyer 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    904      1.35    bouyer 		    (wdc_cp->ch_channel << 6) + 0x4, 1,
    905      1.35    bouyer 		    &wdr->sata_error) != 0) {
    906      1.35    bouyer 			aprint_error("%s: couldn't map channel %d "
    907      1.35    bouyer 			    "sata_error regs\n",
    908      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    909      1.35    bouyer 			    wdc_cp->ch_channel);
    910      1.35    bouyer 			continue;
    911      1.35    bouyer 		}
    912      1.35    bouyer 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    913      1.35    bouyer 		    (wdc_cp->ch_channel << 6) + 0x8, 1,
    914      1.35    bouyer 		    &wdr->sata_control) != 0) {
    915      1.35    bouyer 			aprint_error("%s: couldn't map channel %d "
    916      1.35    bouyer 			    "sata_control regs\n",
    917      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    918      1.35    bouyer 			    wdc_cp->ch_channel);
    919      1.35    bouyer 			continue;
    920      1.35    bouyer 		}
    921      1.35    bouyer 		sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
    922      1.35    bouyer 
    923      1.35    bouyer 		if (pci_mapreg_map(pa, (0x10 + (4 * (channel))),
    924      1.35    bouyer 		    PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
    925      1.35    bouyer 		    NULL, &cmdsize) != 0) {
    926      1.35    bouyer 			aprint_error("%s: couldn't map %s channel regs\n",
    927      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    928      1.35    bouyer 			    cp->name);
    929      1.35    bouyer 		}
    930      1.35    bouyer 		wdr->ctl_iot = wdr->cmd_iot;
    931      1.35    bouyer 		for (i = 0; i < WDC_NREG; i++) {
    932      1.35    bouyer 			if (bus_space_subregion(wdr->cmd_iot,
    933      1.35    bouyer 			    wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
    934      1.35    bouyer 			    &wdr->cmd_iohs[i]) != 0) {
    935      1.35    bouyer 				aprint_error("%s: couldn't subregion %s "
    936      1.35    bouyer 				    "channel cmd regs\n",
    937      1.35    bouyer 				    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    938      1.35    bouyer 				    cp->name);
    939      1.35    bouyer 				return;
    940      1.35    bouyer 			}
    941      1.35    bouyer 		}
    942      1.35    bouyer 		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
    943      1.35    bouyer 		    WDC_NREG + 2, 1,  &wdr->ctl_ioh) != 0) {
    944      1.35    bouyer 			aprint_error("%s: couldn't map channel %d ctl regs\n",
    945      1.35    bouyer 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel);
    946      1.35    bouyer 			return;
    947      1.35    bouyer 		}
    948      1.35    bouyer 		wdc_init_shadow_regs(wdc_cp);
    949      1.35    bouyer 		wdcattach(wdc_cp);
    950      1.35    bouyer 	}
    951      1.35    bouyer }
    952