viaide.c revision 1.41.8.3 1 1.41.8.3 joerg /* $NetBSD: viaide.c,v 1.41.8.3 2007/11/14 19:04:32 joerg Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.1 bouyer * must display the following acknowledgement:
16 1.1 bouyer * This product includes software developed by Manuel Bouyer.
17 1.1 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.1 bouyer * derived from this software without specific prior written permission.
19 1.1 bouyer *
20 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.24 perry * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 bouyer *
31 1.1 bouyer */
32 1.1 bouyer
33 1.25 lukem #include <sys/cdefs.h>
34 1.41.8.3 joerg __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.41.8.3 2007/11/14 19:04:32 joerg Exp $");
35 1.25 lukem
36 1.1 bouyer #include <sys/param.h>
37 1.1 bouyer #include <sys/systm.h>
38 1.1 bouyer
39 1.1 bouyer #include <dev/pci/pcivar.h>
40 1.1 bouyer #include <dev/pci/pcidevs.h>
41 1.1 bouyer #include <dev/pci/pciidereg.h>
42 1.1 bouyer #include <dev/pci/pciidevar.h>
43 1.1 bouyer #include <dev/pci/pciide_apollo_reg.h>
44 1.1 bouyer
45 1.5 fvdl static int via_pcib_match(struct pci_attach_args *);
46 1.4 enami static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
47 1.35 bouyer static int via_sata_chip_map_common(struct pciide_softc *,
48 1.35 bouyer struct pci_attach_args *);
49 1.4 enami static void via_sata_chip_map(struct pciide_softc *,
50 1.35 bouyer struct pci_attach_args *, int);
51 1.35 bouyer static void via_sata_chip_map_0(struct pciide_softc *,
52 1.35 bouyer struct pci_attach_args *);
53 1.35 bouyer static void via_sata_chip_map_6(struct pciide_softc *,
54 1.35 bouyer struct pci_attach_args *);
55 1.35 bouyer static void via_sata_chip_map_7(struct pciide_softc *,
56 1.35 bouyer struct pci_attach_args *);
57 1.35 bouyer static void via_sata_chip_map_new(struct pciide_softc *,
58 1.4 enami struct pci_attach_args *);
59 1.15 thorpej static void via_setup_channel(struct ata_channel *);
60 1.4 enami
61 1.4 enami static int viaide_match(struct device *, struct cfdata *, void *);
62 1.4 enami static void viaide_attach(struct device *, struct device *, void *);
63 1.4 enami static const struct pciide_product_desc *
64 1.4 enami viaide_lookup(pcireg_t);
65 1.1 bouyer
66 1.1 bouyer CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
67 1.1 bouyer viaide_match, viaide_attach, NULL, NULL);
68 1.1 bouyer
69 1.2 thorpej static const struct pciide_product_desc pciide_amd_products[] = {
70 1.1 bouyer { PCI_PRODUCT_AMD_PBC756_IDE,
71 1.1 bouyer 0,
72 1.1 bouyer "Advanced Micro Devices AMD756 IDE Controller",
73 1.1 bouyer via_chip_map
74 1.1 bouyer },
75 1.1 bouyer { PCI_PRODUCT_AMD_PBC766_IDE,
76 1.1 bouyer 0,
77 1.1 bouyer "Advanced Micro Devices AMD766 IDE Controller",
78 1.1 bouyer via_chip_map
79 1.1 bouyer },
80 1.1 bouyer { PCI_PRODUCT_AMD_PBC768_IDE,
81 1.1 bouyer 0,
82 1.1 bouyer "Advanced Micro Devices AMD768 IDE Controller",
83 1.1 bouyer via_chip_map
84 1.1 bouyer },
85 1.1 bouyer { PCI_PRODUCT_AMD_PBC8111_IDE,
86 1.1 bouyer 0,
87 1.1 bouyer "Advanced Micro Devices AMD8111 IDE Controller",
88 1.1 bouyer via_chip_map
89 1.1 bouyer },
90 1.38 isaki { PCI_PRODUCT_AMD_CS5536_IDE,
91 1.38 isaki 0,
92 1.38 isaki "Advanced Micro Devices CS5536 IDE Controller",
93 1.38 isaki via_chip_map
94 1.38 isaki },
95 1.1 bouyer { 0,
96 1.1 bouyer 0,
97 1.1 bouyer NULL,
98 1.1 bouyer NULL
99 1.1 bouyer }
100 1.1 bouyer };
101 1.1 bouyer
102 1.2 thorpej static const struct pciide_product_desc pciide_nvidia_products[] = {
103 1.1 bouyer { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
104 1.1 bouyer 0,
105 1.1 bouyer "NVIDIA nForce IDE Controller",
106 1.1 bouyer via_chip_map
107 1.1 bouyer },
108 1.1 bouyer { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
109 1.1 bouyer 0,
110 1.1 bouyer "NVIDIA nForce2 IDE Controller",
111 1.1 bouyer via_chip_map
112 1.1 bouyer },
113 1.20 jdolecek { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
114 1.20 jdolecek 0,
115 1.20 jdolecek "NVIDIA nForce2 Ultra 400 IDE Controller",
116 1.20 jdolecek via_chip_map
117 1.20 jdolecek },
118 1.20 jdolecek { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
119 1.20 jdolecek 0,
120 1.20 jdolecek "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
121 1.35 bouyer via_sata_chip_map_6
122 1.20 jdolecek },
123 1.10 fvdl { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
124 1.10 fvdl 0,
125 1.10 fvdl "NVIDIA nForce3 IDE Controller",
126 1.10 fvdl via_chip_map
127 1.10 fvdl },
128 1.19 xtraeme { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
129 1.19 xtraeme 0,
130 1.19 xtraeme "NVIDIA nForce3 250 IDE Controller",
131 1.19 xtraeme via_chip_map
132 1.19 xtraeme },
133 1.19 xtraeme { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
134 1.19 xtraeme 0,
135 1.19 xtraeme "NVIDIA nForce3 250 Serial ATA Controller",
136 1.35 bouyer via_sata_chip_map_6
137 1.19 xtraeme },
138 1.32 xtraeme { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
139 1.32 xtraeme 0,
140 1.32 xtraeme "NVIDIA nForce3 250 Serial ATA Controller",
141 1.35 bouyer via_sata_chip_map_6
142 1.32 xtraeme },
143 1.21 kent { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
144 1.21 kent 0,
145 1.21 kent "NVIDIA nForce4 IDE Controller",
146 1.21 kent via_chip_map
147 1.21 kent },
148 1.21 kent { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
149 1.21 kent 0,
150 1.21 kent "NVIDIA nForce4 Serial ATA Controller",
151 1.35 bouyer via_sata_chip_map_6
152 1.21 kent },
153 1.21 kent { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
154 1.21 kent 0,
155 1.21 kent "NVIDIA nForce4 Serial ATA Controller",
156 1.35 bouyer via_sata_chip_map_6
157 1.21 kent },
158 1.27 manu { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
159 1.27 manu 0,
160 1.27 manu "NVIDIA nForce430 IDE Controller",
161 1.27 manu via_chip_map
162 1.27 manu },
163 1.27 manu { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
164 1.27 manu 0,
165 1.27 manu "NVIDIA nForce430 Serial ATA Controller",
166 1.35 bouyer via_sata_chip_map_6
167 1.27 manu },
168 1.27 manu { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
169 1.27 manu 0,
170 1.27 manu "NVIDIA nForce430 Serial ATA Controller",
171 1.35 bouyer via_sata_chip_map_6
172 1.27 manu },
173 1.30 xtraeme { PCI_PRODUCT_NVIDIA_MCP04_IDE,
174 1.30 xtraeme 0,
175 1.30 xtraeme "NVIDIA MCP04 IDE Controller",
176 1.30 xtraeme via_chip_map
177 1.30 xtraeme },
178 1.30 xtraeme { PCI_PRODUCT_NVIDIA_MCP04_SATA,
179 1.30 xtraeme 0,
180 1.31 xtraeme "NVIDIA MCP04 Serial ATA Controller",
181 1.35 bouyer via_sata_chip_map_6
182 1.30 xtraeme },
183 1.30 xtraeme { PCI_PRODUCT_NVIDIA_MCP04_SATA2,
184 1.30 xtraeme 0,
185 1.31 xtraeme "NVIDIA MCP04 Serial ATA Controller",
186 1.35 bouyer via_sata_chip_map_6
187 1.30 xtraeme },
188 1.30 xtraeme { PCI_PRODUCT_NVIDIA_MCP55_IDE,
189 1.30 xtraeme 0,
190 1.30 xtraeme "NVIDIA MCP55 IDE Controller",
191 1.30 xtraeme via_chip_map
192 1.30 xtraeme },
193 1.30 xtraeme { PCI_PRODUCT_NVIDIA_MCP55_SATA,
194 1.30 xtraeme 0,
195 1.31 xtraeme "NVIDIA MCP55 Serial ATA Controller",
196 1.35 bouyer via_sata_chip_map_6
197 1.30 xtraeme },
198 1.30 xtraeme { PCI_PRODUCT_NVIDIA_MCP55_SATA2,
199 1.30 xtraeme 0,
200 1.31 xtraeme "NVIDIA MCP55 Serial ATA Controller",
201 1.35 bouyer via_sata_chip_map_6
202 1.30 xtraeme },
203 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP61_IDE,
204 1.33 xtraeme 0,
205 1.33 xtraeme "NVIDIA MCP61 IDE Controller",
206 1.33 xtraeme via_chip_map
207 1.33 xtraeme },
208 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP65_IDE,
209 1.33 xtraeme 0,
210 1.33 xtraeme "NVIDIA MCP65 IDE Controller",
211 1.33 xtraeme via_chip_map
212 1.33 xtraeme },
213 1.41.8.3 joerg { PCI_PRODUCT_NVIDIA_MCP73_IDE,
214 1.41.8.3 joerg 0,
215 1.41.8.3 joerg "NVIDIA MCP73 IDE Controller",
216 1.41.8.3 joerg via_chip_map
217 1.41.8.3 joerg },
218 1.41.8.3 joerg { PCI_PRODUCT_NVIDIA_MCP77_IDE,
219 1.41.8.3 joerg 0,
220 1.41.8.3 joerg "NVIDIA MCP77 IDE Controller",
221 1.41.8.3 joerg via_chip_map
222 1.41.8.3 joerg },
223 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP61_SATA,
224 1.33 xtraeme 0,
225 1.33 xtraeme "NVIDIA MCP61 Serial ATA Controller",
226 1.35 bouyer via_sata_chip_map_6
227 1.33 xtraeme },
228 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP61_SATA2,
229 1.33 xtraeme 0,
230 1.33 xtraeme "NVIDIA MCP61 Serial ATA Controller",
231 1.35 bouyer via_sata_chip_map_6
232 1.33 xtraeme },
233 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP61_SATA3,
234 1.33 xtraeme 0,
235 1.33 xtraeme "NVIDIA MCP61 Serial ATA Controller",
236 1.35 bouyer via_sata_chip_map_6
237 1.33 xtraeme },
238 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP65_SATA,
239 1.33 xtraeme 0,
240 1.33 xtraeme "NVIDIA MCP65 Serial ATA Controller",
241 1.35 bouyer via_sata_chip_map_6
242 1.33 xtraeme },
243 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP65_SATA2,
244 1.33 xtraeme 0,
245 1.33 xtraeme "NVIDIA MCP65 Serial ATA Controller",
246 1.35 bouyer via_sata_chip_map_6
247 1.33 xtraeme },
248 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP65_SATA3,
249 1.33 xtraeme 0,
250 1.33 xtraeme "NVIDIA MCP65 Serial ATA Controller",
251 1.35 bouyer via_sata_chip_map_6
252 1.33 xtraeme },
253 1.33 xtraeme { PCI_PRODUCT_NVIDIA_MCP65_SATA4,
254 1.33 xtraeme 0,
255 1.33 xtraeme "NVIDIA MCP65 Serial ATA Controller",
256 1.35 bouyer via_sata_chip_map_6
257 1.33 xtraeme },
258 1.41.8.1 jmcneill { PCI_PRODUCT_NVIDIA_MCP67_IDE,
259 1.41.8.1 jmcneill 0,
260 1.41.8.1 jmcneill "NVIDIA MCP67 IDE Controller",
261 1.41.8.1 jmcneill via_chip_map,
262 1.41.8.1 jmcneill },
263 1.41.8.1 jmcneill { PCI_PRODUCT_NVIDIA_MCP67_SATA,
264 1.41.8.1 jmcneill 0,
265 1.41.8.1 jmcneill "NVIDIA MCP67 Serial ATA Controller",
266 1.41.8.1 jmcneill via_sata_chip_map_6,
267 1.41.8.1 jmcneill },
268 1.41.8.1 jmcneill { PCI_PRODUCT_NVIDIA_MCP67_SATA2,
269 1.41.8.1 jmcneill 0,
270 1.41.8.1 jmcneill "NVIDIA MCP67 Serial ATA Controller",
271 1.41.8.1 jmcneill via_sata_chip_map_6,
272 1.41.8.1 jmcneill },
273 1.41.8.1 jmcneill { PCI_PRODUCT_NVIDIA_MCP67_SATA3,
274 1.41.8.1 jmcneill 0,
275 1.41.8.1 jmcneill "NVIDIA MCP67 Serial ATA Controller",
276 1.41.8.1 jmcneill via_sata_chip_map_6,
277 1.41.8.1 jmcneill },
278 1.41.8.1 jmcneill { PCI_PRODUCT_NVIDIA_MCP67_SATA4,
279 1.41.8.1 jmcneill 0,
280 1.41.8.1 jmcneill "NVIDIA MCP67 Serial ATA Controller",
281 1.41.8.1 jmcneill via_sata_chip_map_6,
282 1.41.8.1 jmcneill },
283 1.1 bouyer { 0,
284 1.1 bouyer 0,
285 1.1 bouyer NULL,
286 1.1 bouyer NULL
287 1.1 bouyer }
288 1.1 bouyer };
289 1.1 bouyer
290 1.2 thorpej static const struct pciide_product_desc pciide_via_products[] = {
291 1.1 bouyer { PCI_PRODUCT_VIATECH_VT82C586_IDE,
292 1.1 bouyer 0,
293 1.1 bouyer NULL,
294 1.1 bouyer via_chip_map,
295 1.1 bouyer },
296 1.1 bouyer { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
297 1.1 bouyer 0,
298 1.1 bouyer NULL,
299 1.1 bouyer via_chip_map,
300 1.1 bouyer },
301 1.41.8.1 jmcneill { PCI_PRODUCT_VIATECH_CX700_IDE,
302 1.41.8.1 jmcneill 0,
303 1.41.8.1 jmcneill NULL,
304 1.41.8.1 jmcneill via_chip_map,
305 1.41.8.1 jmcneill },
306 1.23 abs { PCI_PRODUCT_VIATECH_VT6421_RAID,
307 1.22 abs 0,
308 1.23 abs "VIA Technologies VT6421 Serial RAID Controller",
309 1.35 bouyer via_sata_chip_map_new,
310 1.22 abs },
311 1.1 bouyer { PCI_PRODUCT_VIATECH_VT8237_SATA,
312 1.6 mycroft 0,
313 1.1 bouyer "VIA Technologies VT8237 SATA Controller",
314 1.35 bouyer via_sata_chip_map_7,
315 1.35 bouyer },
316 1.35 bouyer { PCI_PRODUCT_VIATECH_VT8237A_SATA,
317 1.35 bouyer 0,
318 1.35 bouyer "VIA Technologies VT8237A SATA Controller",
319 1.41 garbled via_sata_chip_map_7,
320 1.1 bouyer },
321 1.29 xtraeme { PCI_PRODUCT_VIATECH_VT8237R_SATA,
322 1.29 xtraeme 0,
323 1.29 xtraeme "VIA Technologies VT8237R SATA Controller",
324 1.35 bouyer via_sata_chip_map_0,
325 1.29 xtraeme },
326 1.1 bouyer { 0,
327 1.1 bouyer 0,
328 1.1 bouyer NULL,
329 1.1 bouyer NULL
330 1.1 bouyer }
331 1.1 bouyer };
332 1.1 bouyer
333 1.4 enami static const struct pciide_product_desc *
334 1.4 enami viaide_lookup(pcireg_t id)
335 1.4 enami {
336 1.4 enami
337 1.4 enami switch (PCI_VENDOR(id)) {
338 1.4 enami case PCI_VENDOR_VIATECH:
339 1.4 enami return (pciide_lookup_product(id, pciide_via_products));
340 1.4 enami
341 1.4 enami case PCI_VENDOR_AMD:
342 1.4 enami return (pciide_lookup_product(id, pciide_amd_products));
343 1.4 enami
344 1.4 enami case PCI_VENDOR_NVIDIA:
345 1.4 enami return (pciide_lookup_product(id, pciide_nvidia_products));
346 1.4 enami }
347 1.4 enami return (NULL);
348 1.4 enami }
349 1.4 enami
350 1.2 thorpej static int
351 1.37 christos viaide_match(struct device *parent, struct cfdata *match,
352 1.34 christos void *aux)
353 1.1 bouyer {
354 1.1 bouyer struct pci_attach_args *pa = aux;
355 1.1 bouyer
356 1.4 enami if (viaide_lookup(pa->pa_id) != NULL)
357 1.4 enami return (2);
358 1.1 bouyer return (0);
359 1.1 bouyer }
360 1.1 bouyer
361 1.2 thorpej static void
362 1.37 christos viaide_attach(struct device *parent, struct device *self, void *aux)
363 1.1 bouyer {
364 1.1 bouyer struct pci_attach_args *pa = aux;
365 1.1 bouyer struct pciide_softc *sc = (struct pciide_softc *)self;
366 1.4 enami const struct pciide_product_desc *pp;
367 1.1 bouyer
368 1.4 enami pp = viaide_lookup(pa->pa_id);
369 1.1 bouyer if (pp == NULL)
370 1.1 bouyer panic("viaide_attach");
371 1.1 bouyer pciide_common_attach(sc, pa, pp);
372 1.1 bouyer }
373 1.1 bouyer
374 1.5 fvdl static int
375 1.5 fvdl via_pcib_match(struct pci_attach_args *pa)
376 1.5 fvdl {
377 1.5 fvdl if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
378 1.5 fvdl PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
379 1.5 fvdl PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
380 1.5 fvdl return (1);
381 1.5 fvdl return 0;
382 1.5 fvdl }
383 1.5 fvdl
384 1.2 thorpej static void
385 1.2 thorpej via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
386 1.1 bouyer {
387 1.1 bouyer struct pciide_channel *cp;
388 1.1 bouyer pcireg_t interface = PCI_INTERFACE(pa->pa_class);
389 1.1 bouyer pcireg_t vendor = PCI_VENDOR(pa->pa_id);
390 1.1 bouyer int channel;
391 1.1 bouyer u_int32_t ideconf;
392 1.1 bouyer bus_size_t cmdsize, ctlsize;
393 1.1 bouyer pcireg_t pcib_id, pcib_class;
394 1.5 fvdl struct pci_attach_args pcib_pa;
395 1.1 bouyer
396 1.1 bouyer if (pciide_chipen(sc, pa) == 0)
397 1.1 bouyer return;
398 1.1 bouyer
399 1.3 enami switch (vendor) {
400 1.1 bouyer case PCI_VENDOR_VIATECH:
401 1.1 bouyer /*
402 1.5 fvdl * get a PCI tag for the ISA bridge.
403 1.1 bouyer */
404 1.12 drochner if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
405 1.5 fvdl goto unknown;
406 1.5 fvdl pcib_id = pcib_pa.pa_id;
407 1.5 fvdl pcib_class = pcib_pa.pa_class;
408 1.1 bouyer aprint_normal("%s: VIA Technologies ",
409 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
410 1.1 bouyer switch (PCI_PRODUCT(pcib_id)) {
411 1.1 bouyer case PCI_PRODUCT_VIATECH_VT82C586_ISA:
412 1.1 bouyer aprint_normal("VT82C586 (Apollo VP) ");
413 1.1 bouyer if(PCI_REVISION(pcib_class) >= 0x02) {
414 1.1 bouyer aprint_normal("ATA33 controller\n");
415 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
416 1.1 bouyer } else {
417 1.1 bouyer aprint_normal("controller\n");
418 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
419 1.1 bouyer }
420 1.1 bouyer break;
421 1.1 bouyer case PCI_PRODUCT_VIATECH_VT82C596A:
422 1.1 bouyer aprint_normal("VT82C596A (Apollo Pro) ");
423 1.1 bouyer if (PCI_REVISION(pcib_class) >= 0x12) {
424 1.1 bouyer aprint_normal("ATA66 controller\n");
425 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
426 1.1 bouyer } else {
427 1.1 bouyer aprint_normal("ATA33 controller\n");
428 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
429 1.1 bouyer }
430 1.1 bouyer break;
431 1.1 bouyer case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
432 1.1 bouyer aprint_normal("VT82C686A (Apollo KX133) ");
433 1.1 bouyer if (PCI_REVISION(pcib_class) >= 0x40) {
434 1.1 bouyer aprint_normal("ATA100 controller\n");
435 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
436 1.1 bouyer } else {
437 1.1 bouyer aprint_normal("ATA66 controller\n");
438 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
439 1.1 bouyer }
440 1.1 bouyer break;
441 1.1 bouyer case PCI_PRODUCT_VIATECH_VT8231:
442 1.1 bouyer aprint_normal("VT8231 ATA100 controller\n");
443 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
444 1.1 bouyer break;
445 1.1 bouyer case PCI_PRODUCT_VIATECH_VT8233:
446 1.1 bouyer aprint_normal("VT8233 ATA100 controller\n");
447 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
448 1.1 bouyer break;
449 1.1 bouyer case PCI_PRODUCT_VIATECH_VT8233A:
450 1.1 bouyer aprint_normal("VT8233A ATA133 controller\n");
451 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
452 1.1 bouyer break;
453 1.1 bouyer case PCI_PRODUCT_VIATECH_VT8235:
454 1.1 bouyer aprint_normal("VT8235 ATA133 controller\n");
455 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
456 1.1 bouyer break;
457 1.5 fvdl case PCI_PRODUCT_VIATECH_VT8237:
458 1.1 bouyer aprint_normal("VT8237 ATA133 controller\n");
459 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
460 1.1 bouyer break;
461 1.40 mlelstv case PCI_PRODUCT_VIATECH_VT8237A_ISA:
462 1.40 mlelstv aprint_normal("VT8237A ATA133 controller\n");
463 1.40 mlelstv sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
464 1.40 mlelstv break;
465 1.41.8.1 jmcneill case PCI_PRODUCT_VIATECH_CX700_IDE:
466 1.41.8.1 jmcneill aprint_normal("CX700 ATA133 controller\n");
467 1.41.8.1 jmcneill sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
468 1.41.8.1 jmcneill break;
469 1.1 bouyer default:
470 1.5 fvdl unknown:
471 1.1 bouyer aprint_normal("unknown VIA ATA controller\n");
472 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
473 1.1 bouyer }
474 1.1 bouyer sc->sc_apo_regbase = APO_VIA_REGBASE;
475 1.1 bouyer break;
476 1.1 bouyer case PCI_VENDOR_AMD:
477 1.1 bouyer switch (sc->sc_pp->ide_product) {
478 1.11 bouyer case PCI_PRODUCT_AMD_PBC8111_IDE:
479 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
480 1.11 bouyer break;
481 1.41.8.2 joerg case PCI_PRODUCT_AMD_CS5536_IDE:
482 1.1 bouyer case PCI_PRODUCT_AMD_PBC766_IDE:
483 1.1 bouyer case PCI_PRODUCT_AMD_PBC768_IDE:
484 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
485 1.1 bouyer break;
486 1.1 bouyer default:
487 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
488 1.1 bouyer }
489 1.1 bouyer sc->sc_apo_regbase = APO_AMD_REGBASE;
490 1.1 bouyer break;
491 1.1 bouyer case PCI_VENDOR_NVIDIA:
492 1.1 bouyer switch (sc->sc_pp->ide_product) {
493 1.1 bouyer case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
494 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
495 1.1 bouyer break;
496 1.1 bouyer case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
497 1.20 jdolecek case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
498 1.5 fvdl case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
499 1.19 xtraeme case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
500 1.21 kent case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
501 1.28 xtraeme case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
502 1.30 xtraeme case PCI_PRODUCT_NVIDIA_MCP04_IDE:
503 1.30 xtraeme case PCI_PRODUCT_NVIDIA_MCP55_IDE:
504 1.33 xtraeme case PCI_PRODUCT_NVIDIA_MCP61_IDE:
505 1.33 xtraeme case PCI_PRODUCT_NVIDIA_MCP65_IDE:
506 1.41.8.1 jmcneill case PCI_PRODUCT_NVIDIA_MCP67_IDE:
507 1.41.8.3 joerg case PCI_PRODUCT_NVIDIA_MCP73_IDE:
508 1.41.8.3 joerg case PCI_PRODUCT_NVIDIA_MCP77_IDE:
509 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
510 1.1 bouyer break;
511 1.1 bouyer }
512 1.1 bouyer sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
513 1.1 bouyer break;
514 1.1 bouyer default:
515 1.1 bouyer panic("via_chip_map: unknown vendor");
516 1.1 bouyer }
517 1.3 enami
518 1.39 ad aprint_verbose("%s: bus-master DMA support present",
519 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
520 1.1 bouyer pciide_mapreg_dma(sc, pa);
521 1.39 ad aprint_verbose("\n");
522 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
523 1.1 bouyer if (sc->sc_dma_ok) {
524 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
525 1.1 bouyer sc->sc_wdcdev.irqack = pciide_irqack;
526 1.17 thorpej if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
527 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
528 1.1 bouyer }
529 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
530 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
531 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
532 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
533 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
534 1.1 bouyer
535 1.41 garbled if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
536 1.41 garbled PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
537 1.41 garbled sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
538 1.41 garbled
539 1.15 thorpej wdc_allocate_regs(&sc->sc_wdcdev);
540 1.15 thorpej
541 1.14 thorpej ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
542 1.1 bouyer "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
543 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
544 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
545 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
546 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
547 1.1 bouyer DEBUG_PROBE);
548 1.1 bouyer
549 1.1 bouyer ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
550 1.17 thorpej for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
551 1.17 thorpej channel++) {
552 1.1 bouyer cp = &sc->pciide_channels[channel];
553 1.1 bouyer if (pciide_chansetup(sc, channel, interface) == 0)
554 1.1 bouyer continue;
555 1.1 bouyer
556 1.1 bouyer if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
557 1.1 bouyer aprint_normal("%s: %s channel ignored (disabled)\n",
558 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
559 1.15 thorpej cp->ata_channel.ch_flags |= ATACH_DISABLED;
560 1.1 bouyer continue;
561 1.1 bouyer }
562 1.1 bouyer pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
563 1.1 bouyer pciide_pci_intr);
564 1.1 bouyer }
565 1.1 bouyer }
566 1.1 bouyer
567 1.2 thorpej static void
568 1.15 thorpej via_setup_channel(struct ata_channel *chp)
569 1.1 bouyer {
570 1.1 bouyer u_int32_t udmatim_reg, datatim_reg;
571 1.1 bouyer u_int8_t idedma_ctl;
572 1.18 thorpej int mode, drive, s;
573 1.1 bouyer struct ata_drive_datas *drvp;
574 1.17 thorpej struct atac_softc *atac = chp->ch_atac;
575 1.16 thorpej struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
576 1.16 thorpej struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
577 1.1 bouyer #ifndef PCIIDE_AMD756_ENABLEDMA
578 1.1 bouyer int rev = PCI_REVISION(
579 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
580 1.1 bouyer #endif
581 1.1 bouyer
582 1.1 bouyer idedma_ctl = 0;
583 1.1 bouyer datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
584 1.1 bouyer udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
585 1.9 thorpej datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
586 1.9 thorpej udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
587 1.1 bouyer
588 1.1 bouyer /* setup DMA if needed */
589 1.1 bouyer pciide_channel_dma_setup(cp);
590 1.1 bouyer
591 1.1 bouyer for (drive = 0; drive < 2; drive++) {
592 1.1 bouyer drvp = &chp->ch_drive[drive];
593 1.1 bouyer /* If no drive, skip */
594 1.1 bouyer if ((drvp->drive_flags & DRIVE) == 0)
595 1.1 bouyer continue;
596 1.1 bouyer /* add timing values, setup DMA if needed */
597 1.1 bouyer if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
598 1.1 bouyer (drvp->drive_flags & DRIVE_UDMA) == 0)) {
599 1.1 bouyer mode = drvp->PIO_mode;
600 1.1 bouyer goto pio;
601 1.1 bouyer }
602 1.17 thorpej if ((atac->atac_cap & ATAC_CAP_UDMA) &&
603 1.1 bouyer (drvp->drive_flags & DRIVE_UDMA)) {
604 1.1 bouyer /* use Ultra/DMA */
605 1.18 thorpej s = splbio();
606 1.1 bouyer drvp->drive_flags &= ~DRIVE_DMA;
607 1.18 thorpej splx(s);
608 1.9 thorpej udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
609 1.9 thorpej APO_UDMA_EN_MTH(chp->ch_channel, drive);
610 1.3 enami switch (PCI_VENDOR(sc->sc_pci_id)) {
611 1.1 bouyer case PCI_VENDOR_VIATECH:
612 1.17 thorpej if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
613 1.1 bouyer /* 8233a */
614 1.1 bouyer udmatim_reg |= APO_UDMA_TIME(
615 1.9 thorpej chp->ch_channel,
616 1.1 bouyer drive,
617 1.1 bouyer via_udma133_tim[drvp->UDMA_mode]);
618 1.17 thorpej } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
619 1.1 bouyer /* 686b */
620 1.1 bouyer udmatim_reg |= APO_UDMA_TIME(
621 1.9 thorpej chp->ch_channel,
622 1.1 bouyer drive,
623 1.1 bouyer via_udma100_tim[drvp->UDMA_mode]);
624 1.17 thorpej } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
625 1.1 bouyer /* 596b or 686a */
626 1.1 bouyer udmatim_reg |= APO_UDMA_CLK66(
627 1.9 thorpej chp->ch_channel);
628 1.1 bouyer udmatim_reg |= APO_UDMA_TIME(
629 1.9 thorpej chp->ch_channel,
630 1.1 bouyer drive,
631 1.1 bouyer via_udma66_tim[drvp->UDMA_mode]);
632 1.1 bouyer } else {
633 1.1 bouyer /* 596a or 586b */
634 1.1 bouyer udmatim_reg |= APO_UDMA_TIME(
635 1.9 thorpej chp->ch_channel,
636 1.1 bouyer drive,
637 1.1 bouyer via_udma33_tim[drvp->UDMA_mode]);
638 1.1 bouyer }
639 1.1 bouyer break;
640 1.1 bouyer case PCI_VENDOR_AMD:
641 1.1 bouyer case PCI_VENDOR_NVIDIA:
642 1.9 thorpej udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
643 1.1 bouyer drive, amd7x6_udma_tim[drvp->UDMA_mode]);
644 1.1 bouyer break;
645 1.1 bouyer }
646 1.1 bouyer /* can use PIO timings, MW DMA unused */
647 1.1 bouyer mode = drvp->PIO_mode;
648 1.1 bouyer } else {
649 1.1 bouyer /* use Multiword DMA, but only if revision is OK */
650 1.18 thorpej s = splbio();
651 1.1 bouyer drvp->drive_flags &= ~DRIVE_UDMA;
652 1.18 thorpej splx(s);
653 1.1 bouyer #ifndef PCIIDE_AMD756_ENABLEDMA
654 1.1 bouyer /*
655 1.1 bouyer * The workaround doesn't seem to be necessary
656 1.1 bouyer * with all drives, so it can be disabled by
657 1.1 bouyer * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
658 1.1 bouyer * triggered.
659 1.1 bouyer */
660 1.1 bouyer if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
661 1.1 bouyer sc->sc_pp->ide_product ==
662 1.3 enami PCI_PRODUCT_AMD_PBC756_IDE &&
663 1.1 bouyer AMD756_CHIPREV_DISABLEDMA(rev)) {
664 1.1 bouyer aprint_normal(
665 1.1 bouyer "%s:%d:%d: multi-word DMA disabled due "
666 1.1 bouyer "to chip revision\n",
667 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
668 1.9 thorpej chp->ch_channel, drive);
669 1.1 bouyer mode = drvp->PIO_mode;
670 1.18 thorpej s = splbio();
671 1.1 bouyer drvp->drive_flags &= ~DRIVE_DMA;
672 1.18 thorpej splx(s);
673 1.1 bouyer goto pio;
674 1.1 bouyer }
675 1.1 bouyer #endif
676 1.1 bouyer /* mode = min(pio, dma+2) */
677 1.3 enami if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
678 1.1 bouyer mode = drvp->PIO_mode;
679 1.1 bouyer else
680 1.1 bouyer mode = drvp->DMA_mode + 2;
681 1.1 bouyer }
682 1.1 bouyer idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
683 1.1 bouyer
684 1.1 bouyer pio: /* setup PIO mode */
685 1.1 bouyer if (mode <= 2) {
686 1.1 bouyer drvp->DMA_mode = 0;
687 1.1 bouyer drvp->PIO_mode = 0;
688 1.1 bouyer mode = 0;
689 1.1 bouyer } else {
690 1.1 bouyer drvp->PIO_mode = mode;
691 1.1 bouyer drvp->DMA_mode = mode - 2;
692 1.1 bouyer }
693 1.1 bouyer datatim_reg |=
694 1.9 thorpej APO_DATATIM_PULSE(chp->ch_channel, drive,
695 1.1 bouyer apollo_pio_set[mode]) |
696 1.9 thorpej APO_DATATIM_RECOV(chp->ch_channel, drive,
697 1.1 bouyer apollo_pio_rec[mode]);
698 1.1 bouyer }
699 1.1 bouyer if (idedma_ctl != 0) {
700 1.1 bouyer /* Add software bits in status register */
701 1.7 fvdl bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
702 1.1 bouyer idedma_ctl);
703 1.1 bouyer }
704 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
705 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
706 1.14 thorpej ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
707 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
708 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
709 1.1 bouyer }
710 1.1 bouyer
711 1.35 bouyer static int
712 1.35 bouyer via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa)
713 1.1 bouyer {
714 1.35 bouyer bus_size_t satasize;
715 1.36 bouyer int maptype, ret;
716 1.1 bouyer
717 1.1 bouyer if (pciide_chipen(sc, pa) == 0)
718 1.35 bouyer return 0;
719 1.1 bouyer
720 1.39 ad aprint_verbose("%s: bus-master DMA support present",
721 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
722 1.1 bouyer pciide_mapreg_dma(sc, pa);
723 1.39 ad aprint_verbose("\n");
724 1.1 bouyer
725 1.1 bouyer if (sc->sc_dma_ok) {
726 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
727 1.1 bouyer sc->sc_wdcdev.irqack = pciide_irqack;
728 1.1 bouyer }
729 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
730 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
731 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
732 1.17 thorpej
733 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
734 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
735 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
736 1.17 thorpej sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
737 1.1 bouyer
738 1.41 garbled if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
739 1.41 garbled PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
740 1.41 garbled sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
741 1.41 garbled
742 1.15 thorpej wdc_allocate_regs(&sc->sc_wdcdev);
743 1.36 bouyer maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
744 1.36 bouyer PCI_MAPREG_START + 0x14);
745 1.36 bouyer switch(maptype) {
746 1.36 bouyer case PCI_MAPREG_TYPE_IO:
747 1.36 bouyer ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
748 1.36 bouyer PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
749 1.36 bouyer NULL, &satasize);
750 1.36 bouyer break;
751 1.36 bouyer case PCI_MAPREG_MEM_TYPE_32BIT:
752 1.36 bouyer ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
753 1.35 bouyer PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
754 1.35 bouyer 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
755 1.36 bouyer NULL, &satasize);
756 1.36 bouyer break;
757 1.36 bouyer default:
758 1.36 bouyer aprint_error("%s: couldn't map sata regs, unsupported"
759 1.36 bouyer "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
760 1.36 bouyer maptype);
761 1.36 bouyer return 0;
762 1.36 bouyer }
763 1.36 bouyer if (ret != 0) {
764 1.36 bouyer aprint_error("%s: couldn't map sata regs\n",
765 1.36 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
766 1.36 bouyer return 0;
767 1.35 bouyer }
768 1.35 bouyer return 1;
769 1.35 bouyer }
770 1.35 bouyer
771 1.35 bouyer static void
772 1.35 bouyer via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa,
773 1.35 bouyer int satareg_shift)
774 1.35 bouyer {
775 1.35 bouyer struct pciide_channel *cp;
776 1.35 bouyer struct ata_channel *wdc_cp;
777 1.35 bouyer struct wdc_regs *wdr;
778 1.35 bouyer pcireg_t interface = PCI_INTERFACE(pa->pa_class);
779 1.35 bouyer int channel;
780 1.35 bouyer bus_size_t cmdsize, ctlsize;
781 1.35 bouyer
782 1.35 bouyer if (via_sata_chip_map_common(sc, pa) == 0)
783 1.35 bouyer return;
784 1.35 bouyer
785 1.35 bouyer if (interface == 0) {
786 1.35 bouyer ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
787 1.35 bouyer DEBUG_PROBE);
788 1.35 bouyer interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
789 1.35 bouyer PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
790 1.35 bouyer }
791 1.15 thorpej
792 1.17 thorpej for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
793 1.17 thorpej channel++) {
794 1.1 bouyer cp = &sc->pciide_channels[channel];
795 1.1 bouyer if (pciide_chansetup(sc, channel, interface) == 0)
796 1.1 bouyer continue;
797 1.35 bouyer wdc_cp = &cp->ata_channel;
798 1.35 bouyer wdr = CHAN_TO_WDC_REGS(wdc_cp);
799 1.35 bouyer wdr->sata_iot = sc->sc_ba5_st;
800 1.35 bouyer wdr->sata_baseioh = sc->sc_ba5_sh;
801 1.35 bouyer if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
802 1.35 bouyer (wdc_cp->ch_channel << satareg_shift) + 0x0, 1,
803 1.35 bouyer &wdr->sata_status) != 0) {
804 1.35 bouyer aprint_error("%s: couldn't map channel %d "
805 1.35 bouyer "sata_status regs\n",
806 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
807 1.35 bouyer wdc_cp->ch_channel);
808 1.35 bouyer continue;
809 1.35 bouyer }
810 1.35 bouyer if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
811 1.35 bouyer (wdc_cp->ch_channel << satareg_shift) + 0x4, 1,
812 1.35 bouyer &wdr->sata_error) != 0) {
813 1.35 bouyer aprint_error("%s: couldn't map channel %d "
814 1.35 bouyer "sata_error regs\n",
815 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
816 1.35 bouyer wdc_cp->ch_channel);
817 1.35 bouyer continue;
818 1.35 bouyer }
819 1.35 bouyer if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
820 1.35 bouyer (wdc_cp->ch_channel << satareg_shift) + 0x8, 1,
821 1.35 bouyer &wdr->sata_control) != 0) {
822 1.35 bouyer aprint_error("%s: couldn't map channel %d "
823 1.35 bouyer "sata_control regs\n",
824 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
825 1.35 bouyer wdc_cp->ch_channel);
826 1.35 bouyer continue;
827 1.35 bouyer }
828 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
829 1.1 bouyer pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
830 1.3 enami pciide_pci_intr);
831 1.1 bouyer }
832 1.1 bouyer }
833 1.35 bouyer
834 1.35 bouyer static void
835 1.35 bouyer via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa)
836 1.35 bouyer {
837 1.35 bouyer via_sata_chip_map(sc, pa, 0);
838 1.35 bouyer }
839 1.35 bouyer
840 1.35 bouyer static void
841 1.35 bouyer via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa)
842 1.35 bouyer {
843 1.35 bouyer via_sata_chip_map(sc, pa, 6);
844 1.35 bouyer }
845 1.35 bouyer
846 1.35 bouyer static void
847 1.35 bouyer via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa)
848 1.35 bouyer {
849 1.35 bouyer via_sata_chip_map(sc, pa, 7);
850 1.35 bouyer }
851 1.35 bouyer
852 1.35 bouyer static void
853 1.35 bouyer via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa)
854 1.35 bouyer {
855 1.35 bouyer struct pciide_channel *cp;
856 1.35 bouyer struct ata_channel *wdc_cp;
857 1.35 bouyer struct wdc_regs *wdr;
858 1.35 bouyer pcireg_t interface = PCI_INTERFACE(pa->pa_class);
859 1.35 bouyer int channel;
860 1.35 bouyer bus_size_t cmdsize;
861 1.35 bouyer pci_intr_handle_t intrhandle;
862 1.35 bouyer const char *intrstr;
863 1.35 bouyer int i;
864 1.35 bouyer
865 1.35 bouyer if (via_sata_chip_map_common(sc, pa) == 0)
866 1.35 bouyer return;
867 1.35 bouyer
868 1.35 bouyer if (interface == 0) {
869 1.35 bouyer ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
870 1.35 bouyer DEBUG_PROBE);
871 1.35 bouyer interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
872 1.35 bouyer PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
873 1.35 bouyer }
874 1.35 bouyer
875 1.35 bouyer if (pci_intr_map(pa, &intrhandle) != 0) {
876 1.35 bouyer aprint_error("%s: couldn't map native-PCI interrupt\n",
877 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
878 1.35 bouyer return;
879 1.35 bouyer }
880 1.35 bouyer intrstr = pci_intr_string(pa->pa_pc, intrhandle);
881 1.35 bouyer sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
882 1.35 bouyer intrhandle, IPL_BIO, pciide_pci_intr, sc);
883 1.35 bouyer if (sc->sc_pci_ih == NULL) {
884 1.35 bouyer aprint_error(
885 1.35 bouyer "%s: couldn't establish native-PCI interrupt",
886 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
887 1.35 bouyer if (intrstr != NULL)
888 1.35 bouyer aprint_error(" at %s", intrstr);
889 1.35 bouyer aprint_error("\n");
890 1.35 bouyer return;
891 1.35 bouyer }
892 1.35 bouyer aprint_normal("%s: using %s for native-PCI interrupt\n",
893 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
894 1.35 bouyer intrstr ? intrstr : "unknown interrupt");
895 1.35 bouyer
896 1.35 bouyer for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
897 1.35 bouyer channel++) {
898 1.35 bouyer cp = &sc->pciide_channels[channel];
899 1.35 bouyer if (pciide_chansetup(sc, channel, interface) == 0)
900 1.35 bouyer continue;
901 1.35 bouyer cp->ata_channel.ch_ndrive = 1;
902 1.35 bouyer wdc_cp = &cp->ata_channel;
903 1.35 bouyer wdr = CHAN_TO_WDC_REGS(wdc_cp);
904 1.35 bouyer
905 1.35 bouyer wdr->sata_iot = sc->sc_ba5_st;
906 1.35 bouyer wdr->sata_baseioh = sc->sc_ba5_sh;
907 1.35 bouyer if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
908 1.35 bouyer (wdc_cp->ch_channel << 6) + 0x0, 1,
909 1.35 bouyer &wdr->sata_status) != 0) {
910 1.35 bouyer aprint_error("%s: couldn't map channel %d "
911 1.35 bouyer "sata_status regs\n",
912 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
913 1.35 bouyer wdc_cp->ch_channel);
914 1.35 bouyer continue;
915 1.35 bouyer }
916 1.35 bouyer if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
917 1.35 bouyer (wdc_cp->ch_channel << 6) + 0x4, 1,
918 1.35 bouyer &wdr->sata_error) != 0) {
919 1.35 bouyer aprint_error("%s: couldn't map channel %d "
920 1.35 bouyer "sata_error regs\n",
921 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
922 1.35 bouyer wdc_cp->ch_channel);
923 1.35 bouyer continue;
924 1.35 bouyer }
925 1.35 bouyer if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
926 1.35 bouyer (wdc_cp->ch_channel << 6) + 0x8, 1,
927 1.35 bouyer &wdr->sata_control) != 0) {
928 1.35 bouyer aprint_error("%s: couldn't map channel %d "
929 1.35 bouyer "sata_control regs\n",
930 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
931 1.35 bouyer wdc_cp->ch_channel);
932 1.35 bouyer continue;
933 1.35 bouyer }
934 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
935 1.35 bouyer
936 1.35 bouyer if (pci_mapreg_map(pa, (0x10 + (4 * (channel))),
937 1.35 bouyer PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
938 1.35 bouyer NULL, &cmdsize) != 0) {
939 1.35 bouyer aprint_error("%s: couldn't map %s channel regs\n",
940 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
941 1.35 bouyer cp->name);
942 1.35 bouyer }
943 1.35 bouyer wdr->ctl_iot = wdr->cmd_iot;
944 1.35 bouyer for (i = 0; i < WDC_NREG; i++) {
945 1.35 bouyer if (bus_space_subregion(wdr->cmd_iot,
946 1.35 bouyer wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
947 1.35 bouyer &wdr->cmd_iohs[i]) != 0) {
948 1.35 bouyer aprint_error("%s: couldn't subregion %s "
949 1.35 bouyer "channel cmd regs\n",
950 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
951 1.35 bouyer cp->name);
952 1.35 bouyer return;
953 1.35 bouyer }
954 1.35 bouyer }
955 1.35 bouyer if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
956 1.35 bouyer WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) {
957 1.35 bouyer aprint_error("%s: couldn't map channel %d ctl regs\n",
958 1.35 bouyer sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel);
959 1.35 bouyer return;
960 1.35 bouyer }
961 1.35 bouyer wdc_init_shadow_regs(wdc_cp);
962 1.35 bouyer wdcattach(wdc_cp);
963 1.35 bouyer }
964 1.35 bouyer }
965