viaide.c revision 1.10
1 /* $NetBSD: viaide.c,v 1.10 2004/02/20 16:36:29 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_apollo_reg.h> 41 42 static int via_pcib_match(struct pci_attach_args *); 43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 44 static void via_sata_chip_map(struct pciide_softc *, 45 struct pci_attach_args *); 46 static void via_setup_channel(struct wdc_channel *); 47 48 static int viaide_match(struct device *, struct cfdata *, void *); 49 static void viaide_attach(struct device *, struct device *, void *); 50 static const struct pciide_product_desc * 51 viaide_lookup(pcireg_t); 52 53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 54 viaide_match, viaide_attach, NULL, NULL); 55 56 static const struct pciide_product_desc pciide_amd_products[] = { 57 { PCI_PRODUCT_AMD_PBC756_IDE, 58 0, 59 "Advanced Micro Devices AMD756 IDE Controller", 60 via_chip_map 61 }, 62 { PCI_PRODUCT_AMD_PBC766_IDE, 63 0, 64 "Advanced Micro Devices AMD766 IDE Controller", 65 via_chip_map 66 }, 67 { PCI_PRODUCT_AMD_PBC768_IDE, 68 0, 69 "Advanced Micro Devices AMD768 IDE Controller", 70 via_chip_map 71 }, 72 { PCI_PRODUCT_AMD_PBC8111_IDE, 73 0, 74 "Advanced Micro Devices AMD8111 IDE Controller", 75 via_chip_map 76 }, 77 { 0, 78 0, 79 NULL, 80 NULL 81 } 82 }; 83 84 static const struct pciide_product_desc pciide_nvidia_products[] = { 85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 86 0, 87 "NVIDIA nForce IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 91 0, 92 "NVIDIA nForce2 IDE Controller", 93 via_chip_map 94 }, 95 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 96 0, 97 "NVIDIA nForce3 IDE Controller", 98 via_chip_map 99 }, 100 { 0, 101 0, 102 NULL, 103 NULL 104 } 105 }; 106 107 static const struct pciide_product_desc pciide_via_products[] = { 108 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 109 0, 110 NULL, 111 via_chip_map, 112 }, 113 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 114 0, 115 NULL, 116 via_chip_map, 117 }, 118 { PCI_PRODUCT_VIATECH_VT8237_SATA, 119 0, 120 "VIA Technologies VT8237 SATA Controller", 121 via_sata_chip_map, 122 }, 123 { 0, 124 0, 125 NULL, 126 NULL 127 } 128 }; 129 130 static const struct pciide_product_desc * 131 viaide_lookup(pcireg_t id) 132 { 133 134 switch (PCI_VENDOR(id)) { 135 case PCI_VENDOR_VIATECH: 136 return (pciide_lookup_product(id, pciide_via_products)); 137 138 case PCI_VENDOR_AMD: 139 return (pciide_lookup_product(id, pciide_amd_products)); 140 141 case PCI_VENDOR_NVIDIA: 142 return (pciide_lookup_product(id, pciide_nvidia_products)); 143 } 144 return (NULL); 145 } 146 147 static int 148 viaide_match(struct device *parent, struct cfdata *match, void *aux) 149 { 150 struct pci_attach_args *pa = aux; 151 152 if (viaide_lookup(pa->pa_id) != NULL) 153 return (2); 154 return (0); 155 } 156 157 static void 158 viaide_attach(struct device *parent, struct device *self, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct pciide_softc *sc = (struct pciide_softc *)self; 162 const struct pciide_product_desc *pp; 163 164 pp = viaide_lookup(pa->pa_id); 165 if (pp == NULL) 166 panic("viaide_attach"); 167 pciide_common_attach(sc, pa, pp); 168 } 169 170 static int 171 via_pcib_match(struct pci_attach_args *pa) 172 { 173 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 174 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 175 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 176 return (1); 177 return 0; 178 } 179 180 static void 181 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 182 { 183 struct pciide_channel *cp; 184 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 185 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 186 int channel; 187 u_int32_t ideconf; 188 bus_size_t cmdsize, ctlsize; 189 pcireg_t pcib_id, pcib_class; 190 struct pci_attach_args pcib_pa; 191 192 if (pciide_chipen(sc, pa) == 0) 193 return; 194 195 switch (vendor) { 196 case PCI_VENDOR_VIATECH: 197 /* 198 * get a PCI tag for the ISA bridge. 199 */ 200 if (pci_enumerate_bus( 201 (struct pci_softc *)sc->sc_wdcdev.sc_dev.dv_parent, 202 via_pcib_match, &pcib_pa) == 0) 203 goto unknown; 204 pcib_id = pcib_pa.pa_id; 205 pcib_class = pcib_pa.pa_class; 206 aprint_normal("%s: VIA Technologies ", 207 sc->sc_wdcdev.sc_dev.dv_xname); 208 switch (PCI_PRODUCT(pcib_id)) { 209 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 210 aprint_normal("VT82C586 (Apollo VP) "); 211 if(PCI_REVISION(pcib_class) >= 0x02) { 212 aprint_normal("ATA33 controller\n"); 213 sc->sc_wdcdev.UDMA_cap = 2; 214 } else { 215 aprint_normal("controller\n"); 216 sc->sc_wdcdev.UDMA_cap = 0; 217 } 218 break; 219 case PCI_PRODUCT_VIATECH_VT82C596A: 220 aprint_normal("VT82C596A (Apollo Pro) "); 221 if (PCI_REVISION(pcib_class) >= 0x12) { 222 aprint_normal("ATA66 controller\n"); 223 sc->sc_wdcdev.UDMA_cap = 4; 224 } else { 225 aprint_normal("ATA33 controller\n"); 226 sc->sc_wdcdev.UDMA_cap = 2; 227 } 228 break; 229 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 230 aprint_normal("VT82C686A (Apollo KX133) "); 231 if (PCI_REVISION(pcib_class) >= 0x40) { 232 aprint_normal("ATA100 controller\n"); 233 sc->sc_wdcdev.UDMA_cap = 5; 234 } else { 235 aprint_normal("ATA66 controller\n"); 236 sc->sc_wdcdev.UDMA_cap = 4; 237 } 238 break; 239 case PCI_PRODUCT_VIATECH_VT8231: 240 aprint_normal("VT8231 ATA100 controller\n"); 241 sc->sc_wdcdev.UDMA_cap = 5; 242 break; 243 case PCI_PRODUCT_VIATECH_VT8233: 244 aprint_normal("VT8233 ATA100 controller\n"); 245 sc->sc_wdcdev.UDMA_cap = 5; 246 break; 247 case PCI_PRODUCT_VIATECH_VT8233A: 248 aprint_normal("VT8233A ATA133 controller\n"); 249 sc->sc_wdcdev.UDMA_cap = 6; 250 break; 251 case PCI_PRODUCT_VIATECH_VT8235: 252 aprint_normal("VT8235 ATA133 controller\n"); 253 sc->sc_wdcdev.UDMA_cap = 6; 254 break; 255 case PCI_PRODUCT_VIATECH_VT8237: 256 aprint_normal("VT8237 ATA133 controller\n"); 257 sc->sc_wdcdev.UDMA_cap = 6; 258 break; 259 default: 260 unknown: 261 aprint_normal("unknown VIA ATA controller\n"); 262 sc->sc_wdcdev.UDMA_cap = 0; 263 } 264 sc->sc_apo_regbase = APO_VIA_REGBASE; 265 break; 266 case PCI_VENDOR_AMD: 267 switch (sc->sc_pp->ide_product) { 268 case PCI_PRODUCT_AMD_PBC766_IDE: 269 case PCI_PRODUCT_AMD_PBC768_IDE: 270 case PCI_PRODUCT_AMD_PBC8111_IDE: 271 sc->sc_wdcdev.UDMA_cap = 5; 272 break; 273 default: 274 sc->sc_wdcdev.UDMA_cap = 4; 275 } 276 sc->sc_apo_regbase = APO_AMD_REGBASE; 277 break; 278 case PCI_VENDOR_NVIDIA: 279 switch (sc->sc_pp->ide_product) { 280 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 281 sc->sc_wdcdev.UDMA_cap = 5; 282 break; 283 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 284 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 285 sc->sc_wdcdev.UDMA_cap = 6; 286 break; 287 } 288 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 289 break; 290 default: 291 panic("via_chip_map: unknown vendor"); 292 } 293 294 aprint_normal("%s: bus-master DMA support present", 295 sc->sc_wdcdev.sc_dev.dv_xname); 296 pciide_mapreg_dma(sc, pa); 297 aprint_normal("\n"); 298 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 299 WDC_CAPABILITY_MODE; 300 if (sc->sc_dma_ok) { 301 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 302 sc->sc_wdcdev.irqack = pciide_irqack; 303 if (sc->sc_wdcdev.UDMA_cap > 0) 304 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 305 } 306 sc->sc_wdcdev.PIO_cap = 4; 307 sc->sc_wdcdev.DMA_cap = 2; 308 sc->sc_wdcdev.set_modes = via_setup_channel; 309 sc->sc_wdcdev.channels = sc->wdc_chanarray; 310 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 311 312 WDCDEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 313 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 314 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 315 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 316 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 317 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 318 DEBUG_PROBE); 319 320 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 321 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 322 cp = &sc->pciide_channels[channel]; 323 if (pciide_chansetup(sc, channel, interface) == 0) 324 continue; 325 326 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 327 aprint_normal("%s: %s channel ignored (disabled)\n", 328 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 329 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 330 continue; 331 } 332 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 333 pciide_pci_intr); 334 } 335 } 336 337 static void 338 via_setup_channel(struct wdc_channel *chp) 339 { 340 u_int32_t udmatim_reg, datatim_reg; 341 u_int8_t idedma_ctl; 342 int mode, drive; 343 struct ata_drive_datas *drvp; 344 struct pciide_channel *cp = (struct pciide_channel*)chp; 345 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 346 struct wdc_softc *wdc = &sc->sc_wdcdev; 347 #ifndef PCIIDE_AMD756_ENABLEDMA 348 int rev = PCI_REVISION( 349 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 350 #endif 351 352 idedma_ctl = 0; 353 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 354 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 355 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 356 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 357 358 /* setup DMA if needed */ 359 pciide_channel_dma_setup(cp); 360 361 for (drive = 0; drive < 2; drive++) { 362 drvp = &chp->ch_drive[drive]; 363 /* If no drive, skip */ 364 if ((drvp->drive_flags & DRIVE) == 0) 365 continue; 366 /* add timing values, setup DMA if needed */ 367 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 368 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 369 mode = drvp->PIO_mode; 370 goto pio; 371 } 372 if ((wdc->cap & WDC_CAPABILITY_UDMA) && 373 (drvp->drive_flags & DRIVE_UDMA)) { 374 /* use Ultra/DMA */ 375 drvp->drive_flags &= ~DRIVE_DMA; 376 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 377 APO_UDMA_EN_MTH(chp->ch_channel, drive); 378 switch (PCI_VENDOR(sc->sc_pci_id)) { 379 case PCI_VENDOR_VIATECH: 380 if (sc->sc_wdcdev.UDMA_cap == 6) { 381 /* 8233a */ 382 udmatim_reg |= APO_UDMA_TIME( 383 chp->ch_channel, 384 drive, 385 via_udma133_tim[drvp->UDMA_mode]); 386 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 387 /* 686b */ 388 udmatim_reg |= APO_UDMA_TIME( 389 chp->ch_channel, 390 drive, 391 via_udma100_tim[drvp->UDMA_mode]); 392 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 393 /* 596b or 686a */ 394 udmatim_reg |= APO_UDMA_CLK66( 395 chp->ch_channel); 396 udmatim_reg |= APO_UDMA_TIME( 397 chp->ch_channel, 398 drive, 399 via_udma66_tim[drvp->UDMA_mode]); 400 } else { 401 /* 596a or 586b */ 402 udmatim_reg |= APO_UDMA_TIME( 403 chp->ch_channel, 404 drive, 405 via_udma33_tim[drvp->UDMA_mode]); 406 } 407 break; 408 case PCI_VENDOR_AMD: 409 case PCI_VENDOR_NVIDIA: 410 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 411 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 412 break; 413 } 414 /* can use PIO timings, MW DMA unused */ 415 mode = drvp->PIO_mode; 416 } else { 417 /* use Multiword DMA, but only if revision is OK */ 418 drvp->drive_flags &= ~DRIVE_UDMA; 419 #ifndef PCIIDE_AMD756_ENABLEDMA 420 /* 421 * The workaround doesn't seem to be necessary 422 * with all drives, so it can be disabled by 423 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 424 * triggered. 425 */ 426 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 427 sc->sc_pp->ide_product == 428 PCI_PRODUCT_AMD_PBC756_IDE && 429 AMD756_CHIPREV_DISABLEDMA(rev)) { 430 aprint_normal( 431 "%s:%d:%d: multi-word DMA disabled due " 432 "to chip revision\n", 433 sc->sc_wdcdev.sc_dev.dv_xname, 434 chp->ch_channel, drive); 435 mode = drvp->PIO_mode; 436 drvp->drive_flags &= ~DRIVE_DMA; 437 goto pio; 438 } 439 #endif 440 /* mode = min(pio, dma+2) */ 441 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 442 mode = drvp->PIO_mode; 443 else 444 mode = drvp->DMA_mode + 2; 445 } 446 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 447 448 pio: /* setup PIO mode */ 449 if (mode <= 2) { 450 drvp->DMA_mode = 0; 451 drvp->PIO_mode = 0; 452 mode = 0; 453 } else { 454 drvp->PIO_mode = mode; 455 drvp->DMA_mode = mode - 2; 456 } 457 datatim_reg |= 458 APO_DATATIM_PULSE(chp->ch_channel, drive, 459 apollo_pio_set[mode]) | 460 APO_DATATIM_RECOV(chp->ch_channel, drive, 461 apollo_pio_rec[mode]); 462 } 463 if (idedma_ctl != 0) { 464 /* Add software bits in status register */ 465 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 466 idedma_ctl); 467 } 468 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 469 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 470 WDCDEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 471 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 472 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 473 } 474 475 static void 476 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 477 { 478 struct pciide_channel *cp; 479 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 480 int channel; 481 bus_size_t cmdsize, ctlsize; 482 483 if (pciide_chipen(sc, pa) == 0) 484 return; 485 486 if (interface == 0) { 487 WDCDEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 488 DEBUG_PROBE); 489 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 490 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 491 } 492 493 aprint_normal("%s: bus-master DMA support present", 494 sc->sc_wdcdev.sc_dev.dv_xname); 495 pciide_mapreg_dma(sc, pa); 496 aprint_normal("\n"); 497 498 if (sc->sc_dma_ok) { 499 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA | 500 WDC_CAPABILITY_IRQACK; 501 sc->sc_wdcdev.irqack = pciide_irqack; 502 } 503 sc->sc_wdcdev.PIO_cap = 4; 504 sc->sc_wdcdev.DMA_cap = 2; 505 sc->sc_wdcdev.UDMA_cap = 6; 506 507 sc->sc_wdcdev.channels = sc->wdc_chanarray; 508 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 509 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 510 WDC_CAPABILITY_MODE; 511 sc->sc_wdcdev.set_modes = sata_setup_channel; 512 513 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 514 cp = &sc->pciide_channels[channel]; 515 if (pciide_chansetup(sc, channel, interface) == 0) 516 continue; 517 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 518 pciide_pci_intr); 519 } 520 } 521
Indexes created Sat Oct 18 23:09:54 GMT 2025