viaide.c revision 1.11.4.2
1 /* $NetBSD: viaide.c,v 1.11.4.2 2005/05/05 21:40:30 riz Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_apollo_reg.h> 41 42 static int via_pcib_match(struct pci_attach_args *); 43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 44 static void via_sata_chip_map(struct pciide_softc *, 45 struct pci_attach_args *); 46 static void via_setup_channel(struct wdc_channel *); 47 48 static int viaide_match(struct device *, struct cfdata *, void *); 49 static void viaide_attach(struct device *, struct device *, void *); 50 static const struct pciide_product_desc * 51 viaide_lookup(pcireg_t); 52 53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 54 viaide_match, viaide_attach, NULL, NULL); 55 56 static const struct pciide_product_desc pciide_amd_products[] = { 57 { PCI_PRODUCT_AMD_PBC756_IDE, 58 0, 59 "Advanced Micro Devices AMD756 IDE Controller", 60 via_chip_map 61 }, 62 { PCI_PRODUCT_AMD_PBC766_IDE, 63 0, 64 "Advanced Micro Devices AMD766 IDE Controller", 65 via_chip_map 66 }, 67 { PCI_PRODUCT_AMD_PBC768_IDE, 68 0, 69 "Advanced Micro Devices AMD768 IDE Controller", 70 via_chip_map 71 }, 72 { PCI_PRODUCT_AMD_PBC8111_IDE, 73 0, 74 "Advanced Micro Devices AMD8111 IDE Controller", 75 via_chip_map 76 }, 77 { 0, 78 0, 79 NULL, 80 NULL 81 } 82 }; 83 84 static const struct pciide_product_desc pciide_nvidia_products[] = { 85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 86 0, 87 "NVIDIA nForce IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 91 0, 92 "NVIDIA nForce2 IDE Controller", 93 via_chip_map 94 }, 95 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 96 0, 97 "NVIDIA nForce3 IDE Controller", 98 via_chip_map 99 }, 100 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 101 0, 102 "NVIDIA nForce3 250 IDE Controller", 103 via_chip_map 104 }, 105 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 106 0, 107 "NVIDIA nForce3 250 Serial ATA Controller", 108 via_sata_chip_map 109 }, 110 { 0, 111 0, 112 NULL, 113 NULL 114 } 115 }; 116 117 static const struct pciide_product_desc pciide_via_products[] = { 118 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 119 0, 120 NULL, 121 via_chip_map, 122 }, 123 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 124 0, 125 NULL, 126 via_chip_map, 127 }, 128 { PCI_PRODUCT_VIATECH_VT6421_RAID, 129 0, 130 "VIA Technologies VT6421 Serial RAID Controller", 131 via_sata_chip_map, 132 }, 133 { PCI_PRODUCT_VIATECH_VT8237_SATA, 134 0, 135 "VIA Technologies VT8237 SATA Controller", 136 via_sata_chip_map, 137 }, 138 { 0, 139 0, 140 NULL, 141 NULL 142 } 143 }; 144 145 static const struct pciide_product_desc * 146 viaide_lookup(pcireg_t id) 147 { 148 149 switch (PCI_VENDOR(id)) { 150 case PCI_VENDOR_VIATECH: 151 return (pciide_lookup_product(id, pciide_via_products)); 152 153 case PCI_VENDOR_AMD: 154 return (pciide_lookup_product(id, pciide_amd_products)); 155 156 case PCI_VENDOR_NVIDIA: 157 return (pciide_lookup_product(id, pciide_nvidia_products)); 158 } 159 return (NULL); 160 } 161 162 static int 163 viaide_match(struct device *parent, struct cfdata *match, void *aux) 164 { 165 struct pci_attach_args *pa = aux; 166 167 if (viaide_lookup(pa->pa_id) != NULL) 168 return (2); 169 return (0); 170 } 171 172 static void 173 viaide_attach(struct device *parent, struct device *self, void *aux) 174 { 175 struct pci_attach_args *pa = aux; 176 struct pciide_softc *sc = (struct pciide_softc *)self; 177 const struct pciide_product_desc *pp; 178 179 pp = viaide_lookup(pa->pa_id); 180 if (pp == NULL) 181 panic("viaide_attach"); 182 pciide_common_attach(sc, pa, pp); 183 } 184 185 static int 186 via_pcib_match(struct pci_attach_args *pa) 187 { 188 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 189 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 190 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 191 return (1); 192 return 0; 193 } 194 195 static void 196 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 197 { 198 struct pciide_channel *cp; 199 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 200 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 201 int channel; 202 u_int32_t ideconf; 203 bus_size_t cmdsize, ctlsize; 204 pcireg_t pcib_id, pcib_class; 205 struct pci_attach_args pcib_pa; 206 207 if (pciide_chipen(sc, pa) == 0) 208 return; 209 210 switch (vendor) { 211 case PCI_VENDOR_VIATECH: 212 /* 213 * get a PCI tag for the ISA bridge. 214 */ 215 if (pci_enumerate_bus( 216 (struct pci_softc *)sc->sc_wdcdev.sc_dev.dv_parent, 217 via_pcib_match, &pcib_pa) == 0) 218 goto unknown; 219 pcib_id = pcib_pa.pa_id; 220 pcib_class = pcib_pa.pa_class; 221 aprint_normal("%s: VIA Technologies ", 222 sc->sc_wdcdev.sc_dev.dv_xname); 223 switch (PCI_PRODUCT(pcib_id)) { 224 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 225 aprint_normal("VT82C586 (Apollo VP) "); 226 if(PCI_REVISION(pcib_class) >= 0x02) { 227 aprint_normal("ATA33 controller\n"); 228 sc->sc_wdcdev.UDMA_cap = 2; 229 } else { 230 aprint_normal("controller\n"); 231 sc->sc_wdcdev.UDMA_cap = 0; 232 } 233 break; 234 case PCI_PRODUCT_VIATECH_VT82C596A: 235 aprint_normal("VT82C596A (Apollo Pro) "); 236 if (PCI_REVISION(pcib_class) >= 0x12) { 237 aprint_normal("ATA66 controller\n"); 238 sc->sc_wdcdev.UDMA_cap = 4; 239 } else { 240 aprint_normal("ATA33 controller\n"); 241 sc->sc_wdcdev.UDMA_cap = 2; 242 } 243 break; 244 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 245 aprint_normal("VT82C686A (Apollo KX133) "); 246 if (PCI_REVISION(pcib_class) >= 0x40) { 247 aprint_normal("ATA100 controller\n"); 248 sc->sc_wdcdev.UDMA_cap = 5; 249 } else { 250 aprint_normal("ATA66 controller\n"); 251 sc->sc_wdcdev.UDMA_cap = 4; 252 } 253 break; 254 case PCI_PRODUCT_VIATECH_VT8231: 255 aprint_normal("VT8231 ATA100 controller\n"); 256 sc->sc_wdcdev.UDMA_cap = 5; 257 break; 258 case PCI_PRODUCT_VIATECH_VT8233: 259 aprint_normal("VT8233 ATA100 controller\n"); 260 sc->sc_wdcdev.UDMA_cap = 5; 261 break; 262 case PCI_PRODUCT_VIATECH_VT8233A: 263 aprint_normal("VT8233A ATA133 controller\n"); 264 sc->sc_wdcdev.UDMA_cap = 6; 265 break; 266 case PCI_PRODUCT_VIATECH_VT8235: 267 aprint_normal("VT8235 ATA133 controller\n"); 268 sc->sc_wdcdev.UDMA_cap = 6; 269 break; 270 case PCI_PRODUCT_VIATECH_VT8237: 271 aprint_normal("VT8237 ATA133 controller\n"); 272 sc->sc_wdcdev.UDMA_cap = 6; 273 break; 274 default: 275 unknown: 276 aprint_normal("unknown VIA ATA controller\n"); 277 sc->sc_wdcdev.UDMA_cap = 0; 278 } 279 sc->sc_apo_regbase = APO_VIA_REGBASE; 280 break; 281 case PCI_VENDOR_AMD: 282 switch (sc->sc_pp->ide_product) { 283 case PCI_PRODUCT_AMD_PBC8111_IDE: 284 sc->sc_wdcdev.UDMA_cap = 6; 285 break; 286 case PCI_PRODUCT_AMD_PBC766_IDE: 287 case PCI_PRODUCT_AMD_PBC768_IDE: 288 sc->sc_wdcdev.UDMA_cap = 5; 289 break; 290 default: 291 sc->sc_wdcdev.UDMA_cap = 4; 292 } 293 sc->sc_apo_regbase = APO_AMD_REGBASE; 294 break; 295 case PCI_VENDOR_NVIDIA: 296 switch (sc->sc_pp->ide_product) { 297 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 298 sc->sc_wdcdev.UDMA_cap = 5; 299 break; 300 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 301 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 302 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 303 sc->sc_wdcdev.UDMA_cap = 6; 304 break; 305 } 306 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 307 break; 308 default: 309 panic("via_chip_map: unknown vendor"); 310 } 311 312 aprint_normal("%s: bus-master DMA support present", 313 sc->sc_wdcdev.sc_dev.dv_xname); 314 pciide_mapreg_dma(sc, pa); 315 aprint_normal("\n"); 316 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 317 WDC_CAPABILITY_MODE; 318 if (sc->sc_dma_ok) { 319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 320 sc->sc_wdcdev.irqack = pciide_irqack; 321 if (sc->sc_wdcdev.UDMA_cap > 0) 322 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 323 } 324 sc->sc_wdcdev.PIO_cap = 4; 325 sc->sc_wdcdev.DMA_cap = 2; 326 sc->sc_wdcdev.set_modes = via_setup_channel; 327 sc->sc_wdcdev.channels = sc->wdc_chanarray; 328 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 329 330 WDCDEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 331 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 332 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 333 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 334 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 335 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 336 DEBUG_PROBE); 337 338 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 339 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 340 cp = &sc->pciide_channels[channel]; 341 if (pciide_chansetup(sc, channel, interface) == 0) 342 continue; 343 344 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 345 aprint_normal("%s: %s channel ignored (disabled)\n", 346 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 347 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 348 continue; 349 } 350 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 351 pciide_pci_intr); 352 } 353 } 354 355 static void 356 via_setup_channel(struct wdc_channel *chp) 357 { 358 u_int32_t udmatim_reg, datatim_reg; 359 u_int8_t idedma_ctl; 360 int mode, drive; 361 struct ata_drive_datas *drvp; 362 struct pciide_channel *cp = (struct pciide_channel*)chp; 363 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 364 struct wdc_softc *wdc = &sc->sc_wdcdev; 365 #ifndef PCIIDE_AMD756_ENABLEDMA 366 int rev = PCI_REVISION( 367 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 368 #endif 369 370 idedma_ctl = 0; 371 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 372 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 373 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 374 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 375 376 /* setup DMA if needed */ 377 pciide_channel_dma_setup(cp); 378 379 for (drive = 0; drive < 2; drive++) { 380 drvp = &chp->ch_drive[drive]; 381 /* If no drive, skip */ 382 if ((drvp->drive_flags & DRIVE) == 0) 383 continue; 384 /* add timing values, setup DMA if needed */ 385 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 386 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 387 mode = drvp->PIO_mode; 388 goto pio; 389 } 390 if ((wdc->cap & WDC_CAPABILITY_UDMA) && 391 (drvp->drive_flags & DRIVE_UDMA)) { 392 /* use Ultra/DMA */ 393 drvp->drive_flags &= ~DRIVE_DMA; 394 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 395 APO_UDMA_EN_MTH(chp->ch_channel, drive); 396 switch (PCI_VENDOR(sc->sc_pci_id)) { 397 case PCI_VENDOR_VIATECH: 398 if (sc->sc_wdcdev.UDMA_cap == 6) { 399 /* 8233a */ 400 udmatim_reg |= APO_UDMA_TIME( 401 chp->ch_channel, 402 drive, 403 via_udma133_tim[drvp->UDMA_mode]); 404 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 405 /* 686b */ 406 udmatim_reg |= APO_UDMA_TIME( 407 chp->ch_channel, 408 drive, 409 via_udma100_tim[drvp->UDMA_mode]); 410 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 411 /* 596b or 686a */ 412 udmatim_reg |= APO_UDMA_CLK66( 413 chp->ch_channel); 414 udmatim_reg |= APO_UDMA_TIME( 415 chp->ch_channel, 416 drive, 417 via_udma66_tim[drvp->UDMA_mode]); 418 } else { 419 /* 596a or 586b */ 420 udmatim_reg |= APO_UDMA_TIME( 421 chp->ch_channel, 422 drive, 423 via_udma33_tim[drvp->UDMA_mode]); 424 } 425 break; 426 case PCI_VENDOR_AMD: 427 case PCI_VENDOR_NVIDIA: 428 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 429 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 430 break; 431 } 432 /* can use PIO timings, MW DMA unused */ 433 mode = drvp->PIO_mode; 434 } else { 435 /* use Multiword DMA, but only if revision is OK */ 436 drvp->drive_flags &= ~DRIVE_UDMA; 437 #ifndef PCIIDE_AMD756_ENABLEDMA 438 /* 439 * The workaround doesn't seem to be necessary 440 * with all drives, so it can be disabled by 441 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 442 * triggered. 443 */ 444 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 445 sc->sc_pp->ide_product == 446 PCI_PRODUCT_AMD_PBC756_IDE && 447 AMD756_CHIPREV_DISABLEDMA(rev)) { 448 aprint_normal( 449 "%s:%d:%d: multi-word DMA disabled due " 450 "to chip revision\n", 451 sc->sc_wdcdev.sc_dev.dv_xname, 452 chp->ch_channel, drive); 453 mode = drvp->PIO_mode; 454 drvp->drive_flags &= ~DRIVE_DMA; 455 goto pio; 456 } 457 #endif 458 /* mode = min(pio, dma+2) */ 459 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 460 mode = drvp->PIO_mode; 461 else 462 mode = drvp->DMA_mode + 2; 463 } 464 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 465 466 pio: /* setup PIO mode */ 467 if (mode <= 2) { 468 drvp->DMA_mode = 0; 469 drvp->PIO_mode = 0; 470 mode = 0; 471 } else { 472 drvp->PIO_mode = mode; 473 drvp->DMA_mode = mode - 2; 474 } 475 datatim_reg |= 476 APO_DATATIM_PULSE(chp->ch_channel, drive, 477 apollo_pio_set[mode]) | 478 APO_DATATIM_RECOV(chp->ch_channel, drive, 479 apollo_pio_rec[mode]); 480 } 481 if (idedma_ctl != 0) { 482 /* Add software bits in status register */ 483 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 484 idedma_ctl); 485 } 486 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 487 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 488 WDCDEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 489 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 490 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 491 } 492 493 static void 494 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 495 { 496 struct pciide_channel *cp; 497 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 498 int channel; 499 bus_size_t cmdsize, ctlsize; 500 501 if (pciide_chipen(sc, pa) == 0) 502 return; 503 504 if (interface == 0) { 505 WDCDEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 506 DEBUG_PROBE); 507 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 508 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 509 } 510 511 aprint_normal("%s: bus-master DMA support present", 512 sc->sc_wdcdev.sc_dev.dv_xname); 513 pciide_mapreg_dma(sc, pa); 514 aprint_normal("\n"); 515 516 if (sc->sc_dma_ok) { 517 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA | 518 WDC_CAPABILITY_IRQACK; 519 sc->sc_wdcdev.irqack = pciide_irqack; 520 } 521 sc->sc_wdcdev.PIO_cap = 4; 522 sc->sc_wdcdev.DMA_cap = 2; 523 sc->sc_wdcdev.UDMA_cap = 6; 524 525 sc->sc_wdcdev.channels = sc->wdc_chanarray; 526 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 527 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 528 WDC_CAPABILITY_MODE; 529 sc->sc_wdcdev.set_modes = sata_setup_channel; 530 531 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 532 cp = &sc->pciide_channels[channel]; 533 if (pciide_chansetup(sc, channel, interface) == 0) 534 continue; 535 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 536 pciide_pci_intr); 537 } 538 } 539
Indexes created Wed Oct 22 06:10:02 GMT 2025