viaide.c revision 1.12.2.6 1 /* $NetBSD: viaide.c,v 1.12.2.6 2004/11/14 08:15:45 skrll Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35
36 #include <dev/pci/pcivar.h>
37 #include <dev/pci/pcidevs.h>
38 #include <dev/pci/pciidereg.h>
39 #include <dev/pci/pciidevar.h>
40 #include <dev/pci/pciide_apollo_reg.h>
41
42 static int via_pcib_match(struct pci_attach_args *);
43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
44 static void via_sata_chip_map(struct pciide_softc *,
45 struct pci_attach_args *);
46 static void via_setup_channel(struct ata_channel *);
47
48 static int viaide_match(struct device *, struct cfdata *, void *);
49 static void viaide_attach(struct device *, struct device *, void *);
50 static const struct pciide_product_desc *
51 viaide_lookup(pcireg_t);
52
53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
54 viaide_match, viaide_attach, NULL, NULL);
55
56 static const struct pciide_product_desc pciide_amd_products[] = {
57 { PCI_PRODUCT_AMD_PBC756_IDE,
58 0,
59 "Advanced Micro Devices AMD756 IDE Controller",
60 via_chip_map
61 },
62 { PCI_PRODUCT_AMD_PBC766_IDE,
63 0,
64 "Advanced Micro Devices AMD766 IDE Controller",
65 via_chip_map
66 },
67 { PCI_PRODUCT_AMD_PBC768_IDE,
68 0,
69 "Advanced Micro Devices AMD768 IDE Controller",
70 via_chip_map
71 },
72 { PCI_PRODUCT_AMD_PBC8111_IDE,
73 0,
74 "Advanced Micro Devices AMD8111 IDE Controller",
75 via_chip_map
76 },
77 { 0,
78 0,
79 NULL,
80 NULL
81 }
82 };
83
84 static const struct pciide_product_desc pciide_nvidia_products[] = {
85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
86 0,
87 "NVIDIA nForce IDE Controller",
88 via_chip_map
89 },
90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
91 0,
92 "NVIDIA nForce2 IDE Controller",
93 via_chip_map
94 },
95 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
96 0,
97 "NVIDIA nForce3 IDE Controller",
98 via_chip_map
99 },
100 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
101 0,
102 "NVIDIA nForce3 250 IDE Controller",
103 via_chip_map
104 },
105 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
106 0,
107 "NVIDIA nForce3 250 Serial ATA Controller",
108 via_sata_chip_map
109 },
110 { 0,
111 0,
112 NULL,
113 NULL
114 }
115 };
116
117 static const struct pciide_product_desc pciide_via_products[] = {
118 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
119 0,
120 NULL,
121 via_chip_map,
122 },
123 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
124 0,
125 NULL,
126 via_chip_map,
127 },
128 { PCI_PRODUCT_VIATECH_VT8237_SATA,
129 0,
130 "VIA Technologies VT8237 SATA Controller",
131 via_sata_chip_map,
132 },
133 { 0,
134 0,
135 NULL,
136 NULL
137 }
138 };
139
140 static const struct pciide_product_desc *
141 viaide_lookup(pcireg_t id)
142 {
143
144 switch (PCI_VENDOR(id)) {
145 case PCI_VENDOR_VIATECH:
146 return (pciide_lookup_product(id, pciide_via_products));
147
148 case PCI_VENDOR_AMD:
149 return (pciide_lookup_product(id, pciide_amd_products));
150
151 case PCI_VENDOR_NVIDIA:
152 return (pciide_lookup_product(id, pciide_nvidia_products));
153 }
154 return (NULL);
155 }
156
157 static int
158 viaide_match(struct device *parent, struct cfdata *match, void *aux)
159 {
160 struct pci_attach_args *pa = aux;
161
162 if (viaide_lookup(pa->pa_id) != NULL)
163 return (2);
164 return (0);
165 }
166
167 static void
168 viaide_attach(struct device *parent, struct device *self, void *aux)
169 {
170 struct pci_attach_args *pa = aux;
171 struct pciide_softc *sc = (struct pciide_softc *)self;
172 const struct pciide_product_desc *pp;
173
174 pp = viaide_lookup(pa->pa_id);
175 if (pp == NULL)
176 panic("viaide_attach");
177 pciide_common_attach(sc, pa, pp);
178 }
179
180 static int
181 via_pcib_match(struct pci_attach_args *pa)
182 {
183 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
184 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
185 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
186 return (1);
187 return 0;
188 }
189
190 static void
191 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
192 {
193 struct pciide_channel *cp;
194 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
195 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
196 int channel;
197 u_int32_t ideconf;
198 bus_size_t cmdsize, ctlsize;
199 pcireg_t pcib_id, pcib_class;
200 struct pci_attach_args pcib_pa;
201
202 if (pciide_chipen(sc, pa) == 0)
203 return;
204
205 switch (vendor) {
206 case PCI_VENDOR_VIATECH:
207 /*
208 * get a PCI tag for the ISA bridge.
209 */
210 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
211 goto unknown;
212 pcib_id = pcib_pa.pa_id;
213 pcib_class = pcib_pa.pa_class;
214 aprint_normal("%s: VIA Technologies ",
215 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
216 switch (PCI_PRODUCT(pcib_id)) {
217 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
218 aprint_normal("VT82C586 (Apollo VP) ");
219 if(PCI_REVISION(pcib_class) >= 0x02) {
220 aprint_normal("ATA33 controller\n");
221 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
222 } else {
223 aprint_normal("controller\n");
224 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
225 }
226 break;
227 case PCI_PRODUCT_VIATECH_VT82C596A:
228 aprint_normal("VT82C596A (Apollo Pro) ");
229 if (PCI_REVISION(pcib_class) >= 0x12) {
230 aprint_normal("ATA66 controller\n");
231 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
232 } else {
233 aprint_normal("ATA33 controller\n");
234 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
235 }
236 break;
237 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
238 aprint_normal("VT82C686A (Apollo KX133) ");
239 if (PCI_REVISION(pcib_class) >= 0x40) {
240 aprint_normal("ATA100 controller\n");
241 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
242 } else {
243 aprint_normal("ATA66 controller\n");
244 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
245 }
246 break;
247 case PCI_PRODUCT_VIATECH_VT8231:
248 aprint_normal("VT8231 ATA100 controller\n");
249 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
250 break;
251 case PCI_PRODUCT_VIATECH_VT8233:
252 aprint_normal("VT8233 ATA100 controller\n");
253 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
254 break;
255 case PCI_PRODUCT_VIATECH_VT8233A:
256 aprint_normal("VT8233A ATA133 controller\n");
257 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
258 break;
259 case PCI_PRODUCT_VIATECH_VT8235:
260 aprint_normal("VT8235 ATA133 controller\n");
261 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
262 break;
263 case PCI_PRODUCT_VIATECH_VT8237:
264 aprint_normal("VT8237 ATA133 controller\n");
265 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
266 break;
267 default:
268 unknown:
269 aprint_normal("unknown VIA ATA controller\n");
270 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
271 }
272 sc->sc_apo_regbase = APO_VIA_REGBASE;
273 break;
274 case PCI_VENDOR_AMD:
275 switch (sc->sc_pp->ide_product) {
276 case PCI_PRODUCT_AMD_PBC8111_IDE:
277 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
278 break;
279 case PCI_PRODUCT_AMD_PBC766_IDE:
280 case PCI_PRODUCT_AMD_PBC768_IDE:
281 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
282 break;
283 default:
284 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
285 }
286 sc->sc_apo_regbase = APO_AMD_REGBASE;
287 break;
288 case PCI_VENDOR_NVIDIA:
289 switch (sc->sc_pp->ide_product) {
290 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
291 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
292 break;
293 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
294 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
295 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
297 break;
298 }
299 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
300 break;
301 default:
302 panic("via_chip_map: unknown vendor");
303 }
304
305 aprint_normal("%s: bus-master DMA support present",
306 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
307 pciide_mapreg_dma(sc, pa);
308 aprint_normal("\n");
309 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
310 if (sc->sc_dma_ok) {
311 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
312 sc->sc_wdcdev.irqack = pciide_irqack;
313 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
314 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
315 }
316 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
317 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
318 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
319 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
320 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
321
322 wdc_allocate_regs(&sc->sc_wdcdev);
323
324 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
325 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
326 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
327 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
328 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
329 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
330 DEBUG_PROBE);
331
332 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
333 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
334 channel++) {
335 cp = &sc->pciide_channels[channel];
336 if (pciide_chansetup(sc, channel, interface) == 0)
337 continue;
338
339 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
340 aprint_normal("%s: %s channel ignored (disabled)\n",
341 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
342 cp->ata_channel.ch_flags |= ATACH_DISABLED;
343 continue;
344 }
345 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
346 pciide_pci_intr);
347 }
348 }
349
350 static void
351 via_setup_channel(struct ata_channel *chp)
352 {
353 u_int32_t udmatim_reg, datatim_reg;
354 u_int8_t idedma_ctl;
355 int mode, drive, s;
356 struct ata_drive_datas *drvp;
357 struct atac_softc *atac = chp->ch_atac;
358 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
359 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
360 #ifndef PCIIDE_AMD756_ENABLEDMA
361 int rev = PCI_REVISION(
362 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
363 #endif
364
365 idedma_ctl = 0;
366 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
367 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
368 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
369 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
370
371 /* setup DMA if needed */
372 pciide_channel_dma_setup(cp);
373
374 for (drive = 0; drive < 2; drive++) {
375 drvp = &chp->ch_drive[drive];
376 /* If no drive, skip */
377 if ((drvp->drive_flags & DRIVE) == 0)
378 continue;
379 /* add timing values, setup DMA if needed */
380 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
381 (drvp->drive_flags & DRIVE_UDMA) == 0)) {
382 mode = drvp->PIO_mode;
383 goto pio;
384 }
385 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
386 (drvp->drive_flags & DRIVE_UDMA)) {
387 /* use Ultra/DMA */
388 s = splbio();
389 drvp->drive_flags &= ~DRIVE_DMA;
390 splx(s);
391 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
392 APO_UDMA_EN_MTH(chp->ch_channel, drive);
393 switch (PCI_VENDOR(sc->sc_pci_id)) {
394 case PCI_VENDOR_VIATECH:
395 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
396 /* 8233a */
397 udmatim_reg |= APO_UDMA_TIME(
398 chp->ch_channel,
399 drive,
400 via_udma133_tim[drvp->UDMA_mode]);
401 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
402 /* 686b */
403 udmatim_reg |= APO_UDMA_TIME(
404 chp->ch_channel,
405 drive,
406 via_udma100_tim[drvp->UDMA_mode]);
407 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
408 /* 596b or 686a */
409 udmatim_reg |= APO_UDMA_CLK66(
410 chp->ch_channel);
411 udmatim_reg |= APO_UDMA_TIME(
412 chp->ch_channel,
413 drive,
414 via_udma66_tim[drvp->UDMA_mode]);
415 } else {
416 /* 596a or 586b */
417 udmatim_reg |= APO_UDMA_TIME(
418 chp->ch_channel,
419 drive,
420 via_udma33_tim[drvp->UDMA_mode]);
421 }
422 break;
423 case PCI_VENDOR_AMD:
424 case PCI_VENDOR_NVIDIA:
425 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
426 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
427 break;
428 }
429 /* can use PIO timings, MW DMA unused */
430 mode = drvp->PIO_mode;
431 } else {
432 /* use Multiword DMA, but only if revision is OK */
433 s = splbio();
434 drvp->drive_flags &= ~DRIVE_UDMA;
435 splx(s);
436 #ifndef PCIIDE_AMD756_ENABLEDMA
437 /*
438 * The workaround doesn't seem to be necessary
439 * with all drives, so it can be disabled by
440 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
441 * triggered.
442 */
443 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
444 sc->sc_pp->ide_product ==
445 PCI_PRODUCT_AMD_PBC756_IDE &&
446 AMD756_CHIPREV_DISABLEDMA(rev)) {
447 aprint_normal(
448 "%s:%d:%d: multi-word DMA disabled due "
449 "to chip revision\n",
450 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
451 chp->ch_channel, drive);
452 mode = drvp->PIO_mode;
453 s = splbio();
454 drvp->drive_flags &= ~DRIVE_DMA;
455 splx(s);
456 goto pio;
457 }
458 #endif
459 /* mode = min(pio, dma+2) */
460 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
461 mode = drvp->PIO_mode;
462 else
463 mode = drvp->DMA_mode + 2;
464 }
465 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
466
467 pio: /* setup PIO mode */
468 if (mode <= 2) {
469 drvp->DMA_mode = 0;
470 drvp->PIO_mode = 0;
471 mode = 0;
472 } else {
473 drvp->PIO_mode = mode;
474 drvp->DMA_mode = mode - 2;
475 }
476 datatim_reg |=
477 APO_DATATIM_PULSE(chp->ch_channel, drive,
478 apollo_pio_set[mode]) |
479 APO_DATATIM_RECOV(chp->ch_channel, drive,
480 apollo_pio_rec[mode]);
481 }
482 if (idedma_ctl != 0) {
483 /* Add software bits in status register */
484 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
485 idedma_ctl);
486 }
487 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
488 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
489 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
490 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
491 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
492 }
493
494 static void
495 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
496 {
497 struct pciide_channel *cp;
498 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
499 int channel;
500 bus_size_t cmdsize, ctlsize;
501
502 if (pciide_chipen(sc, pa) == 0)
503 return;
504
505 if (interface == 0) {
506 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
507 DEBUG_PROBE);
508 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
509 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
510 }
511
512 aprint_normal("%s: bus-master DMA support present",
513 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
514 pciide_mapreg_dma(sc, pa);
515 aprint_normal("\n");
516
517 if (sc->sc_dma_ok) {
518 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
519 sc->sc_wdcdev.irqack = pciide_irqack;
520 }
521 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
522 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
523 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
524
525 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
526 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
527 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
528 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
529
530 wdc_allocate_regs(&sc->sc_wdcdev);
531
532 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
533 channel++) {
534 cp = &sc->pciide_channels[channel];
535 if (pciide_chansetup(sc, channel, interface) == 0)
536 continue;
537 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
538 pciide_pci_intr);
539 }
540 }
541