viaide.c revision 1.12.2.7 1 /* $NetBSD: viaide.c,v 1.12.2.7 2005/01/17 19:31:26 skrll Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35
36 #include <dev/pci/pcivar.h>
37 #include <dev/pci/pcidevs.h>
38 #include <dev/pci/pciidereg.h>
39 #include <dev/pci/pciidevar.h>
40 #include <dev/pci/pciide_apollo_reg.h>
41
42 static int via_pcib_match(struct pci_attach_args *);
43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
44 static void via_sata_chip_map(struct pciide_softc *,
45 struct pci_attach_args *);
46 static void via_setup_channel(struct ata_channel *);
47
48 static int viaide_match(struct device *, struct cfdata *, void *);
49 static void viaide_attach(struct device *, struct device *, void *);
50 static const struct pciide_product_desc *
51 viaide_lookup(pcireg_t);
52
53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
54 viaide_match, viaide_attach, NULL, NULL);
55
56 static const struct pciide_product_desc pciide_amd_products[] = {
57 { PCI_PRODUCT_AMD_PBC756_IDE,
58 0,
59 "Advanced Micro Devices AMD756 IDE Controller",
60 via_chip_map
61 },
62 { PCI_PRODUCT_AMD_PBC766_IDE,
63 0,
64 "Advanced Micro Devices AMD766 IDE Controller",
65 via_chip_map
66 },
67 { PCI_PRODUCT_AMD_PBC768_IDE,
68 0,
69 "Advanced Micro Devices AMD768 IDE Controller",
70 via_chip_map
71 },
72 { PCI_PRODUCT_AMD_PBC8111_IDE,
73 0,
74 "Advanced Micro Devices AMD8111 IDE Controller",
75 via_chip_map
76 },
77 { 0,
78 0,
79 NULL,
80 NULL
81 }
82 };
83
84 static const struct pciide_product_desc pciide_nvidia_products[] = {
85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
86 0,
87 "NVIDIA nForce IDE Controller",
88 via_chip_map
89 },
90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
91 0,
92 "NVIDIA nForce2 IDE Controller",
93 via_chip_map
94 },
95 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
96 0,
97 "NVIDIA nForce2 Ultra 400 IDE Controller",
98 via_chip_map
99 },
100 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
101 0,
102 "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
103 via_sata_chip_map
104 },
105 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
106 0,
107 "NVIDIA nForce3 IDE Controller",
108 via_chip_map
109 },
110 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
111 0,
112 "NVIDIA nForce3 250 IDE Controller",
113 via_chip_map
114 },
115 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
116 0,
117 "NVIDIA nForce3 250 Serial ATA Controller",
118 via_sata_chip_map
119 },
120 { 0,
121 0,
122 NULL,
123 NULL
124 }
125 };
126
127 static const struct pciide_product_desc pciide_via_products[] = {
128 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
129 0,
130 NULL,
131 via_chip_map,
132 },
133 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
134 0,
135 NULL,
136 via_chip_map,
137 },
138 { PCI_PRODUCT_VIATECH_VT8237_SATA,
139 0,
140 "VIA Technologies VT8237 SATA Controller",
141 via_sata_chip_map,
142 },
143 { 0,
144 0,
145 NULL,
146 NULL
147 }
148 };
149
150 static const struct pciide_product_desc *
151 viaide_lookup(pcireg_t id)
152 {
153
154 switch (PCI_VENDOR(id)) {
155 case PCI_VENDOR_VIATECH:
156 return (pciide_lookup_product(id, pciide_via_products));
157
158 case PCI_VENDOR_AMD:
159 return (pciide_lookup_product(id, pciide_amd_products));
160
161 case PCI_VENDOR_NVIDIA:
162 return (pciide_lookup_product(id, pciide_nvidia_products));
163 }
164 return (NULL);
165 }
166
167 static int
168 viaide_match(struct device *parent, struct cfdata *match, void *aux)
169 {
170 struct pci_attach_args *pa = aux;
171
172 if (viaide_lookup(pa->pa_id) != NULL)
173 return (2);
174 return (0);
175 }
176
177 static void
178 viaide_attach(struct device *parent, struct device *self, void *aux)
179 {
180 struct pci_attach_args *pa = aux;
181 struct pciide_softc *sc = (struct pciide_softc *)self;
182 const struct pciide_product_desc *pp;
183
184 pp = viaide_lookup(pa->pa_id);
185 if (pp == NULL)
186 panic("viaide_attach");
187 pciide_common_attach(sc, pa, pp);
188 }
189
190 static int
191 via_pcib_match(struct pci_attach_args *pa)
192 {
193 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
194 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
195 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
196 return (1);
197 return 0;
198 }
199
200 static void
201 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
202 {
203 struct pciide_channel *cp;
204 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
205 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
206 int channel;
207 u_int32_t ideconf;
208 bus_size_t cmdsize, ctlsize;
209 pcireg_t pcib_id, pcib_class;
210 struct pci_attach_args pcib_pa;
211
212 if (pciide_chipen(sc, pa) == 0)
213 return;
214
215 switch (vendor) {
216 case PCI_VENDOR_VIATECH:
217 /*
218 * get a PCI tag for the ISA bridge.
219 */
220 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
221 goto unknown;
222 pcib_id = pcib_pa.pa_id;
223 pcib_class = pcib_pa.pa_class;
224 aprint_normal("%s: VIA Technologies ",
225 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
226 switch (PCI_PRODUCT(pcib_id)) {
227 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
228 aprint_normal("VT82C586 (Apollo VP) ");
229 if(PCI_REVISION(pcib_class) >= 0x02) {
230 aprint_normal("ATA33 controller\n");
231 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
232 } else {
233 aprint_normal("controller\n");
234 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
235 }
236 break;
237 case PCI_PRODUCT_VIATECH_VT82C596A:
238 aprint_normal("VT82C596A (Apollo Pro) ");
239 if (PCI_REVISION(pcib_class) >= 0x12) {
240 aprint_normal("ATA66 controller\n");
241 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
242 } else {
243 aprint_normal("ATA33 controller\n");
244 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
245 }
246 break;
247 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
248 aprint_normal("VT82C686A (Apollo KX133) ");
249 if (PCI_REVISION(pcib_class) >= 0x40) {
250 aprint_normal("ATA100 controller\n");
251 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
252 } else {
253 aprint_normal("ATA66 controller\n");
254 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
255 }
256 break;
257 case PCI_PRODUCT_VIATECH_VT8231:
258 aprint_normal("VT8231 ATA100 controller\n");
259 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
260 break;
261 case PCI_PRODUCT_VIATECH_VT8233:
262 aprint_normal("VT8233 ATA100 controller\n");
263 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
264 break;
265 case PCI_PRODUCT_VIATECH_VT8233A:
266 aprint_normal("VT8233A ATA133 controller\n");
267 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
268 break;
269 case PCI_PRODUCT_VIATECH_VT8235:
270 aprint_normal("VT8235 ATA133 controller\n");
271 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
272 break;
273 case PCI_PRODUCT_VIATECH_VT8237:
274 aprint_normal("VT8237 ATA133 controller\n");
275 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
276 break;
277 default:
278 unknown:
279 aprint_normal("unknown VIA ATA controller\n");
280 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
281 }
282 sc->sc_apo_regbase = APO_VIA_REGBASE;
283 break;
284 case PCI_VENDOR_AMD:
285 switch (sc->sc_pp->ide_product) {
286 case PCI_PRODUCT_AMD_PBC8111_IDE:
287 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
288 break;
289 case PCI_PRODUCT_AMD_PBC766_IDE:
290 case PCI_PRODUCT_AMD_PBC768_IDE:
291 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
292 break;
293 default:
294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
295 }
296 sc->sc_apo_regbase = APO_AMD_REGBASE;
297 break;
298 case PCI_VENDOR_NVIDIA:
299 switch (sc->sc_pp->ide_product) {
300 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
301 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
302 break;
303 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
304 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
305 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
306 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
307 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
308 break;
309 }
310 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
311 break;
312 default:
313 panic("via_chip_map: unknown vendor");
314 }
315
316 aprint_normal("%s: bus-master DMA support present",
317 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
318 pciide_mapreg_dma(sc, pa);
319 aprint_normal("\n");
320 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
321 if (sc->sc_dma_ok) {
322 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
323 sc->sc_wdcdev.irqack = pciide_irqack;
324 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
325 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
326 }
327 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
328 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
329 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
330 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
331 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
332
333 wdc_allocate_regs(&sc->sc_wdcdev);
334
335 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
336 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
337 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
338 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
339 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
340 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
341 DEBUG_PROBE);
342
343 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
344 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
345 channel++) {
346 cp = &sc->pciide_channels[channel];
347 if (pciide_chansetup(sc, channel, interface) == 0)
348 continue;
349
350 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
351 aprint_normal("%s: %s channel ignored (disabled)\n",
352 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
353 cp->ata_channel.ch_flags |= ATACH_DISABLED;
354 continue;
355 }
356 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
357 pciide_pci_intr);
358 }
359 }
360
361 static void
362 via_setup_channel(struct ata_channel *chp)
363 {
364 u_int32_t udmatim_reg, datatim_reg;
365 u_int8_t idedma_ctl;
366 int mode, drive, s;
367 struct ata_drive_datas *drvp;
368 struct atac_softc *atac = chp->ch_atac;
369 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
370 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
371 #ifndef PCIIDE_AMD756_ENABLEDMA
372 int rev = PCI_REVISION(
373 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
374 #endif
375
376 idedma_ctl = 0;
377 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
378 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
379 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
380 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
381
382 /* setup DMA if needed */
383 pciide_channel_dma_setup(cp);
384
385 for (drive = 0; drive < 2; drive++) {
386 drvp = &chp->ch_drive[drive];
387 /* If no drive, skip */
388 if ((drvp->drive_flags & DRIVE) == 0)
389 continue;
390 /* add timing values, setup DMA if needed */
391 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
392 (drvp->drive_flags & DRIVE_UDMA) == 0)) {
393 mode = drvp->PIO_mode;
394 goto pio;
395 }
396 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
397 (drvp->drive_flags & DRIVE_UDMA)) {
398 /* use Ultra/DMA */
399 s = splbio();
400 drvp->drive_flags &= ~DRIVE_DMA;
401 splx(s);
402 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
403 APO_UDMA_EN_MTH(chp->ch_channel, drive);
404 switch (PCI_VENDOR(sc->sc_pci_id)) {
405 case PCI_VENDOR_VIATECH:
406 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
407 /* 8233a */
408 udmatim_reg |= APO_UDMA_TIME(
409 chp->ch_channel,
410 drive,
411 via_udma133_tim[drvp->UDMA_mode]);
412 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
413 /* 686b */
414 udmatim_reg |= APO_UDMA_TIME(
415 chp->ch_channel,
416 drive,
417 via_udma100_tim[drvp->UDMA_mode]);
418 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
419 /* 596b or 686a */
420 udmatim_reg |= APO_UDMA_CLK66(
421 chp->ch_channel);
422 udmatim_reg |= APO_UDMA_TIME(
423 chp->ch_channel,
424 drive,
425 via_udma66_tim[drvp->UDMA_mode]);
426 } else {
427 /* 596a or 586b */
428 udmatim_reg |= APO_UDMA_TIME(
429 chp->ch_channel,
430 drive,
431 via_udma33_tim[drvp->UDMA_mode]);
432 }
433 break;
434 case PCI_VENDOR_AMD:
435 case PCI_VENDOR_NVIDIA:
436 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
437 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
438 break;
439 }
440 /* can use PIO timings, MW DMA unused */
441 mode = drvp->PIO_mode;
442 } else {
443 /* use Multiword DMA, but only if revision is OK */
444 s = splbio();
445 drvp->drive_flags &= ~DRIVE_UDMA;
446 splx(s);
447 #ifndef PCIIDE_AMD756_ENABLEDMA
448 /*
449 * The workaround doesn't seem to be necessary
450 * with all drives, so it can be disabled by
451 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
452 * triggered.
453 */
454 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
455 sc->sc_pp->ide_product ==
456 PCI_PRODUCT_AMD_PBC756_IDE &&
457 AMD756_CHIPREV_DISABLEDMA(rev)) {
458 aprint_normal(
459 "%s:%d:%d: multi-word DMA disabled due "
460 "to chip revision\n",
461 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
462 chp->ch_channel, drive);
463 mode = drvp->PIO_mode;
464 s = splbio();
465 drvp->drive_flags &= ~DRIVE_DMA;
466 splx(s);
467 goto pio;
468 }
469 #endif
470 /* mode = min(pio, dma+2) */
471 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
472 mode = drvp->PIO_mode;
473 else
474 mode = drvp->DMA_mode + 2;
475 }
476 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
477
478 pio: /* setup PIO mode */
479 if (mode <= 2) {
480 drvp->DMA_mode = 0;
481 drvp->PIO_mode = 0;
482 mode = 0;
483 } else {
484 drvp->PIO_mode = mode;
485 drvp->DMA_mode = mode - 2;
486 }
487 datatim_reg |=
488 APO_DATATIM_PULSE(chp->ch_channel, drive,
489 apollo_pio_set[mode]) |
490 APO_DATATIM_RECOV(chp->ch_channel, drive,
491 apollo_pio_rec[mode]);
492 }
493 if (idedma_ctl != 0) {
494 /* Add software bits in status register */
495 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
496 idedma_ctl);
497 }
498 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
499 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
500 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
501 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
502 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
503 }
504
505 static void
506 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
507 {
508 struct pciide_channel *cp;
509 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
510 int channel;
511 bus_size_t cmdsize, ctlsize;
512
513 if (pciide_chipen(sc, pa) == 0)
514 return;
515
516 if (interface == 0) {
517 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
518 DEBUG_PROBE);
519 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
520 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
521 }
522
523 aprint_normal("%s: bus-master DMA support present",
524 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
525 pciide_mapreg_dma(sc, pa);
526 aprint_normal("\n");
527
528 if (sc->sc_dma_ok) {
529 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
530 sc->sc_wdcdev.irqack = pciide_irqack;
531 }
532 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
533 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
534 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
535
536 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
537 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
538 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
539 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
540
541 wdc_allocate_regs(&sc->sc_wdcdev);
542
543 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
544 channel++) {
545 cp = &sc->pciide_channels[channel];
546 if (pciide_chansetup(sc, channel, interface) == 0)
547 continue;
548 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
549 pciide_pci_intr);
550 }
551 }
552