viaide.c revision 1.14
1 /* $NetBSD: viaide.c,v 1.14 2004/08/13 04:10:49 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_apollo_reg.h> 41 42 static int via_pcib_match(struct pci_attach_args *); 43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 44 static void via_sata_chip_map(struct pciide_softc *, 45 struct pci_attach_args *); 46 static void via_setup_channel(struct wdc_channel *); 47 48 static int viaide_match(struct device *, struct cfdata *, void *); 49 static void viaide_attach(struct device *, struct device *, void *); 50 static const struct pciide_product_desc * 51 viaide_lookup(pcireg_t); 52 53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 54 viaide_match, viaide_attach, NULL, NULL); 55 56 static const struct pciide_product_desc pciide_amd_products[] = { 57 { PCI_PRODUCT_AMD_PBC756_IDE, 58 0, 59 "Advanced Micro Devices AMD756 IDE Controller", 60 via_chip_map 61 }, 62 { PCI_PRODUCT_AMD_PBC766_IDE, 63 0, 64 "Advanced Micro Devices AMD766 IDE Controller", 65 via_chip_map 66 }, 67 { PCI_PRODUCT_AMD_PBC768_IDE, 68 0, 69 "Advanced Micro Devices AMD768 IDE Controller", 70 via_chip_map 71 }, 72 { PCI_PRODUCT_AMD_PBC8111_IDE, 73 0, 74 "Advanced Micro Devices AMD8111 IDE Controller", 75 via_chip_map 76 }, 77 { 0, 78 0, 79 NULL, 80 NULL 81 } 82 }; 83 84 static const struct pciide_product_desc pciide_nvidia_products[] = { 85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 86 0, 87 "NVIDIA nForce IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 91 0, 92 "NVIDIA nForce2 IDE Controller", 93 via_chip_map 94 }, 95 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 96 0, 97 "NVIDIA nForce3 IDE Controller", 98 via_chip_map 99 }, 100 { 0, 101 0, 102 NULL, 103 NULL 104 } 105 }; 106 107 static const struct pciide_product_desc pciide_via_products[] = { 108 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 109 0, 110 NULL, 111 via_chip_map, 112 }, 113 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 114 0, 115 NULL, 116 via_chip_map, 117 }, 118 { PCI_PRODUCT_VIATECH_VT8237_SATA, 119 0, 120 "VIA Technologies VT8237 SATA Controller", 121 via_sata_chip_map, 122 }, 123 { 0, 124 0, 125 NULL, 126 NULL 127 } 128 }; 129 130 static const struct pciide_product_desc * 131 viaide_lookup(pcireg_t id) 132 { 133 134 switch (PCI_VENDOR(id)) { 135 case PCI_VENDOR_VIATECH: 136 return (pciide_lookup_product(id, pciide_via_products)); 137 138 case PCI_VENDOR_AMD: 139 return (pciide_lookup_product(id, pciide_amd_products)); 140 141 case PCI_VENDOR_NVIDIA: 142 return (pciide_lookup_product(id, pciide_nvidia_products)); 143 } 144 return (NULL); 145 } 146 147 static int 148 viaide_match(struct device *parent, struct cfdata *match, void *aux) 149 { 150 struct pci_attach_args *pa = aux; 151 152 if (viaide_lookup(pa->pa_id) != NULL) 153 return (2); 154 return (0); 155 } 156 157 static void 158 viaide_attach(struct device *parent, struct device *self, void *aux) 159 { 160 struct pci_attach_args *pa = aux; 161 struct pciide_softc *sc = (struct pciide_softc *)self; 162 const struct pciide_product_desc *pp; 163 164 pp = viaide_lookup(pa->pa_id); 165 if (pp == NULL) 166 panic("viaide_attach"); 167 pciide_common_attach(sc, pa, pp); 168 } 169 170 static int 171 via_pcib_match(struct pci_attach_args *pa) 172 { 173 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 174 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 175 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 176 return (1); 177 return 0; 178 } 179 180 static void 181 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 182 { 183 struct pciide_channel *cp; 184 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 185 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 186 int channel; 187 u_int32_t ideconf; 188 bus_size_t cmdsize, ctlsize; 189 pcireg_t pcib_id, pcib_class; 190 struct pci_attach_args pcib_pa; 191 192 if (pciide_chipen(sc, pa) == 0) 193 return; 194 195 switch (vendor) { 196 case PCI_VENDOR_VIATECH: 197 /* 198 * get a PCI tag for the ISA bridge. 199 */ 200 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 201 goto unknown; 202 pcib_id = pcib_pa.pa_id; 203 pcib_class = pcib_pa.pa_class; 204 aprint_normal("%s: VIA Technologies ", 205 sc->sc_wdcdev.sc_dev.dv_xname); 206 switch (PCI_PRODUCT(pcib_id)) { 207 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 208 aprint_normal("VT82C586 (Apollo VP) "); 209 if(PCI_REVISION(pcib_class) >= 0x02) { 210 aprint_normal("ATA33 controller\n"); 211 sc->sc_wdcdev.UDMA_cap = 2; 212 } else { 213 aprint_normal("controller\n"); 214 sc->sc_wdcdev.UDMA_cap = 0; 215 } 216 break; 217 case PCI_PRODUCT_VIATECH_VT82C596A: 218 aprint_normal("VT82C596A (Apollo Pro) "); 219 if (PCI_REVISION(pcib_class) >= 0x12) { 220 aprint_normal("ATA66 controller\n"); 221 sc->sc_wdcdev.UDMA_cap = 4; 222 } else { 223 aprint_normal("ATA33 controller\n"); 224 sc->sc_wdcdev.UDMA_cap = 2; 225 } 226 break; 227 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 228 aprint_normal("VT82C686A (Apollo KX133) "); 229 if (PCI_REVISION(pcib_class) >= 0x40) { 230 aprint_normal("ATA100 controller\n"); 231 sc->sc_wdcdev.UDMA_cap = 5; 232 } else { 233 aprint_normal("ATA66 controller\n"); 234 sc->sc_wdcdev.UDMA_cap = 4; 235 } 236 break; 237 case PCI_PRODUCT_VIATECH_VT8231: 238 aprint_normal("VT8231 ATA100 controller\n"); 239 sc->sc_wdcdev.UDMA_cap = 5; 240 break; 241 case PCI_PRODUCT_VIATECH_VT8233: 242 aprint_normal("VT8233 ATA100 controller\n"); 243 sc->sc_wdcdev.UDMA_cap = 5; 244 break; 245 case PCI_PRODUCT_VIATECH_VT8233A: 246 aprint_normal("VT8233A ATA133 controller\n"); 247 sc->sc_wdcdev.UDMA_cap = 6; 248 break; 249 case PCI_PRODUCT_VIATECH_VT8235: 250 aprint_normal("VT8235 ATA133 controller\n"); 251 sc->sc_wdcdev.UDMA_cap = 6; 252 break; 253 case PCI_PRODUCT_VIATECH_VT8237: 254 aprint_normal("VT8237 ATA133 controller\n"); 255 sc->sc_wdcdev.UDMA_cap = 6; 256 break; 257 default: 258 unknown: 259 aprint_normal("unknown VIA ATA controller\n"); 260 sc->sc_wdcdev.UDMA_cap = 0; 261 } 262 sc->sc_apo_regbase = APO_VIA_REGBASE; 263 break; 264 case PCI_VENDOR_AMD: 265 switch (sc->sc_pp->ide_product) { 266 case PCI_PRODUCT_AMD_PBC8111_IDE: 267 sc->sc_wdcdev.UDMA_cap = 6; 268 break; 269 case PCI_PRODUCT_AMD_PBC766_IDE: 270 case PCI_PRODUCT_AMD_PBC768_IDE: 271 sc->sc_wdcdev.UDMA_cap = 5; 272 break; 273 default: 274 sc->sc_wdcdev.UDMA_cap = 4; 275 } 276 sc->sc_apo_regbase = APO_AMD_REGBASE; 277 break; 278 case PCI_VENDOR_NVIDIA: 279 switch (sc->sc_pp->ide_product) { 280 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 281 sc->sc_wdcdev.UDMA_cap = 5; 282 break; 283 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 284 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 285 sc->sc_wdcdev.UDMA_cap = 6; 286 break; 287 } 288 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 289 break; 290 default: 291 panic("via_chip_map: unknown vendor"); 292 } 293 294 aprint_normal("%s: bus-master DMA support present", 295 sc->sc_wdcdev.sc_dev.dv_xname); 296 pciide_mapreg_dma(sc, pa); 297 aprint_normal("\n"); 298 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 299 if (sc->sc_dma_ok) { 300 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 301 sc->sc_wdcdev.irqack = pciide_irqack; 302 if (sc->sc_wdcdev.UDMA_cap > 0) 303 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 304 } 305 sc->sc_wdcdev.PIO_cap = 4; 306 sc->sc_wdcdev.DMA_cap = 2; 307 sc->sc_wdcdev.set_modes = via_setup_channel; 308 sc->sc_wdcdev.channels = sc->wdc_chanarray; 309 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 310 311 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 312 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 313 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 314 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 315 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 316 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 317 DEBUG_PROBE); 318 319 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 320 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 321 cp = &sc->pciide_channels[channel]; 322 if (pciide_chansetup(sc, channel, interface) == 0) 323 continue; 324 325 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 326 aprint_normal("%s: %s channel ignored (disabled)\n", 327 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 328 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 329 continue; 330 } 331 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 332 pciide_pci_intr); 333 } 334 } 335 336 static void 337 via_setup_channel(struct wdc_channel *chp) 338 { 339 u_int32_t udmatim_reg, datatim_reg; 340 u_int8_t idedma_ctl; 341 int mode, drive; 342 struct ata_drive_datas *drvp; 343 struct pciide_channel *cp = (struct pciide_channel*)chp; 344 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 345 struct wdc_softc *wdc = &sc->sc_wdcdev; 346 #ifndef PCIIDE_AMD756_ENABLEDMA 347 int rev = PCI_REVISION( 348 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 349 #endif 350 351 idedma_ctl = 0; 352 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 353 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 354 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 355 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 356 357 /* setup DMA if needed */ 358 pciide_channel_dma_setup(cp); 359 360 for (drive = 0; drive < 2; drive++) { 361 drvp = &chp->ch_drive[drive]; 362 /* If no drive, skip */ 363 if ((drvp->drive_flags & DRIVE) == 0) 364 continue; 365 /* add timing values, setup DMA if needed */ 366 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 367 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 368 mode = drvp->PIO_mode; 369 goto pio; 370 } 371 if ((wdc->cap & WDC_CAPABILITY_UDMA) && 372 (drvp->drive_flags & DRIVE_UDMA)) { 373 /* use Ultra/DMA */ 374 drvp->drive_flags &= ~DRIVE_DMA; 375 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 376 APO_UDMA_EN_MTH(chp->ch_channel, drive); 377 switch (PCI_VENDOR(sc->sc_pci_id)) { 378 case PCI_VENDOR_VIATECH: 379 if (sc->sc_wdcdev.UDMA_cap == 6) { 380 /* 8233a */ 381 udmatim_reg |= APO_UDMA_TIME( 382 chp->ch_channel, 383 drive, 384 via_udma133_tim[drvp->UDMA_mode]); 385 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 386 /* 686b */ 387 udmatim_reg |= APO_UDMA_TIME( 388 chp->ch_channel, 389 drive, 390 via_udma100_tim[drvp->UDMA_mode]); 391 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 392 /* 596b or 686a */ 393 udmatim_reg |= APO_UDMA_CLK66( 394 chp->ch_channel); 395 udmatim_reg |= APO_UDMA_TIME( 396 chp->ch_channel, 397 drive, 398 via_udma66_tim[drvp->UDMA_mode]); 399 } else { 400 /* 596a or 586b */ 401 udmatim_reg |= APO_UDMA_TIME( 402 chp->ch_channel, 403 drive, 404 via_udma33_tim[drvp->UDMA_mode]); 405 } 406 break; 407 case PCI_VENDOR_AMD: 408 case PCI_VENDOR_NVIDIA: 409 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 410 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 411 break; 412 } 413 /* can use PIO timings, MW DMA unused */ 414 mode = drvp->PIO_mode; 415 } else { 416 /* use Multiword DMA, but only if revision is OK */ 417 drvp->drive_flags &= ~DRIVE_UDMA; 418 #ifndef PCIIDE_AMD756_ENABLEDMA 419 /* 420 * The workaround doesn't seem to be necessary 421 * with all drives, so it can be disabled by 422 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 423 * triggered. 424 */ 425 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 426 sc->sc_pp->ide_product == 427 PCI_PRODUCT_AMD_PBC756_IDE && 428 AMD756_CHIPREV_DISABLEDMA(rev)) { 429 aprint_normal( 430 "%s:%d:%d: multi-word DMA disabled due " 431 "to chip revision\n", 432 sc->sc_wdcdev.sc_dev.dv_xname, 433 chp->ch_channel, drive); 434 mode = drvp->PIO_mode; 435 drvp->drive_flags &= ~DRIVE_DMA; 436 goto pio; 437 } 438 #endif 439 /* mode = min(pio, dma+2) */ 440 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 441 mode = drvp->PIO_mode; 442 else 443 mode = drvp->DMA_mode + 2; 444 } 445 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 446 447 pio: /* setup PIO mode */ 448 if (mode <= 2) { 449 drvp->DMA_mode = 0; 450 drvp->PIO_mode = 0; 451 mode = 0; 452 } else { 453 drvp->PIO_mode = mode; 454 drvp->DMA_mode = mode - 2; 455 } 456 datatim_reg |= 457 APO_DATATIM_PULSE(chp->ch_channel, drive, 458 apollo_pio_set[mode]) | 459 APO_DATATIM_RECOV(chp->ch_channel, drive, 460 apollo_pio_rec[mode]); 461 } 462 if (idedma_ctl != 0) { 463 /* Add software bits in status register */ 464 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 465 idedma_ctl); 466 } 467 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 468 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 469 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 470 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 471 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 472 } 473 474 static void 475 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 476 { 477 struct pciide_channel *cp; 478 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 479 int channel; 480 bus_size_t cmdsize, ctlsize; 481 482 if (pciide_chipen(sc, pa) == 0) 483 return; 484 485 if (interface == 0) { 486 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 487 DEBUG_PROBE); 488 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 489 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 490 } 491 492 aprint_normal("%s: bus-master DMA support present", 493 sc->sc_wdcdev.sc_dev.dv_xname); 494 pciide_mapreg_dma(sc, pa); 495 aprint_normal("\n"); 496 497 if (sc->sc_dma_ok) { 498 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA; 499 sc->sc_wdcdev.irqack = pciide_irqack; 500 } 501 sc->sc_wdcdev.PIO_cap = 4; 502 sc->sc_wdcdev.DMA_cap = 2; 503 sc->sc_wdcdev.UDMA_cap = 6; 504 505 sc->sc_wdcdev.channels = sc->wdc_chanarray; 506 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 507 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 508 sc->sc_wdcdev.set_modes = sata_setup_channel; 509 510 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 511 cp = &sc->pciide_channels[channel]; 512 if (pciide_chansetup(sc, channel, interface) == 0) 513 continue; 514 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 515 pciide_pci_intr); 516 } 517 } 518
Indexes created Tue Oct 21 19:09:51 GMT 2025