viaide.c revision 1.22
1 /* $NetBSD: viaide.c,v 1.22 2005/02/01 18:21:42 abs Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pciidereg.h> 39 #include <dev/pci/pciidevar.h> 40 #include <dev/pci/pciide_apollo_reg.h> 41 42 static int via_pcib_match(struct pci_attach_args *); 43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 44 static void via_sata_chip_map(struct pciide_softc *, 45 struct pci_attach_args *); 46 static void via_setup_channel(struct ata_channel *); 47 48 static int viaide_match(struct device *, struct cfdata *, void *); 49 static void viaide_attach(struct device *, struct device *, void *); 50 static const struct pciide_product_desc * 51 viaide_lookup(pcireg_t); 52 53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 54 viaide_match, viaide_attach, NULL, NULL); 55 56 static const struct pciide_product_desc pciide_amd_products[] = { 57 { PCI_PRODUCT_AMD_PBC756_IDE, 58 0, 59 "Advanced Micro Devices AMD756 IDE Controller", 60 via_chip_map 61 }, 62 { PCI_PRODUCT_AMD_PBC766_IDE, 63 0, 64 "Advanced Micro Devices AMD766 IDE Controller", 65 via_chip_map 66 }, 67 { PCI_PRODUCT_AMD_PBC768_IDE, 68 0, 69 "Advanced Micro Devices AMD768 IDE Controller", 70 via_chip_map 71 }, 72 { PCI_PRODUCT_AMD_PBC8111_IDE, 73 0, 74 "Advanced Micro Devices AMD8111 IDE Controller", 75 via_chip_map 76 }, 77 { 0, 78 0, 79 NULL, 80 NULL 81 } 82 }; 83 84 static const struct pciide_product_desc pciide_nvidia_products[] = { 85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 86 0, 87 "NVIDIA nForce IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 91 0, 92 "NVIDIA nForce2 IDE Controller", 93 via_chip_map 94 }, 95 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 96 0, 97 "NVIDIA nForce2 Ultra 400 IDE Controller", 98 via_chip_map 99 }, 100 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 101 0, 102 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 103 via_sata_chip_map 104 }, 105 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 106 0, 107 "NVIDIA nForce3 IDE Controller", 108 via_chip_map 109 }, 110 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 111 0, 112 "NVIDIA nForce3 250 IDE Controller", 113 via_chip_map 114 }, 115 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 116 0, 117 "NVIDIA nForce3 250 Serial ATA Controller", 118 via_sata_chip_map 119 }, 120 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 121 0, 122 "NVIDIA nForce4 IDE Controller", 123 via_chip_map 124 }, 125 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 126 0, 127 "NVIDIA nForce4 Serial ATA Controller", 128 via_sata_chip_map 129 }, 130 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 131 0, 132 "NVIDIA nForce4 Serial ATA Controller", 133 via_sata_chip_map 134 }, 135 { 0, 136 0, 137 NULL, 138 NULL 139 } 140 }; 141 142 static const struct pciide_product_desc pciide_via_products[] = { 143 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 144 0, 145 NULL, 146 via_chip_map, 147 }, 148 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 149 0, 150 NULL, 151 via_chip_map, 152 }, 153 { PCI_PRODUCT_VIATECH_VT642_RAID, 154 0, 155 "VIA Technologies VT642 SATA RAID Controller", 156 via_sata_chip_map, 157 }, 158 { PCI_PRODUCT_VIATECH_VT8237_SATA, 159 0, 160 "VIA Technologies VT8237 SATA Controller", 161 via_sata_chip_map, 162 }, 163 { 0, 164 0, 165 NULL, 166 NULL 167 } 168 }; 169 170 static const struct pciide_product_desc * 171 viaide_lookup(pcireg_t id) 172 { 173 174 switch (PCI_VENDOR(id)) { 175 case PCI_VENDOR_VIATECH: 176 return (pciide_lookup_product(id, pciide_via_products)); 177 178 case PCI_VENDOR_AMD: 179 return (pciide_lookup_product(id, pciide_amd_products)); 180 181 case PCI_VENDOR_NVIDIA: 182 return (pciide_lookup_product(id, pciide_nvidia_products)); 183 } 184 return (NULL); 185 } 186 187 static int 188 viaide_match(struct device *parent, struct cfdata *match, void *aux) 189 { 190 struct pci_attach_args *pa = aux; 191 192 if (viaide_lookup(pa->pa_id) != NULL) 193 return (2); 194 return (0); 195 } 196 197 static void 198 viaide_attach(struct device *parent, struct device *self, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 struct pciide_softc *sc = (struct pciide_softc *)self; 202 const struct pciide_product_desc *pp; 203 204 pp = viaide_lookup(pa->pa_id); 205 if (pp == NULL) 206 panic("viaide_attach"); 207 pciide_common_attach(sc, pa, pp); 208 } 209 210 static int 211 via_pcib_match(struct pci_attach_args *pa) 212 { 213 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 214 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 215 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 216 return (1); 217 return 0; 218 } 219 220 static void 221 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 222 { 223 struct pciide_channel *cp; 224 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 225 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 226 int channel; 227 u_int32_t ideconf; 228 bus_size_t cmdsize, ctlsize; 229 pcireg_t pcib_id, pcib_class; 230 struct pci_attach_args pcib_pa; 231 232 if (pciide_chipen(sc, pa) == 0) 233 return; 234 235 switch (vendor) { 236 case PCI_VENDOR_VIATECH: 237 /* 238 * get a PCI tag for the ISA bridge. 239 */ 240 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 241 goto unknown; 242 pcib_id = pcib_pa.pa_id; 243 pcib_class = pcib_pa.pa_class; 244 aprint_normal("%s: VIA Technologies ", 245 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 246 switch (PCI_PRODUCT(pcib_id)) { 247 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 248 aprint_normal("VT82C586 (Apollo VP) "); 249 if(PCI_REVISION(pcib_class) >= 0x02) { 250 aprint_normal("ATA33 controller\n"); 251 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 252 } else { 253 aprint_normal("controller\n"); 254 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 255 } 256 break; 257 case PCI_PRODUCT_VIATECH_VT82C596A: 258 aprint_normal("VT82C596A (Apollo Pro) "); 259 if (PCI_REVISION(pcib_class) >= 0x12) { 260 aprint_normal("ATA66 controller\n"); 261 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 262 } else { 263 aprint_normal("ATA33 controller\n"); 264 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 265 } 266 break; 267 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 268 aprint_normal("VT82C686A (Apollo KX133) "); 269 if (PCI_REVISION(pcib_class) >= 0x40) { 270 aprint_normal("ATA100 controller\n"); 271 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 272 } else { 273 aprint_normal("ATA66 controller\n"); 274 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 275 } 276 break; 277 case PCI_PRODUCT_VIATECH_VT8231: 278 aprint_normal("VT8231 ATA100 controller\n"); 279 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 280 break; 281 case PCI_PRODUCT_VIATECH_VT8233: 282 aprint_normal("VT8233 ATA100 controller\n"); 283 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 284 break; 285 case PCI_PRODUCT_VIATECH_VT8233A: 286 aprint_normal("VT8233A ATA133 controller\n"); 287 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 288 break; 289 case PCI_PRODUCT_VIATECH_VT8235: 290 aprint_normal("VT8235 ATA133 controller\n"); 291 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 292 break; 293 case PCI_PRODUCT_VIATECH_VT8237: 294 aprint_normal("VT8237 ATA133 controller\n"); 295 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 296 break; 297 default: 298 unknown: 299 aprint_normal("unknown VIA ATA controller\n"); 300 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 301 } 302 sc->sc_apo_regbase = APO_VIA_REGBASE; 303 break; 304 case PCI_VENDOR_AMD: 305 switch (sc->sc_pp->ide_product) { 306 case PCI_PRODUCT_AMD_PBC8111_IDE: 307 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 308 break; 309 case PCI_PRODUCT_AMD_PBC766_IDE: 310 case PCI_PRODUCT_AMD_PBC768_IDE: 311 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 312 break; 313 default: 314 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 315 } 316 sc->sc_apo_regbase = APO_AMD_REGBASE; 317 break; 318 case PCI_VENDOR_NVIDIA: 319 switch (sc->sc_pp->ide_product) { 320 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 321 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 322 break; 323 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 324 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 325 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 326 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 327 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 328 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 329 break; 330 } 331 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 332 break; 333 default: 334 panic("via_chip_map: unknown vendor"); 335 } 336 337 aprint_normal("%s: bus-master DMA support present", 338 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 339 pciide_mapreg_dma(sc, pa); 340 aprint_normal("\n"); 341 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 342 if (sc->sc_dma_ok) { 343 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 344 sc->sc_wdcdev.irqack = pciide_irqack; 345 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 346 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 347 } 348 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 349 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 350 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 351 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 352 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 353 354 wdc_allocate_regs(&sc->sc_wdcdev); 355 356 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 357 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 358 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 359 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 360 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 361 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 362 DEBUG_PROBE); 363 364 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 365 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 366 channel++) { 367 cp = &sc->pciide_channels[channel]; 368 if (pciide_chansetup(sc, channel, interface) == 0) 369 continue; 370 371 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 372 aprint_normal("%s: %s channel ignored (disabled)\n", 373 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 374 cp->ata_channel.ch_flags |= ATACH_DISABLED; 375 continue; 376 } 377 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 378 pciide_pci_intr); 379 } 380 } 381 382 static void 383 via_setup_channel(struct ata_channel *chp) 384 { 385 u_int32_t udmatim_reg, datatim_reg; 386 u_int8_t idedma_ctl; 387 int mode, drive, s; 388 struct ata_drive_datas *drvp; 389 struct atac_softc *atac = chp->ch_atac; 390 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 391 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 392 #ifndef PCIIDE_AMD756_ENABLEDMA 393 int rev = PCI_REVISION( 394 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 395 #endif 396 397 idedma_ctl = 0; 398 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 399 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 400 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 401 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 402 403 /* setup DMA if needed */ 404 pciide_channel_dma_setup(cp); 405 406 for (drive = 0; drive < 2; drive++) { 407 drvp = &chp->ch_drive[drive]; 408 /* If no drive, skip */ 409 if ((drvp->drive_flags & DRIVE) == 0) 410 continue; 411 /* add timing values, setup DMA if needed */ 412 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 413 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 414 mode = drvp->PIO_mode; 415 goto pio; 416 } 417 if ((atac->atac_cap & ATAC_CAP_UDMA) && 418 (drvp->drive_flags & DRIVE_UDMA)) { 419 /* use Ultra/DMA */ 420 s = splbio(); 421 drvp->drive_flags &= ~DRIVE_DMA; 422 splx(s); 423 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 424 APO_UDMA_EN_MTH(chp->ch_channel, drive); 425 switch (PCI_VENDOR(sc->sc_pci_id)) { 426 case PCI_VENDOR_VIATECH: 427 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 428 /* 8233a */ 429 udmatim_reg |= APO_UDMA_TIME( 430 chp->ch_channel, 431 drive, 432 via_udma133_tim[drvp->UDMA_mode]); 433 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 434 /* 686b */ 435 udmatim_reg |= APO_UDMA_TIME( 436 chp->ch_channel, 437 drive, 438 via_udma100_tim[drvp->UDMA_mode]); 439 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 440 /* 596b or 686a */ 441 udmatim_reg |= APO_UDMA_CLK66( 442 chp->ch_channel); 443 udmatim_reg |= APO_UDMA_TIME( 444 chp->ch_channel, 445 drive, 446 via_udma66_tim[drvp->UDMA_mode]); 447 } else { 448 /* 596a or 586b */ 449 udmatim_reg |= APO_UDMA_TIME( 450 chp->ch_channel, 451 drive, 452 via_udma33_tim[drvp->UDMA_mode]); 453 } 454 break; 455 case PCI_VENDOR_AMD: 456 case PCI_VENDOR_NVIDIA: 457 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 458 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 459 break; 460 } 461 /* can use PIO timings, MW DMA unused */ 462 mode = drvp->PIO_mode; 463 } else { 464 /* use Multiword DMA, but only if revision is OK */ 465 s = splbio(); 466 drvp->drive_flags &= ~DRIVE_UDMA; 467 splx(s); 468 #ifndef PCIIDE_AMD756_ENABLEDMA 469 /* 470 * The workaround doesn't seem to be necessary 471 * with all drives, so it can be disabled by 472 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 473 * triggered. 474 */ 475 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 476 sc->sc_pp->ide_product == 477 PCI_PRODUCT_AMD_PBC756_IDE && 478 AMD756_CHIPREV_DISABLEDMA(rev)) { 479 aprint_normal( 480 "%s:%d:%d: multi-word DMA disabled due " 481 "to chip revision\n", 482 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 483 chp->ch_channel, drive); 484 mode = drvp->PIO_mode; 485 s = splbio(); 486 drvp->drive_flags &= ~DRIVE_DMA; 487 splx(s); 488 goto pio; 489 } 490 #endif 491 /* mode = min(pio, dma+2) */ 492 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 493 mode = drvp->PIO_mode; 494 else 495 mode = drvp->DMA_mode + 2; 496 } 497 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 498 499 pio: /* setup PIO mode */ 500 if (mode <= 2) { 501 drvp->DMA_mode = 0; 502 drvp->PIO_mode = 0; 503 mode = 0; 504 } else { 505 drvp->PIO_mode = mode; 506 drvp->DMA_mode = mode - 2; 507 } 508 datatim_reg |= 509 APO_DATATIM_PULSE(chp->ch_channel, drive, 510 apollo_pio_set[mode]) | 511 APO_DATATIM_RECOV(chp->ch_channel, drive, 512 apollo_pio_rec[mode]); 513 } 514 if (idedma_ctl != 0) { 515 /* Add software bits in status register */ 516 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 517 idedma_ctl); 518 } 519 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 520 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 521 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 522 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 523 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 524 } 525 526 static void 527 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 528 { 529 struct pciide_channel *cp; 530 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 531 int channel; 532 bus_size_t cmdsize, ctlsize; 533 534 if (pciide_chipen(sc, pa) == 0) 535 return; 536 537 if (interface == 0) { 538 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 539 DEBUG_PROBE); 540 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 541 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 542 } 543 544 aprint_normal("%s: bus-master DMA support present", 545 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 546 pciide_mapreg_dma(sc, pa); 547 aprint_normal("\n"); 548 549 if (sc->sc_dma_ok) { 550 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 551 sc->sc_wdcdev.irqack = pciide_irqack; 552 } 553 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 554 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 555 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 556 557 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 558 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 559 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 560 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 561 562 wdc_allocate_regs(&sc->sc_wdcdev); 563 564 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 565 channel++) { 566 cp = &sc->pciide_channels[channel]; 567 if (pciide_chansetup(sc, channel, interface) == 0) 568 continue; 569 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 570 pciide_pci_intr); 571 } 572 } 573
Indexes created Fri Oct 17 09:09:57 GMT 2025