viaide.c revision 1.24.2.1 1 /* $NetBSD: viaide.c,v 1.24.2.1 2006/01/05 22:17:39 riz Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35
36 #include <dev/pci/pcivar.h>
37 #include <dev/pci/pcidevs.h>
38 #include <dev/pci/pciidereg.h>
39 #include <dev/pci/pciidevar.h>
40 #include <dev/pci/pciide_apollo_reg.h>
41
42 static int via_pcib_match(struct pci_attach_args *);
43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
44 static void via_sata_chip_map(struct pciide_softc *,
45 struct pci_attach_args *);
46 static void via_setup_channel(struct ata_channel *);
47
48 static int viaide_match(struct device *, struct cfdata *, void *);
49 static void viaide_attach(struct device *, struct device *, void *);
50 static const struct pciide_product_desc *
51 viaide_lookup(pcireg_t);
52
53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
54 viaide_match, viaide_attach, NULL, NULL);
55
56 static const struct pciide_product_desc pciide_amd_products[] = {
57 { PCI_PRODUCT_AMD_PBC756_IDE,
58 0,
59 "Advanced Micro Devices AMD756 IDE Controller",
60 via_chip_map
61 },
62 { PCI_PRODUCT_AMD_PBC766_IDE,
63 0,
64 "Advanced Micro Devices AMD766 IDE Controller",
65 via_chip_map
66 },
67 { PCI_PRODUCT_AMD_PBC768_IDE,
68 0,
69 "Advanced Micro Devices AMD768 IDE Controller",
70 via_chip_map
71 },
72 { PCI_PRODUCT_AMD_PBC8111_IDE,
73 0,
74 "Advanced Micro Devices AMD8111 IDE Controller",
75 via_chip_map
76 },
77 { 0,
78 0,
79 NULL,
80 NULL
81 }
82 };
83
84 static const struct pciide_product_desc pciide_nvidia_products[] = {
85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
86 0,
87 "NVIDIA nForce IDE Controller",
88 via_chip_map
89 },
90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
91 0,
92 "NVIDIA nForce2 IDE Controller",
93 via_chip_map
94 },
95 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
96 0,
97 "NVIDIA nForce2 Ultra 400 IDE Controller",
98 via_chip_map
99 },
100 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
101 0,
102 "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
103 via_sata_chip_map
104 },
105 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
106 0,
107 "NVIDIA nForce3 IDE Controller",
108 via_chip_map
109 },
110 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
111 0,
112 "NVIDIA nForce3 250 IDE Controller",
113 via_chip_map
114 },
115 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
116 0,
117 "NVIDIA nForce3 250 Serial ATA Controller",
118 via_sata_chip_map
119 },
120 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
121 0,
122 "NVIDIA nForce4 IDE Controller",
123 via_chip_map
124 },
125 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
126 0,
127 "NVIDIA nForce4 Serial ATA Controller",
128 via_sata_chip_map
129 },
130 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
131 0,
132 "NVIDIA nForce4 Serial ATA Controller",
133 via_sata_chip_map
134 },
135 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
136 0,
137 "NVIDIA nForce430 IDE Controller",
138 via_chip_map
139 },
140 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
141 0,
142 "NVIDIA nForce430 Serial ATA Controller",
143 via_sata_chip_map
144 },
145 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
146 0,
147 "NVIDIA nForce430 Serial ATA Controller",
148 via_sata_chip_map
149 },
150 { 0,
151 0,
152 NULL,
153 NULL
154 }
155 };
156
157 static const struct pciide_product_desc pciide_via_products[] = {
158 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
159 0,
160 NULL,
161 via_chip_map,
162 },
163 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
164 0,
165 NULL,
166 via_chip_map,
167 },
168 { PCI_PRODUCT_VIATECH_VT6421_RAID,
169 0,
170 "VIA Technologies VT6421 Serial RAID Controller",
171 via_sata_chip_map,
172 },
173 { PCI_PRODUCT_VIATECH_VT8237_SATA,
174 0,
175 "VIA Technologies VT8237 SATA Controller",
176 via_sata_chip_map,
177 },
178 { 0,
179 0,
180 NULL,
181 NULL
182 }
183 };
184
185 static const struct pciide_product_desc *
186 viaide_lookup(pcireg_t id)
187 {
188
189 switch (PCI_VENDOR(id)) {
190 case PCI_VENDOR_VIATECH:
191 return (pciide_lookup_product(id, pciide_via_products));
192
193 case PCI_VENDOR_AMD:
194 return (pciide_lookup_product(id, pciide_amd_products));
195
196 case PCI_VENDOR_NVIDIA:
197 return (pciide_lookup_product(id, pciide_nvidia_products));
198 }
199 return (NULL);
200 }
201
202 static int
203 viaide_match(struct device *parent, struct cfdata *match, void *aux)
204 {
205 struct pci_attach_args *pa = aux;
206
207 if (viaide_lookup(pa->pa_id) != NULL)
208 return (2);
209 return (0);
210 }
211
212 static void
213 viaide_attach(struct device *parent, struct device *self, void *aux)
214 {
215 struct pci_attach_args *pa = aux;
216 struct pciide_softc *sc = (struct pciide_softc *)self;
217 const struct pciide_product_desc *pp;
218
219 pp = viaide_lookup(pa->pa_id);
220 if (pp == NULL)
221 panic("viaide_attach");
222 pciide_common_attach(sc, pa, pp);
223 }
224
225 static int
226 via_pcib_match(struct pci_attach_args *pa)
227 {
228 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
229 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
230 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
231 return (1);
232 return 0;
233 }
234
235 static void
236 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
237 {
238 struct pciide_channel *cp;
239 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
240 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
241 int channel;
242 u_int32_t ideconf;
243 bus_size_t cmdsize, ctlsize;
244 pcireg_t pcib_id, pcib_class;
245 struct pci_attach_args pcib_pa;
246
247 if (pciide_chipen(sc, pa) == 0)
248 return;
249
250 switch (vendor) {
251 case PCI_VENDOR_VIATECH:
252 /*
253 * get a PCI tag for the ISA bridge.
254 */
255 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
256 goto unknown;
257 pcib_id = pcib_pa.pa_id;
258 pcib_class = pcib_pa.pa_class;
259 aprint_normal("%s: VIA Technologies ",
260 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
261 switch (PCI_PRODUCT(pcib_id)) {
262 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
263 aprint_normal("VT82C586 (Apollo VP) ");
264 if(PCI_REVISION(pcib_class) >= 0x02) {
265 aprint_normal("ATA33 controller\n");
266 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
267 } else {
268 aprint_normal("controller\n");
269 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
270 }
271 break;
272 case PCI_PRODUCT_VIATECH_VT82C596A:
273 aprint_normal("VT82C596A (Apollo Pro) ");
274 if (PCI_REVISION(pcib_class) >= 0x12) {
275 aprint_normal("ATA66 controller\n");
276 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
277 } else {
278 aprint_normal("ATA33 controller\n");
279 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
280 }
281 break;
282 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
283 aprint_normal("VT82C686A (Apollo KX133) ");
284 if (PCI_REVISION(pcib_class) >= 0x40) {
285 aprint_normal("ATA100 controller\n");
286 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
287 } else {
288 aprint_normal("ATA66 controller\n");
289 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
290 }
291 break;
292 case PCI_PRODUCT_VIATECH_VT8231:
293 aprint_normal("VT8231 ATA100 controller\n");
294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
295 break;
296 case PCI_PRODUCT_VIATECH_VT8233:
297 aprint_normal("VT8233 ATA100 controller\n");
298 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
299 break;
300 case PCI_PRODUCT_VIATECH_VT8233A:
301 aprint_normal("VT8233A ATA133 controller\n");
302 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
303 break;
304 case PCI_PRODUCT_VIATECH_VT8235:
305 aprint_normal("VT8235 ATA133 controller\n");
306 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
307 break;
308 case PCI_PRODUCT_VIATECH_VT8237:
309 aprint_normal("VT8237 ATA133 controller\n");
310 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
311 break;
312 default:
313 unknown:
314 aprint_normal("unknown VIA ATA controller\n");
315 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
316 }
317 sc->sc_apo_regbase = APO_VIA_REGBASE;
318 break;
319 case PCI_VENDOR_AMD:
320 switch (sc->sc_pp->ide_product) {
321 case PCI_PRODUCT_AMD_PBC8111_IDE:
322 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
323 break;
324 case PCI_PRODUCT_AMD_PBC766_IDE:
325 case PCI_PRODUCT_AMD_PBC768_IDE:
326 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
327 break;
328 default:
329 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
330 }
331 sc->sc_apo_regbase = APO_AMD_REGBASE;
332 break;
333 case PCI_VENDOR_NVIDIA:
334 switch (sc->sc_pp->ide_product) {
335 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
336 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
337 break;
338 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
339 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
340 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
341 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
342 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
343 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
344 break;
345 }
346 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
347 break;
348 default:
349 panic("via_chip_map: unknown vendor");
350 }
351
352 aprint_normal("%s: bus-master DMA support present",
353 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
354 pciide_mapreg_dma(sc, pa);
355 aprint_normal("\n");
356 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
357 if (sc->sc_dma_ok) {
358 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
359 sc->sc_wdcdev.irqack = pciide_irqack;
360 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
361 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
362 }
363 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
364 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
365 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
366 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
367 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
368
369 wdc_allocate_regs(&sc->sc_wdcdev);
370
371 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
372 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
373 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
374 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
375 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
376 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
377 DEBUG_PROBE);
378
379 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
380 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
381 channel++) {
382 cp = &sc->pciide_channels[channel];
383 if (pciide_chansetup(sc, channel, interface) == 0)
384 continue;
385
386 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
387 aprint_normal("%s: %s channel ignored (disabled)\n",
388 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
389 cp->ata_channel.ch_flags |= ATACH_DISABLED;
390 continue;
391 }
392 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
393 pciide_pci_intr);
394 }
395 }
396
397 static void
398 via_setup_channel(struct ata_channel *chp)
399 {
400 u_int32_t udmatim_reg, datatim_reg;
401 u_int8_t idedma_ctl;
402 int mode, drive, s;
403 struct ata_drive_datas *drvp;
404 struct atac_softc *atac = chp->ch_atac;
405 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
406 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
407 #ifndef PCIIDE_AMD756_ENABLEDMA
408 int rev = PCI_REVISION(
409 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
410 #endif
411
412 idedma_ctl = 0;
413 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
414 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
415 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
416 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
417
418 /* setup DMA if needed */
419 pciide_channel_dma_setup(cp);
420
421 for (drive = 0; drive < 2; drive++) {
422 drvp = &chp->ch_drive[drive];
423 /* If no drive, skip */
424 if ((drvp->drive_flags & DRIVE) == 0)
425 continue;
426 /* add timing values, setup DMA if needed */
427 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
428 (drvp->drive_flags & DRIVE_UDMA) == 0)) {
429 mode = drvp->PIO_mode;
430 goto pio;
431 }
432 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
433 (drvp->drive_flags & DRIVE_UDMA)) {
434 /* use Ultra/DMA */
435 s = splbio();
436 drvp->drive_flags &= ~DRIVE_DMA;
437 splx(s);
438 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
439 APO_UDMA_EN_MTH(chp->ch_channel, drive);
440 switch (PCI_VENDOR(sc->sc_pci_id)) {
441 case PCI_VENDOR_VIATECH:
442 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
443 /* 8233a */
444 udmatim_reg |= APO_UDMA_TIME(
445 chp->ch_channel,
446 drive,
447 via_udma133_tim[drvp->UDMA_mode]);
448 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
449 /* 686b */
450 udmatim_reg |= APO_UDMA_TIME(
451 chp->ch_channel,
452 drive,
453 via_udma100_tim[drvp->UDMA_mode]);
454 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
455 /* 596b or 686a */
456 udmatim_reg |= APO_UDMA_CLK66(
457 chp->ch_channel);
458 udmatim_reg |= APO_UDMA_TIME(
459 chp->ch_channel,
460 drive,
461 via_udma66_tim[drvp->UDMA_mode]);
462 } else {
463 /* 596a or 586b */
464 udmatim_reg |= APO_UDMA_TIME(
465 chp->ch_channel,
466 drive,
467 via_udma33_tim[drvp->UDMA_mode]);
468 }
469 break;
470 case PCI_VENDOR_AMD:
471 case PCI_VENDOR_NVIDIA:
472 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
473 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
474 break;
475 }
476 /* can use PIO timings, MW DMA unused */
477 mode = drvp->PIO_mode;
478 } else {
479 /* use Multiword DMA, but only if revision is OK */
480 s = splbio();
481 drvp->drive_flags &= ~DRIVE_UDMA;
482 splx(s);
483 #ifndef PCIIDE_AMD756_ENABLEDMA
484 /*
485 * The workaround doesn't seem to be necessary
486 * with all drives, so it can be disabled by
487 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
488 * triggered.
489 */
490 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
491 sc->sc_pp->ide_product ==
492 PCI_PRODUCT_AMD_PBC756_IDE &&
493 AMD756_CHIPREV_DISABLEDMA(rev)) {
494 aprint_normal(
495 "%s:%d:%d: multi-word DMA disabled due "
496 "to chip revision\n",
497 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
498 chp->ch_channel, drive);
499 mode = drvp->PIO_mode;
500 s = splbio();
501 drvp->drive_flags &= ~DRIVE_DMA;
502 splx(s);
503 goto pio;
504 }
505 #endif
506 /* mode = min(pio, dma+2) */
507 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
508 mode = drvp->PIO_mode;
509 else
510 mode = drvp->DMA_mode + 2;
511 }
512 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
513
514 pio: /* setup PIO mode */
515 if (mode <= 2) {
516 drvp->DMA_mode = 0;
517 drvp->PIO_mode = 0;
518 mode = 0;
519 } else {
520 drvp->PIO_mode = mode;
521 drvp->DMA_mode = mode - 2;
522 }
523 datatim_reg |=
524 APO_DATATIM_PULSE(chp->ch_channel, drive,
525 apollo_pio_set[mode]) |
526 APO_DATATIM_RECOV(chp->ch_channel, drive,
527 apollo_pio_rec[mode]);
528 }
529 if (idedma_ctl != 0) {
530 /* Add software bits in status register */
531 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
532 idedma_ctl);
533 }
534 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
535 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
536 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
537 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
538 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
539 }
540
541 static void
542 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
543 {
544 struct pciide_channel *cp;
545 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
546 int channel;
547 bus_size_t cmdsize, ctlsize;
548
549 if (pciide_chipen(sc, pa) == 0)
550 return;
551
552 if (interface == 0) {
553 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
554 DEBUG_PROBE);
555 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
556 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
557 }
558
559 aprint_normal("%s: bus-master DMA support present",
560 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
561 pciide_mapreg_dma(sc, pa);
562 aprint_normal("\n");
563
564 if (sc->sc_dma_ok) {
565 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
566 sc->sc_wdcdev.irqack = pciide_irqack;
567 }
568 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
569 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
570 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
571
572 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
573 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
574 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
575 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
576
577 wdc_allocate_regs(&sc->sc_wdcdev);
578
579 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
580 channel++) {
581 cp = &sc->pciide_channels[channel];
582 if (pciide_chansetup(sc, channel, interface) == 0)
583 continue;
584 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
585 pciide_pci_intr);
586 }
587 }
588