viaide.c revision 1.24.2.4 1 /* $NetBSD: viaide.c,v 1.24.2.4 2006/08/03 12:20:09 tron Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35
36 #include <dev/pci/pcivar.h>
37 #include <dev/pci/pcidevs.h>
38 #include <dev/pci/pciidereg.h>
39 #include <dev/pci/pciidevar.h>
40 #include <dev/pci/pciide_apollo_reg.h>
41
42 static int via_pcib_match(struct pci_attach_args *);
43 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
44 static void via_sata_chip_map(struct pciide_softc *,
45 struct pci_attach_args *);
46 static void via_setup_channel(struct ata_channel *);
47
48 static int viaide_match(struct device *, struct cfdata *, void *);
49 static void viaide_attach(struct device *, struct device *, void *);
50 static const struct pciide_product_desc *
51 viaide_lookup(pcireg_t);
52
53 CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
54 viaide_match, viaide_attach, NULL, NULL);
55
56 static const struct pciide_product_desc pciide_amd_products[] = {
57 { PCI_PRODUCT_AMD_PBC756_IDE,
58 0,
59 "Advanced Micro Devices AMD756 IDE Controller",
60 via_chip_map
61 },
62 { PCI_PRODUCT_AMD_PBC766_IDE,
63 0,
64 "Advanced Micro Devices AMD766 IDE Controller",
65 via_chip_map
66 },
67 { PCI_PRODUCT_AMD_PBC768_IDE,
68 0,
69 "Advanced Micro Devices AMD768 IDE Controller",
70 via_chip_map
71 },
72 { PCI_PRODUCT_AMD_PBC8111_IDE,
73 0,
74 "Advanced Micro Devices AMD8111 IDE Controller",
75 via_chip_map
76 },
77 { 0,
78 0,
79 NULL,
80 NULL
81 }
82 };
83
84 static const struct pciide_product_desc pciide_nvidia_products[] = {
85 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
86 0,
87 "NVIDIA nForce IDE Controller",
88 via_chip_map
89 },
90 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
91 0,
92 "NVIDIA nForce2 IDE Controller",
93 via_chip_map
94 },
95 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
96 0,
97 "NVIDIA nForce2 Ultra 400 IDE Controller",
98 via_chip_map
99 },
100 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
101 0,
102 "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
103 via_sata_chip_map
104 },
105 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
106 0,
107 "NVIDIA nForce3 IDE Controller",
108 via_chip_map
109 },
110 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
111 0,
112 "NVIDIA nForce3 250 IDE Controller",
113 via_chip_map
114 },
115 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
116 0,
117 "NVIDIA nForce3 250 Serial ATA Controller",
118 via_sata_chip_map
119 },
120 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
121 0,
122 "NVIDIA nForce3 250 Serial ATA Controller",
123 via_sata_chip_map
124 },
125 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
126 0,
127 "NVIDIA nForce4 IDE Controller",
128 via_chip_map
129 },
130 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
131 0,
132 "NVIDIA nForce4 Serial ATA Controller",
133 via_sata_chip_map
134 },
135 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
136 0,
137 "NVIDIA nForce4 Serial ATA Controller",
138 via_sata_chip_map
139 },
140 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
141 0,
142 "NVIDIA nForce430 IDE Controller",
143 via_chip_map
144 },
145 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
146 0,
147 "NVIDIA nForce430 Serial ATA Controller",
148 via_sata_chip_map
149 },
150 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
151 0,
152 "NVIDIA nForce430 Serial ATA Controller",
153 via_sata_chip_map
154 },
155 { 0,
156 0,
157 NULL,
158 NULL
159 }
160 };
161
162 static const struct pciide_product_desc pciide_via_products[] = {
163 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
164 0,
165 NULL,
166 via_chip_map,
167 },
168 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
169 0,
170 NULL,
171 via_chip_map,
172 },
173 { PCI_PRODUCT_VIATECH_VT6421_RAID,
174 0,
175 "VIA Technologies VT6421 Serial RAID Controller",
176 via_sata_chip_map,
177 },
178 { PCI_PRODUCT_VIATECH_VT8237_SATA,
179 0,
180 "VIA Technologies VT8237 SATA Controller",
181 via_sata_chip_map,
182 },
183 { PCI_PRODUCT_VIATECH_VT8237R_SATA,
184 0,
185 "VIA Technologies VT8237R SATA Controller",
186 via_sata_chip_map,
187 },
188 { 0,
189 0,
190 NULL,
191 NULL
192 }
193 };
194
195 static const struct pciide_product_desc *
196 viaide_lookup(pcireg_t id)
197 {
198
199 switch (PCI_VENDOR(id)) {
200 case PCI_VENDOR_VIATECH:
201 return (pciide_lookup_product(id, pciide_via_products));
202
203 case PCI_VENDOR_AMD:
204 return (pciide_lookup_product(id, pciide_amd_products));
205
206 case PCI_VENDOR_NVIDIA:
207 return (pciide_lookup_product(id, pciide_nvidia_products));
208 }
209 return (NULL);
210 }
211
212 static int
213 viaide_match(struct device *parent, struct cfdata *match, void *aux)
214 {
215 struct pci_attach_args *pa = aux;
216
217 if (viaide_lookup(pa->pa_id) != NULL)
218 return (2);
219 return (0);
220 }
221
222 static void
223 viaide_attach(struct device *parent, struct device *self, void *aux)
224 {
225 struct pci_attach_args *pa = aux;
226 struct pciide_softc *sc = (struct pciide_softc *)self;
227 const struct pciide_product_desc *pp;
228
229 pp = viaide_lookup(pa->pa_id);
230 if (pp == NULL)
231 panic("viaide_attach");
232 pciide_common_attach(sc, pa, pp);
233 }
234
235 static int
236 via_pcib_match(struct pci_attach_args *pa)
237 {
238 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
239 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
240 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
241 return (1);
242 return 0;
243 }
244
245 static void
246 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
247 {
248 struct pciide_channel *cp;
249 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
250 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
251 int channel;
252 u_int32_t ideconf;
253 bus_size_t cmdsize, ctlsize;
254 pcireg_t pcib_id, pcib_class;
255 struct pci_attach_args pcib_pa;
256
257 if (pciide_chipen(sc, pa) == 0)
258 return;
259
260 switch (vendor) {
261 case PCI_VENDOR_VIATECH:
262 /*
263 * get a PCI tag for the ISA bridge.
264 */
265 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
266 goto unknown;
267 pcib_id = pcib_pa.pa_id;
268 pcib_class = pcib_pa.pa_class;
269 aprint_normal("%s: VIA Technologies ",
270 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
271 switch (PCI_PRODUCT(pcib_id)) {
272 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
273 aprint_normal("VT82C586 (Apollo VP) ");
274 if(PCI_REVISION(pcib_class) >= 0x02) {
275 aprint_normal("ATA33 controller\n");
276 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
277 } else {
278 aprint_normal("controller\n");
279 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
280 }
281 break;
282 case PCI_PRODUCT_VIATECH_VT82C596A:
283 aprint_normal("VT82C596A (Apollo Pro) ");
284 if (PCI_REVISION(pcib_class) >= 0x12) {
285 aprint_normal("ATA66 controller\n");
286 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
287 } else {
288 aprint_normal("ATA33 controller\n");
289 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
290 }
291 break;
292 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
293 aprint_normal("VT82C686A (Apollo KX133) ");
294 if (PCI_REVISION(pcib_class) >= 0x40) {
295 aprint_normal("ATA100 controller\n");
296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
297 } else {
298 aprint_normal("ATA66 controller\n");
299 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
300 }
301 break;
302 case PCI_PRODUCT_VIATECH_VT8231:
303 aprint_normal("VT8231 ATA100 controller\n");
304 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
305 break;
306 case PCI_PRODUCT_VIATECH_VT8233:
307 aprint_normal("VT8233 ATA100 controller\n");
308 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
309 break;
310 case PCI_PRODUCT_VIATECH_VT8233A:
311 aprint_normal("VT8233A ATA133 controller\n");
312 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
313 break;
314 case PCI_PRODUCT_VIATECH_VT8235:
315 aprint_normal("VT8235 ATA133 controller\n");
316 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
317 break;
318 case PCI_PRODUCT_VIATECH_VT8237:
319 aprint_normal("VT8237 ATA133 controller\n");
320 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
321 break;
322 default:
323 unknown:
324 aprint_normal("unknown VIA ATA controller\n");
325 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
326 }
327 sc->sc_apo_regbase = APO_VIA_REGBASE;
328 break;
329 case PCI_VENDOR_AMD:
330 switch (sc->sc_pp->ide_product) {
331 case PCI_PRODUCT_AMD_PBC8111_IDE:
332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
333 break;
334 case PCI_PRODUCT_AMD_PBC766_IDE:
335 case PCI_PRODUCT_AMD_PBC768_IDE:
336 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
337 break;
338 default:
339 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
340 }
341 sc->sc_apo_regbase = APO_AMD_REGBASE;
342 break;
343 case PCI_VENDOR_NVIDIA:
344 switch (sc->sc_pp->ide_product) {
345 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
346 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
347 break;
348 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
349 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
350 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
351 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
352 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
353 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
354 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
355 break;
356 }
357 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
358 break;
359 default:
360 panic("via_chip_map: unknown vendor");
361 }
362
363 aprint_normal("%s: bus-master DMA support present",
364 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
365 pciide_mapreg_dma(sc, pa);
366 aprint_normal("\n");
367 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
368 if (sc->sc_dma_ok) {
369 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
370 sc->sc_wdcdev.irqack = pciide_irqack;
371 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
372 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
373 }
374 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
375 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
376 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
377 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
378 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
379
380 wdc_allocate_regs(&sc->sc_wdcdev);
381
382 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
383 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
384 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
385 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
386 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
387 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
388 DEBUG_PROBE);
389
390 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
391 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
392 channel++) {
393 cp = &sc->pciide_channels[channel];
394 if (pciide_chansetup(sc, channel, interface) == 0)
395 continue;
396
397 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
398 aprint_normal("%s: %s channel ignored (disabled)\n",
399 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
400 cp->ata_channel.ch_flags |= ATACH_DISABLED;
401 continue;
402 }
403 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
404 pciide_pci_intr);
405 }
406 }
407
408 static void
409 via_setup_channel(struct ata_channel *chp)
410 {
411 u_int32_t udmatim_reg, datatim_reg;
412 u_int8_t idedma_ctl;
413 int mode, drive, s;
414 struct ata_drive_datas *drvp;
415 struct atac_softc *atac = chp->ch_atac;
416 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
417 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
418 #ifndef PCIIDE_AMD756_ENABLEDMA
419 int rev = PCI_REVISION(
420 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
421 #endif
422
423 idedma_ctl = 0;
424 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
425 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
426 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
427 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
428
429 /* setup DMA if needed */
430 pciide_channel_dma_setup(cp);
431
432 for (drive = 0; drive < 2; drive++) {
433 drvp = &chp->ch_drive[drive];
434 /* If no drive, skip */
435 if ((drvp->drive_flags & DRIVE) == 0)
436 continue;
437 /* add timing values, setup DMA if needed */
438 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
439 (drvp->drive_flags & DRIVE_UDMA) == 0)) {
440 mode = drvp->PIO_mode;
441 goto pio;
442 }
443 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
444 (drvp->drive_flags & DRIVE_UDMA)) {
445 /* use Ultra/DMA */
446 s = splbio();
447 drvp->drive_flags &= ~DRIVE_DMA;
448 splx(s);
449 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
450 APO_UDMA_EN_MTH(chp->ch_channel, drive);
451 switch (PCI_VENDOR(sc->sc_pci_id)) {
452 case PCI_VENDOR_VIATECH:
453 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
454 /* 8233a */
455 udmatim_reg |= APO_UDMA_TIME(
456 chp->ch_channel,
457 drive,
458 via_udma133_tim[drvp->UDMA_mode]);
459 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
460 /* 686b */
461 udmatim_reg |= APO_UDMA_TIME(
462 chp->ch_channel,
463 drive,
464 via_udma100_tim[drvp->UDMA_mode]);
465 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
466 /* 596b or 686a */
467 udmatim_reg |= APO_UDMA_CLK66(
468 chp->ch_channel);
469 udmatim_reg |= APO_UDMA_TIME(
470 chp->ch_channel,
471 drive,
472 via_udma66_tim[drvp->UDMA_mode]);
473 } else {
474 /* 596a or 586b */
475 udmatim_reg |= APO_UDMA_TIME(
476 chp->ch_channel,
477 drive,
478 via_udma33_tim[drvp->UDMA_mode]);
479 }
480 break;
481 case PCI_VENDOR_AMD:
482 case PCI_VENDOR_NVIDIA:
483 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
484 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
485 break;
486 }
487 /* can use PIO timings, MW DMA unused */
488 mode = drvp->PIO_mode;
489 } else {
490 /* use Multiword DMA, but only if revision is OK */
491 s = splbio();
492 drvp->drive_flags &= ~DRIVE_UDMA;
493 splx(s);
494 #ifndef PCIIDE_AMD756_ENABLEDMA
495 /*
496 * The workaround doesn't seem to be necessary
497 * with all drives, so it can be disabled by
498 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
499 * triggered.
500 */
501 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
502 sc->sc_pp->ide_product ==
503 PCI_PRODUCT_AMD_PBC756_IDE &&
504 AMD756_CHIPREV_DISABLEDMA(rev)) {
505 aprint_normal(
506 "%s:%d:%d: multi-word DMA disabled due "
507 "to chip revision\n",
508 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
509 chp->ch_channel, drive);
510 mode = drvp->PIO_mode;
511 s = splbio();
512 drvp->drive_flags &= ~DRIVE_DMA;
513 splx(s);
514 goto pio;
515 }
516 #endif
517 /* mode = min(pio, dma+2) */
518 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
519 mode = drvp->PIO_mode;
520 else
521 mode = drvp->DMA_mode + 2;
522 }
523 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
524
525 pio: /* setup PIO mode */
526 if (mode <= 2) {
527 drvp->DMA_mode = 0;
528 drvp->PIO_mode = 0;
529 mode = 0;
530 } else {
531 drvp->PIO_mode = mode;
532 drvp->DMA_mode = mode - 2;
533 }
534 datatim_reg |=
535 APO_DATATIM_PULSE(chp->ch_channel, drive,
536 apollo_pio_set[mode]) |
537 APO_DATATIM_RECOV(chp->ch_channel, drive,
538 apollo_pio_rec[mode]);
539 }
540 if (idedma_ctl != 0) {
541 /* Add software bits in status register */
542 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
543 idedma_ctl);
544 }
545 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
546 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
547 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
548 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
549 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
550 }
551
552 static void
553 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
554 {
555 struct pciide_channel *cp;
556 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
557 int channel;
558 bus_size_t cmdsize, ctlsize;
559
560 if (pciide_chipen(sc, pa) == 0)
561 return;
562
563 if (interface == 0) {
564 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
565 DEBUG_PROBE);
566 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
567 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
568 }
569
570 aprint_normal("%s: bus-master DMA support present",
571 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
572 pciide_mapreg_dma(sc, pa);
573 aprint_normal("\n");
574
575 if (sc->sc_dma_ok) {
576 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
577 sc->sc_wdcdev.irqack = pciide_irqack;
578 }
579 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
580 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
581 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
582
583 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
584 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
585 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
586 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
587
588 wdc_allocate_regs(&sc->sc_wdcdev);
589
590 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
591 channel++) {
592 cp = &sc->pciide_channels[channel];
593 if (pciide_chansetup(sc, channel, interface) == 0)
594 continue;
595 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
596 pciide_pci_intr);
597 }
598 }
599