viaide.c revision 1.25
1 /* $NetBSD: viaide.c,v 1.25 2005/05/24 05:25:15 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.25 2005/05/24 05:25:15 lukem Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_sata_chip_map(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_setup_channel(struct ata_channel *); 50 51 static int viaide_match(struct device *, struct cfdata *, void *); 52 static void viaide_attach(struct device *, struct device *, void *); 53 static const struct pciide_product_desc * 54 viaide_lookup(pcireg_t); 55 56 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 57 viaide_match, viaide_attach, NULL, NULL); 58 59 static const struct pciide_product_desc pciide_amd_products[] = { 60 { PCI_PRODUCT_AMD_PBC756_IDE, 61 0, 62 "Advanced Micro Devices AMD756 IDE Controller", 63 via_chip_map 64 }, 65 { PCI_PRODUCT_AMD_PBC766_IDE, 66 0, 67 "Advanced Micro Devices AMD766 IDE Controller", 68 via_chip_map 69 }, 70 { PCI_PRODUCT_AMD_PBC768_IDE, 71 0, 72 "Advanced Micro Devices AMD768 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC8111_IDE, 76 0, 77 "Advanced Micro Devices AMD8111 IDE Controller", 78 via_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static const struct pciide_product_desc pciide_nvidia_products[] = { 88 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 89 0, 90 "NVIDIA nForce IDE Controller", 91 via_chip_map 92 }, 93 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 94 0, 95 "NVIDIA nForce2 IDE Controller", 96 via_chip_map 97 }, 98 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 99 0, 100 "NVIDIA nForce2 Ultra 400 IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 104 0, 105 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 106 via_sata_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 109 0, 110 "NVIDIA nForce3 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 114 0, 115 "NVIDIA nForce3 250 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 119 0, 120 "NVIDIA nForce3 250 Serial ATA Controller", 121 via_sata_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 124 0, 125 "NVIDIA nForce4 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 129 0, 130 "NVIDIA nForce4 Serial ATA Controller", 131 via_sata_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 134 0, 135 "NVIDIA nForce4 Serial ATA Controller", 136 via_sata_chip_map 137 }, 138 { 0, 139 0, 140 NULL, 141 NULL 142 } 143 }; 144 145 static const struct pciide_product_desc pciide_via_products[] = { 146 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 147 0, 148 NULL, 149 via_chip_map, 150 }, 151 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 152 0, 153 NULL, 154 via_chip_map, 155 }, 156 { PCI_PRODUCT_VIATECH_VT6421_RAID, 157 0, 158 "VIA Technologies VT6421 Serial RAID Controller", 159 via_sata_chip_map, 160 }, 161 { PCI_PRODUCT_VIATECH_VT8237_SATA, 162 0, 163 "VIA Technologies VT8237 SATA Controller", 164 via_sata_chip_map, 165 }, 166 { 0, 167 0, 168 NULL, 169 NULL 170 } 171 }; 172 173 static const struct pciide_product_desc * 174 viaide_lookup(pcireg_t id) 175 { 176 177 switch (PCI_VENDOR(id)) { 178 case PCI_VENDOR_VIATECH: 179 return (pciide_lookup_product(id, pciide_via_products)); 180 181 case PCI_VENDOR_AMD: 182 return (pciide_lookup_product(id, pciide_amd_products)); 183 184 case PCI_VENDOR_NVIDIA: 185 return (pciide_lookup_product(id, pciide_nvidia_products)); 186 } 187 return (NULL); 188 } 189 190 static int 191 viaide_match(struct device *parent, struct cfdata *match, void *aux) 192 { 193 struct pci_attach_args *pa = aux; 194 195 if (viaide_lookup(pa->pa_id) != NULL) 196 return (2); 197 return (0); 198 } 199 200 static void 201 viaide_attach(struct device *parent, struct device *self, void *aux) 202 { 203 struct pci_attach_args *pa = aux; 204 struct pciide_softc *sc = (struct pciide_softc *)self; 205 const struct pciide_product_desc *pp; 206 207 pp = viaide_lookup(pa->pa_id); 208 if (pp == NULL) 209 panic("viaide_attach"); 210 pciide_common_attach(sc, pa, pp); 211 } 212 213 static int 214 via_pcib_match(struct pci_attach_args *pa) 215 { 216 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 217 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 218 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 219 return (1); 220 return 0; 221 } 222 223 static void 224 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 225 { 226 struct pciide_channel *cp; 227 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 228 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 229 int channel; 230 u_int32_t ideconf; 231 bus_size_t cmdsize, ctlsize; 232 pcireg_t pcib_id, pcib_class; 233 struct pci_attach_args pcib_pa; 234 235 if (pciide_chipen(sc, pa) == 0) 236 return; 237 238 switch (vendor) { 239 case PCI_VENDOR_VIATECH: 240 /* 241 * get a PCI tag for the ISA bridge. 242 */ 243 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 244 goto unknown; 245 pcib_id = pcib_pa.pa_id; 246 pcib_class = pcib_pa.pa_class; 247 aprint_normal("%s: VIA Technologies ", 248 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 249 switch (PCI_PRODUCT(pcib_id)) { 250 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 251 aprint_normal("VT82C586 (Apollo VP) "); 252 if(PCI_REVISION(pcib_class) >= 0x02) { 253 aprint_normal("ATA33 controller\n"); 254 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 255 } else { 256 aprint_normal("controller\n"); 257 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 258 } 259 break; 260 case PCI_PRODUCT_VIATECH_VT82C596A: 261 aprint_normal("VT82C596A (Apollo Pro) "); 262 if (PCI_REVISION(pcib_class) >= 0x12) { 263 aprint_normal("ATA66 controller\n"); 264 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 265 } else { 266 aprint_normal("ATA33 controller\n"); 267 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 268 } 269 break; 270 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 271 aprint_normal("VT82C686A (Apollo KX133) "); 272 if (PCI_REVISION(pcib_class) >= 0x40) { 273 aprint_normal("ATA100 controller\n"); 274 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 275 } else { 276 aprint_normal("ATA66 controller\n"); 277 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 278 } 279 break; 280 case PCI_PRODUCT_VIATECH_VT8231: 281 aprint_normal("VT8231 ATA100 controller\n"); 282 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 283 break; 284 case PCI_PRODUCT_VIATECH_VT8233: 285 aprint_normal("VT8233 ATA100 controller\n"); 286 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 287 break; 288 case PCI_PRODUCT_VIATECH_VT8233A: 289 aprint_normal("VT8233A ATA133 controller\n"); 290 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 291 break; 292 case PCI_PRODUCT_VIATECH_VT8235: 293 aprint_normal("VT8235 ATA133 controller\n"); 294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 295 break; 296 case PCI_PRODUCT_VIATECH_VT8237: 297 aprint_normal("VT8237 ATA133 controller\n"); 298 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 299 break; 300 default: 301 unknown: 302 aprint_normal("unknown VIA ATA controller\n"); 303 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 304 } 305 sc->sc_apo_regbase = APO_VIA_REGBASE; 306 break; 307 case PCI_VENDOR_AMD: 308 switch (sc->sc_pp->ide_product) { 309 case PCI_PRODUCT_AMD_PBC8111_IDE: 310 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 311 break; 312 case PCI_PRODUCT_AMD_PBC766_IDE: 313 case PCI_PRODUCT_AMD_PBC768_IDE: 314 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 315 break; 316 default: 317 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 318 } 319 sc->sc_apo_regbase = APO_AMD_REGBASE; 320 break; 321 case PCI_VENDOR_NVIDIA: 322 switch (sc->sc_pp->ide_product) { 323 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 324 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 325 break; 326 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 327 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 328 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 329 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 330 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 331 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 332 break; 333 } 334 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 335 break; 336 default: 337 panic("via_chip_map: unknown vendor"); 338 } 339 340 aprint_normal("%s: bus-master DMA support present", 341 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 342 pciide_mapreg_dma(sc, pa); 343 aprint_normal("\n"); 344 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 345 if (sc->sc_dma_ok) { 346 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 347 sc->sc_wdcdev.irqack = pciide_irqack; 348 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 349 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 350 } 351 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 352 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 353 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 354 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 355 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 356 357 wdc_allocate_regs(&sc->sc_wdcdev); 358 359 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 360 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 361 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 362 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 363 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 364 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 365 DEBUG_PROBE); 366 367 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 368 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 369 channel++) { 370 cp = &sc->pciide_channels[channel]; 371 if (pciide_chansetup(sc, channel, interface) == 0) 372 continue; 373 374 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 375 aprint_normal("%s: %s channel ignored (disabled)\n", 376 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 377 cp->ata_channel.ch_flags |= ATACH_DISABLED; 378 continue; 379 } 380 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 381 pciide_pci_intr); 382 } 383 } 384 385 static void 386 via_setup_channel(struct ata_channel *chp) 387 { 388 u_int32_t udmatim_reg, datatim_reg; 389 u_int8_t idedma_ctl; 390 int mode, drive, s; 391 struct ata_drive_datas *drvp; 392 struct atac_softc *atac = chp->ch_atac; 393 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 394 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 395 #ifndef PCIIDE_AMD756_ENABLEDMA 396 int rev = PCI_REVISION( 397 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 398 #endif 399 400 idedma_ctl = 0; 401 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 402 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 403 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 404 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 405 406 /* setup DMA if needed */ 407 pciide_channel_dma_setup(cp); 408 409 for (drive = 0; drive < 2; drive++) { 410 drvp = &chp->ch_drive[drive]; 411 /* If no drive, skip */ 412 if ((drvp->drive_flags & DRIVE) == 0) 413 continue; 414 /* add timing values, setup DMA if needed */ 415 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 416 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 417 mode = drvp->PIO_mode; 418 goto pio; 419 } 420 if ((atac->atac_cap & ATAC_CAP_UDMA) && 421 (drvp->drive_flags & DRIVE_UDMA)) { 422 /* use Ultra/DMA */ 423 s = splbio(); 424 drvp->drive_flags &= ~DRIVE_DMA; 425 splx(s); 426 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 427 APO_UDMA_EN_MTH(chp->ch_channel, drive); 428 switch (PCI_VENDOR(sc->sc_pci_id)) { 429 case PCI_VENDOR_VIATECH: 430 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 431 /* 8233a */ 432 udmatim_reg |= APO_UDMA_TIME( 433 chp->ch_channel, 434 drive, 435 via_udma133_tim[drvp->UDMA_mode]); 436 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 437 /* 686b */ 438 udmatim_reg |= APO_UDMA_TIME( 439 chp->ch_channel, 440 drive, 441 via_udma100_tim[drvp->UDMA_mode]); 442 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 443 /* 596b or 686a */ 444 udmatim_reg |= APO_UDMA_CLK66( 445 chp->ch_channel); 446 udmatim_reg |= APO_UDMA_TIME( 447 chp->ch_channel, 448 drive, 449 via_udma66_tim[drvp->UDMA_mode]); 450 } else { 451 /* 596a or 586b */ 452 udmatim_reg |= APO_UDMA_TIME( 453 chp->ch_channel, 454 drive, 455 via_udma33_tim[drvp->UDMA_mode]); 456 } 457 break; 458 case PCI_VENDOR_AMD: 459 case PCI_VENDOR_NVIDIA: 460 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 461 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 462 break; 463 } 464 /* can use PIO timings, MW DMA unused */ 465 mode = drvp->PIO_mode; 466 } else { 467 /* use Multiword DMA, but only if revision is OK */ 468 s = splbio(); 469 drvp->drive_flags &= ~DRIVE_UDMA; 470 splx(s); 471 #ifndef PCIIDE_AMD756_ENABLEDMA 472 /* 473 * The workaround doesn't seem to be necessary 474 * with all drives, so it can be disabled by 475 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 476 * triggered. 477 */ 478 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 479 sc->sc_pp->ide_product == 480 PCI_PRODUCT_AMD_PBC756_IDE && 481 AMD756_CHIPREV_DISABLEDMA(rev)) { 482 aprint_normal( 483 "%s:%d:%d: multi-word DMA disabled due " 484 "to chip revision\n", 485 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 486 chp->ch_channel, drive); 487 mode = drvp->PIO_mode; 488 s = splbio(); 489 drvp->drive_flags &= ~DRIVE_DMA; 490 splx(s); 491 goto pio; 492 } 493 #endif 494 /* mode = min(pio, dma+2) */ 495 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 496 mode = drvp->PIO_mode; 497 else 498 mode = drvp->DMA_mode + 2; 499 } 500 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 501 502 pio: /* setup PIO mode */ 503 if (mode <= 2) { 504 drvp->DMA_mode = 0; 505 drvp->PIO_mode = 0; 506 mode = 0; 507 } else { 508 drvp->PIO_mode = mode; 509 drvp->DMA_mode = mode - 2; 510 } 511 datatim_reg |= 512 APO_DATATIM_PULSE(chp->ch_channel, drive, 513 apollo_pio_set[mode]) | 514 APO_DATATIM_RECOV(chp->ch_channel, drive, 515 apollo_pio_rec[mode]); 516 } 517 if (idedma_ctl != 0) { 518 /* Add software bits in status register */ 519 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 520 idedma_ctl); 521 } 522 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 523 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 524 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 525 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 526 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 527 } 528 529 static void 530 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 531 { 532 struct pciide_channel *cp; 533 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 534 int channel; 535 bus_size_t cmdsize, ctlsize; 536 537 if (pciide_chipen(sc, pa) == 0) 538 return; 539 540 if (interface == 0) { 541 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 542 DEBUG_PROBE); 543 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 544 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 545 } 546 547 aprint_normal("%s: bus-master DMA support present", 548 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 549 pciide_mapreg_dma(sc, pa); 550 aprint_normal("\n"); 551 552 if (sc->sc_dma_ok) { 553 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 554 sc->sc_wdcdev.irqack = pciide_irqack; 555 } 556 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 557 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 558 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 559 560 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 561 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 562 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 563 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 564 565 wdc_allocate_regs(&sc->sc_wdcdev); 566 567 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 568 channel++) { 569 cp = &sc->pciide_channels[channel]; 570 if (pciide_chansetup(sc, channel, interface) == 0) 571 continue; 572 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 573 pciide_pci_intr); 574 } 575 } 576
Indexes created Sun Oct 19 02:09:48 GMT 2025