viaide.c revision 1.25.2.1
1 /* $NetBSD: viaide.c,v 1.25.2.1 2006/06/21 15:05:07 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.25.2.1 2006/06/21 15:05:07 yamt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_sata_chip_map(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_setup_channel(struct ata_channel *); 50 51 static int viaide_match(struct device *, struct cfdata *, void *); 52 static void viaide_attach(struct device *, struct device *, void *); 53 static const struct pciide_product_desc * 54 viaide_lookup(pcireg_t); 55 56 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 57 viaide_match, viaide_attach, NULL, NULL); 58 59 static const struct pciide_product_desc pciide_amd_products[] = { 60 { PCI_PRODUCT_AMD_PBC756_IDE, 61 0, 62 "Advanced Micro Devices AMD756 IDE Controller", 63 via_chip_map 64 }, 65 { PCI_PRODUCT_AMD_PBC766_IDE, 66 0, 67 "Advanced Micro Devices AMD766 IDE Controller", 68 via_chip_map 69 }, 70 { PCI_PRODUCT_AMD_PBC768_IDE, 71 0, 72 "Advanced Micro Devices AMD768 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC8111_IDE, 76 0, 77 "Advanced Micro Devices AMD8111 IDE Controller", 78 via_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static const struct pciide_product_desc pciide_nvidia_products[] = { 88 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 89 0, 90 "NVIDIA nForce IDE Controller", 91 via_chip_map 92 }, 93 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 94 0, 95 "NVIDIA nForce2 IDE Controller", 96 via_chip_map 97 }, 98 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 99 0, 100 "NVIDIA nForce2 Ultra 400 IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 104 0, 105 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 106 via_sata_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 109 0, 110 "NVIDIA nForce3 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 114 0, 115 "NVIDIA nForce3 250 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 119 0, 120 "NVIDIA nForce3 250 Serial ATA Controller", 121 via_sata_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 124 0, 125 "NVIDIA nForce4 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 129 0, 130 "NVIDIA nForce4 Serial ATA Controller", 131 via_sata_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 134 0, 135 "NVIDIA nForce4 Serial ATA Controller", 136 via_sata_chip_map 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 139 0, 140 "NVIDIA nForce430 IDE Controller", 141 via_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 144 0, 145 "NVIDIA nForce430 Serial ATA Controller", 146 via_sata_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 149 0, 150 "NVIDIA nForce430 Serial ATA Controller", 151 via_sata_chip_map 152 }, 153 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 154 0, 155 "NVIDIA MCP04 IDE Controller", 156 via_chip_map 157 }, 158 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 159 0, 160 "NVIDIA MCP04 Serial ATA Controller", 161 via_sata_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 164 0, 165 "NVIDIA MCP04 Serial ATA Controller", 166 via_sata_chip_map 167 }, 168 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 169 0, 170 "NVIDIA MCP55 IDE Controller", 171 via_chip_map 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 174 0, 175 "NVIDIA MCP55 Serial ATA Controller", 176 via_sata_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 179 0, 180 "NVIDIA MCP55 Serial ATA Controller", 181 via_sata_chip_map 182 }, 183 { 0, 184 0, 185 NULL, 186 NULL 187 } 188 }; 189 190 static const struct pciide_product_desc pciide_via_products[] = { 191 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 192 0, 193 NULL, 194 via_chip_map, 195 }, 196 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 197 0, 198 NULL, 199 via_chip_map, 200 }, 201 { PCI_PRODUCT_VIATECH_VT6421_RAID, 202 0, 203 "VIA Technologies VT6421 Serial RAID Controller", 204 via_sata_chip_map, 205 }, 206 { PCI_PRODUCT_VIATECH_VT8237_SATA, 207 0, 208 "VIA Technologies VT8237 SATA Controller", 209 via_sata_chip_map, 210 }, 211 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 212 0, 213 "VIA Technologies VT8237R SATA Controller", 214 via_sata_chip_map, 215 }, 216 { 0, 217 0, 218 NULL, 219 NULL 220 } 221 }; 222 223 static const struct pciide_product_desc * 224 viaide_lookup(pcireg_t id) 225 { 226 227 switch (PCI_VENDOR(id)) { 228 case PCI_VENDOR_VIATECH: 229 return (pciide_lookup_product(id, pciide_via_products)); 230 231 case PCI_VENDOR_AMD: 232 return (pciide_lookup_product(id, pciide_amd_products)); 233 234 case PCI_VENDOR_NVIDIA: 235 return (pciide_lookup_product(id, pciide_nvidia_products)); 236 } 237 return (NULL); 238 } 239 240 static int 241 viaide_match(struct device *parent, struct cfdata *match, void *aux) 242 { 243 struct pci_attach_args *pa = aux; 244 245 if (viaide_lookup(pa->pa_id) != NULL) 246 return (2); 247 return (0); 248 } 249 250 static void 251 viaide_attach(struct device *parent, struct device *self, void *aux) 252 { 253 struct pci_attach_args *pa = aux; 254 struct pciide_softc *sc = (struct pciide_softc *)self; 255 const struct pciide_product_desc *pp; 256 257 pp = viaide_lookup(pa->pa_id); 258 if (pp == NULL) 259 panic("viaide_attach"); 260 pciide_common_attach(sc, pa, pp); 261 } 262 263 static int 264 via_pcib_match(struct pci_attach_args *pa) 265 { 266 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 267 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 268 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 269 return (1); 270 return 0; 271 } 272 273 static void 274 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 275 { 276 struct pciide_channel *cp; 277 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 278 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 279 int channel; 280 u_int32_t ideconf; 281 bus_size_t cmdsize, ctlsize; 282 pcireg_t pcib_id, pcib_class; 283 struct pci_attach_args pcib_pa; 284 285 if (pciide_chipen(sc, pa) == 0) 286 return; 287 288 switch (vendor) { 289 case PCI_VENDOR_VIATECH: 290 /* 291 * get a PCI tag for the ISA bridge. 292 */ 293 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 294 goto unknown; 295 pcib_id = pcib_pa.pa_id; 296 pcib_class = pcib_pa.pa_class; 297 aprint_normal("%s: VIA Technologies ", 298 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 299 switch (PCI_PRODUCT(pcib_id)) { 300 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 301 aprint_normal("VT82C586 (Apollo VP) "); 302 if(PCI_REVISION(pcib_class) >= 0x02) { 303 aprint_normal("ATA33 controller\n"); 304 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 305 } else { 306 aprint_normal("controller\n"); 307 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 308 } 309 break; 310 case PCI_PRODUCT_VIATECH_VT82C596A: 311 aprint_normal("VT82C596A (Apollo Pro) "); 312 if (PCI_REVISION(pcib_class) >= 0x12) { 313 aprint_normal("ATA66 controller\n"); 314 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 315 } else { 316 aprint_normal("ATA33 controller\n"); 317 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 318 } 319 break; 320 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 321 aprint_normal("VT82C686A (Apollo KX133) "); 322 if (PCI_REVISION(pcib_class) >= 0x40) { 323 aprint_normal("ATA100 controller\n"); 324 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 325 } else { 326 aprint_normal("ATA66 controller\n"); 327 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 328 } 329 break; 330 case PCI_PRODUCT_VIATECH_VT8231: 331 aprint_normal("VT8231 ATA100 controller\n"); 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 333 break; 334 case PCI_PRODUCT_VIATECH_VT8233: 335 aprint_normal("VT8233 ATA100 controller\n"); 336 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 337 break; 338 case PCI_PRODUCT_VIATECH_VT8233A: 339 aprint_normal("VT8233A ATA133 controller\n"); 340 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 341 break; 342 case PCI_PRODUCT_VIATECH_VT8235: 343 aprint_normal("VT8235 ATA133 controller\n"); 344 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 345 break; 346 case PCI_PRODUCT_VIATECH_VT8237: 347 aprint_normal("VT8237 ATA133 controller\n"); 348 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 349 break; 350 default: 351 unknown: 352 aprint_normal("unknown VIA ATA controller\n"); 353 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 354 } 355 sc->sc_apo_regbase = APO_VIA_REGBASE; 356 break; 357 case PCI_VENDOR_AMD: 358 switch (sc->sc_pp->ide_product) { 359 case PCI_PRODUCT_AMD_PBC8111_IDE: 360 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 361 break; 362 case PCI_PRODUCT_AMD_PBC766_IDE: 363 case PCI_PRODUCT_AMD_PBC768_IDE: 364 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 365 break; 366 default: 367 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 368 } 369 sc->sc_apo_regbase = APO_AMD_REGBASE; 370 break; 371 case PCI_VENDOR_NVIDIA: 372 switch (sc->sc_pp->ide_product) { 373 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 374 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 375 break; 376 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 377 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 378 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 379 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 380 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 381 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 382 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 383 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 384 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 385 break; 386 } 387 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 388 break; 389 default: 390 panic("via_chip_map: unknown vendor"); 391 } 392 393 aprint_normal("%s: bus-master DMA support present", 394 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 395 pciide_mapreg_dma(sc, pa); 396 aprint_normal("\n"); 397 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 398 if (sc->sc_dma_ok) { 399 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 400 sc->sc_wdcdev.irqack = pciide_irqack; 401 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 402 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 403 } 404 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 405 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 406 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 407 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 408 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 409 410 wdc_allocate_regs(&sc->sc_wdcdev); 411 412 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 413 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 414 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 415 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 416 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 417 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 418 DEBUG_PROBE); 419 420 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 421 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 422 channel++) { 423 cp = &sc->pciide_channels[channel]; 424 if (pciide_chansetup(sc, channel, interface) == 0) 425 continue; 426 427 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 428 aprint_normal("%s: %s channel ignored (disabled)\n", 429 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 430 cp->ata_channel.ch_flags |= ATACH_DISABLED; 431 continue; 432 } 433 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 434 pciide_pci_intr); 435 } 436 } 437 438 static void 439 via_setup_channel(struct ata_channel *chp) 440 { 441 u_int32_t udmatim_reg, datatim_reg; 442 u_int8_t idedma_ctl; 443 int mode, drive, s; 444 struct ata_drive_datas *drvp; 445 struct atac_softc *atac = chp->ch_atac; 446 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 447 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 448 #ifndef PCIIDE_AMD756_ENABLEDMA 449 int rev = PCI_REVISION( 450 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 451 #endif 452 453 idedma_ctl = 0; 454 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 455 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 456 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 457 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 458 459 /* setup DMA if needed */ 460 pciide_channel_dma_setup(cp); 461 462 for (drive = 0; drive < 2; drive++) { 463 drvp = &chp->ch_drive[drive]; 464 /* If no drive, skip */ 465 if ((drvp->drive_flags & DRIVE) == 0) 466 continue; 467 /* add timing values, setup DMA if needed */ 468 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 469 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 470 mode = drvp->PIO_mode; 471 goto pio; 472 } 473 if ((atac->atac_cap & ATAC_CAP_UDMA) && 474 (drvp->drive_flags & DRIVE_UDMA)) { 475 /* use Ultra/DMA */ 476 s = splbio(); 477 drvp->drive_flags &= ~DRIVE_DMA; 478 splx(s); 479 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 480 APO_UDMA_EN_MTH(chp->ch_channel, drive); 481 switch (PCI_VENDOR(sc->sc_pci_id)) { 482 case PCI_VENDOR_VIATECH: 483 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 484 /* 8233a */ 485 udmatim_reg |= APO_UDMA_TIME( 486 chp->ch_channel, 487 drive, 488 via_udma133_tim[drvp->UDMA_mode]); 489 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 490 /* 686b */ 491 udmatim_reg |= APO_UDMA_TIME( 492 chp->ch_channel, 493 drive, 494 via_udma100_tim[drvp->UDMA_mode]); 495 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 496 /* 596b or 686a */ 497 udmatim_reg |= APO_UDMA_CLK66( 498 chp->ch_channel); 499 udmatim_reg |= APO_UDMA_TIME( 500 chp->ch_channel, 501 drive, 502 via_udma66_tim[drvp->UDMA_mode]); 503 } else { 504 /* 596a or 586b */ 505 udmatim_reg |= APO_UDMA_TIME( 506 chp->ch_channel, 507 drive, 508 via_udma33_tim[drvp->UDMA_mode]); 509 } 510 break; 511 case PCI_VENDOR_AMD: 512 case PCI_VENDOR_NVIDIA: 513 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 514 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 515 break; 516 } 517 /* can use PIO timings, MW DMA unused */ 518 mode = drvp->PIO_mode; 519 } else { 520 /* use Multiword DMA, but only if revision is OK */ 521 s = splbio(); 522 drvp->drive_flags &= ~DRIVE_UDMA; 523 splx(s); 524 #ifndef PCIIDE_AMD756_ENABLEDMA 525 /* 526 * The workaround doesn't seem to be necessary 527 * with all drives, so it can be disabled by 528 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 529 * triggered. 530 */ 531 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 532 sc->sc_pp->ide_product == 533 PCI_PRODUCT_AMD_PBC756_IDE && 534 AMD756_CHIPREV_DISABLEDMA(rev)) { 535 aprint_normal( 536 "%s:%d:%d: multi-word DMA disabled due " 537 "to chip revision\n", 538 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 539 chp->ch_channel, drive); 540 mode = drvp->PIO_mode; 541 s = splbio(); 542 drvp->drive_flags &= ~DRIVE_DMA; 543 splx(s); 544 goto pio; 545 } 546 #endif 547 /* mode = min(pio, dma+2) */ 548 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 549 mode = drvp->PIO_mode; 550 else 551 mode = drvp->DMA_mode + 2; 552 } 553 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 554 555 pio: /* setup PIO mode */ 556 if (mode <= 2) { 557 drvp->DMA_mode = 0; 558 drvp->PIO_mode = 0; 559 mode = 0; 560 } else { 561 drvp->PIO_mode = mode; 562 drvp->DMA_mode = mode - 2; 563 } 564 datatim_reg |= 565 APO_DATATIM_PULSE(chp->ch_channel, drive, 566 apollo_pio_set[mode]) | 567 APO_DATATIM_RECOV(chp->ch_channel, drive, 568 apollo_pio_rec[mode]); 569 } 570 if (idedma_ctl != 0) { 571 /* Add software bits in status register */ 572 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 573 idedma_ctl); 574 } 575 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 576 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 577 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 578 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 579 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 580 } 581 582 static void 583 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 584 { 585 struct pciide_channel *cp; 586 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 587 int channel; 588 bus_size_t cmdsize, ctlsize; 589 590 if (pciide_chipen(sc, pa) == 0) 591 return; 592 593 if (interface == 0) { 594 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 595 DEBUG_PROBE); 596 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 597 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 598 } 599 600 aprint_normal("%s: bus-master DMA support present", 601 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 602 pciide_mapreg_dma(sc, pa); 603 aprint_normal("\n"); 604 605 if (sc->sc_dma_ok) { 606 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 607 sc->sc_wdcdev.irqack = pciide_irqack; 608 } 609 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 610 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 611 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 612 613 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 614 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 615 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 616 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 617 618 wdc_allocate_regs(&sc->sc_wdcdev); 619 620 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 621 channel++) { 622 cp = &sc->pciide_channels[channel]; 623 if (pciide_chansetup(sc, channel, interface) == 0) 624 continue; 625 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 626 pciide_pci_intr); 627 } 628 } 629
Indexes created Sun Oct 19 18:09:56 GMT 2025