viaide.c revision 1.25.2.5
1 /* $NetBSD: viaide.c,v 1.25.2.5 2007/10/27 11:33:35 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.25.2.5 2007/10/27 11:33:35 yamt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_AMD_CS5536_IDE, 91 0, 92 "Advanced Micro Devices CS5536 IDE Controller", 93 via_chip_map 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static const struct pciide_product_desc pciide_nvidia_products[] = { 103 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 104 0, 105 "NVIDIA nForce IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 109 0, 110 "NVIDIA nForce2 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 114 0, 115 "NVIDIA nForce2 Ultra 400 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 119 0, 120 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 121 via_sata_chip_map_6 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 124 0, 125 "NVIDIA nForce3 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 129 0, 130 "NVIDIA nForce3 250 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 139 0, 140 "NVIDIA nForce3 250 Serial ATA Controller", 141 via_sata_chip_map_6 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 144 0, 145 "NVIDIA nForce4 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 154 0, 155 "NVIDIA nForce4 Serial ATA Controller", 156 via_sata_chip_map_6 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 159 0, 160 "NVIDIA nForce430 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 169 0, 170 "NVIDIA nForce430 Serial ATA Controller", 171 via_sata_chip_map_6 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 174 0, 175 "NVIDIA MCP04 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 184 0, 185 "NVIDIA MCP04 Serial ATA Controller", 186 via_sata_chip_map_6 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 189 0, 190 "NVIDIA MCP55 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 199 0, 200 "NVIDIA MCP55 Serial ATA Controller", 201 via_sata_chip_map_6 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 204 0, 205 "NVIDIA MCP61 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 209 0, 210 "NVIDIA MCP65 IDE Controller", 211 via_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 214 0, 215 "NVIDIA MCP61 Serial ATA Controller", 216 via_sata_chip_map_6 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 219 0, 220 "NVIDIA MCP61 Serial ATA Controller", 221 via_sata_chip_map_6 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 224 0, 225 "NVIDIA MCP61 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 234 0, 235 "NVIDIA MCP65 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 244 0, 245 "NVIDIA MCP65 Serial ATA Controller", 246 via_sata_chip_map_6 247 }, 248 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 249 0, 250 "NVIDIA MCP67 IDE Controller", 251 via_chip_map, 252 }, 253 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 254 0, 255 "NVIDIA MCP67 Serial ATA Controller", 256 via_sata_chip_map_6, 257 }, 258 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 259 0, 260 "NVIDIA MCP67 Serial ATA Controller", 261 via_sata_chip_map_6, 262 }, 263 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 264 0, 265 "NVIDIA MCP67 Serial ATA Controller", 266 via_sata_chip_map_6, 267 }, 268 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 269 0, 270 "NVIDIA MCP67 Serial ATA Controller", 271 via_sata_chip_map_6, 272 }, 273 { 0, 274 0, 275 NULL, 276 NULL 277 } 278 }; 279 280 static const struct pciide_product_desc pciide_via_products[] = { 281 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 282 0, 283 NULL, 284 via_chip_map, 285 }, 286 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 287 0, 288 NULL, 289 via_chip_map, 290 }, 291 { PCI_PRODUCT_VIATECH_CX700_IDE, 292 0, 293 NULL, 294 via_chip_map, 295 }, 296 { PCI_PRODUCT_VIATECH_VT6421_RAID, 297 0, 298 "VIA Technologies VT6421 Serial RAID Controller", 299 via_sata_chip_map_new, 300 }, 301 { PCI_PRODUCT_VIATECH_VT8237_SATA, 302 0, 303 "VIA Technologies VT8237 SATA Controller", 304 via_sata_chip_map_7, 305 }, 306 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 307 0, 308 "VIA Technologies VT8237A SATA Controller", 309 via_sata_chip_map_7, 310 }, 311 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 312 0, 313 "VIA Technologies VT8237R SATA Controller", 314 via_sata_chip_map_0, 315 }, 316 { 0, 317 0, 318 NULL, 319 NULL 320 } 321 }; 322 323 static const struct pciide_product_desc * 324 viaide_lookup(pcireg_t id) 325 { 326 327 switch (PCI_VENDOR(id)) { 328 case PCI_VENDOR_VIATECH: 329 return (pciide_lookup_product(id, pciide_via_products)); 330 331 case PCI_VENDOR_AMD: 332 return (pciide_lookup_product(id, pciide_amd_products)); 333 334 case PCI_VENDOR_NVIDIA: 335 return (pciide_lookup_product(id, pciide_nvidia_products)); 336 } 337 return (NULL); 338 } 339 340 static int 341 viaide_match(struct device *parent, struct cfdata *match, 342 void *aux) 343 { 344 struct pci_attach_args *pa = aux; 345 346 if (viaide_lookup(pa->pa_id) != NULL) 347 return (2); 348 return (0); 349 } 350 351 static void 352 viaide_attach(struct device *parent, struct device *self, void *aux) 353 { 354 struct pci_attach_args *pa = aux; 355 struct pciide_softc *sc = (struct pciide_softc *)self; 356 const struct pciide_product_desc *pp; 357 358 pp = viaide_lookup(pa->pa_id); 359 if (pp == NULL) 360 panic("viaide_attach"); 361 pciide_common_attach(sc, pa, pp); 362 } 363 364 static int 365 via_pcib_match(struct pci_attach_args *pa) 366 { 367 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 368 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 369 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 370 return (1); 371 return 0; 372 } 373 374 static void 375 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 376 { 377 struct pciide_channel *cp; 378 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 379 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 380 int channel; 381 u_int32_t ideconf; 382 bus_size_t cmdsize, ctlsize; 383 pcireg_t pcib_id, pcib_class; 384 struct pci_attach_args pcib_pa; 385 386 if (pciide_chipen(sc, pa) == 0) 387 return; 388 389 switch (vendor) { 390 case PCI_VENDOR_VIATECH: 391 /* 392 * get a PCI tag for the ISA bridge. 393 */ 394 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 395 goto unknown; 396 pcib_id = pcib_pa.pa_id; 397 pcib_class = pcib_pa.pa_class; 398 aprint_normal("%s: VIA Technologies ", 399 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 400 switch (PCI_PRODUCT(pcib_id)) { 401 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 402 aprint_normal("VT82C586 (Apollo VP) "); 403 if(PCI_REVISION(pcib_class) >= 0x02) { 404 aprint_normal("ATA33 controller\n"); 405 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 406 } else { 407 aprint_normal("controller\n"); 408 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 409 } 410 break; 411 case PCI_PRODUCT_VIATECH_VT82C596A: 412 aprint_normal("VT82C596A (Apollo Pro) "); 413 if (PCI_REVISION(pcib_class) >= 0x12) { 414 aprint_normal("ATA66 controller\n"); 415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 416 } else { 417 aprint_normal("ATA33 controller\n"); 418 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 419 } 420 break; 421 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 422 aprint_normal("VT82C686A (Apollo KX133) "); 423 if (PCI_REVISION(pcib_class) >= 0x40) { 424 aprint_normal("ATA100 controller\n"); 425 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 426 } else { 427 aprint_normal("ATA66 controller\n"); 428 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 429 } 430 break; 431 case PCI_PRODUCT_VIATECH_VT8231: 432 aprint_normal("VT8231 ATA100 controller\n"); 433 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 434 break; 435 case PCI_PRODUCT_VIATECH_VT8233: 436 aprint_normal("VT8233 ATA100 controller\n"); 437 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 438 break; 439 case PCI_PRODUCT_VIATECH_VT8233A: 440 aprint_normal("VT8233A ATA133 controller\n"); 441 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 442 break; 443 case PCI_PRODUCT_VIATECH_VT8235: 444 aprint_normal("VT8235 ATA133 controller\n"); 445 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 446 break; 447 case PCI_PRODUCT_VIATECH_VT8237: 448 aprint_normal("VT8237 ATA133 controller\n"); 449 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 450 break; 451 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 452 aprint_normal("VT8237A ATA133 controller\n"); 453 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 454 break; 455 case PCI_PRODUCT_VIATECH_CX700_IDE: 456 aprint_normal("CX700 ATA133 controller\n"); 457 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 458 break; 459 default: 460 unknown: 461 aprint_normal("unknown VIA ATA controller\n"); 462 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 463 } 464 sc->sc_apo_regbase = APO_VIA_REGBASE; 465 break; 466 case PCI_VENDOR_AMD: 467 switch (sc->sc_pp->ide_product) { 468 case PCI_PRODUCT_AMD_PBC8111_IDE: 469 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 470 break; 471 case PCI_PRODUCT_AMD_CS5536_IDE: 472 case PCI_PRODUCT_AMD_PBC766_IDE: 473 case PCI_PRODUCT_AMD_PBC768_IDE: 474 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 475 break; 476 default: 477 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 478 } 479 sc->sc_apo_regbase = APO_AMD_REGBASE; 480 break; 481 case PCI_VENDOR_NVIDIA: 482 switch (sc->sc_pp->ide_product) { 483 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 484 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 485 break; 486 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 487 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 488 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 489 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 490 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 491 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 492 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 493 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 494 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 495 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 496 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 497 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 498 break; 499 } 500 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 501 break; 502 default: 503 panic("via_chip_map: unknown vendor"); 504 } 505 506 aprint_verbose("%s: bus-master DMA support present", 507 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 508 pciide_mapreg_dma(sc, pa); 509 aprint_verbose("\n"); 510 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 511 if (sc->sc_dma_ok) { 512 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 513 sc->sc_wdcdev.irqack = pciide_irqack; 514 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 515 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 516 } 517 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 518 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 519 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 520 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 521 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 522 523 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 524 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 525 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 526 527 wdc_allocate_regs(&sc->sc_wdcdev); 528 529 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 530 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 531 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 532 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 533 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 534 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 535 DEBUG_PROBE); 536 537 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 538 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 539 channel++) { 540 cp = &sc->pciide_channels[channel]; 541 if (pciide_chansetup(sc, channel, interface) == 0) 542 continue; 543 544 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 545 aprint_normal("%s: %s channel ignored (disabled)\n", 546 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 547 cp->ata_channel.ch_flags |= ATACH_DISABLED; 548 continue; 549 } 550 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 551 pciide_pci_intr); 552 } 553 } 554 555 static void 556 via_setup_channel(struct ata_channel *chp) 557 { 558 u_int32_t udmatim_reg, datatim_reg; 559 u_int8_t idedma_ctl; 560 int mode, drive, s; 561 struct ata_drive_datas *drvp; 562 struct atac_softc *atac = chp->ch_atac; 563 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 564 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 565 #ifndef PCIIDE_AMD756_ENABLEDMA 566 int rev = PCI_REVISION( 567 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 568 #endif 569 570 idedma_ctl = 0; 571 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 572 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 573 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 574 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 575 576 /* setup DMA if needed */ 577 pciide_channel_dma_setup(cp); 578 579 for (drive = 0; drive < 2; drive++) { 580 drvp = &chp->ch_drive[drive]; 581 /* If no drive, skip */ 582 if ((drvp->drive_flags & DRIVE) == 0) 583 continue; 584 /* add timing values, setup DMA if needed */ 585 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 586 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 587 mode = drvp->PIO_mode; 588 goto pio; 589 } 590 if ((atac->atac_cap & ATAC_CAP_UDMA) && 591 (drvp->drive_flags & DRIVE_UDMA)) { 592 /* use Ultra/DMA */ 593 s = splbio(); 594 drvp->drive_flags &= ~DRIVE_DMA; 595 splx(s); 596 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 597 APO_UDMA_EN_MTH(chp->ch_channel, drive); 598 switch (PCI_VENDOR(sc->sc_pci_id)) { 599 case PCI_VENDOR_VIATECH: 600 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 601 /* 8233a */ 602 udmatim_reg |= APO_UDMA_TIME( 603 chp->ch_channel, 604 drive, 605 via_udma133_tim[drvp->UDMA_mode]); 606 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 607 /* 686b */ 608 udmatim_reg |= APO_UDMA_TIME( 609 chp->ch_channel, 610 drive, 611 via_udma100_tim[drvp->UDMA_mode]); 612 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 613 /* 596b or 686a */ 614 udmatim_reg |= APO_UDMA_CLK66( 615 chp->ch_channel); 616 udmatim_reg |= APO_UDMA_TIME( 617 chp->ch_channel, 618 drive, 619 via_udma66_tim[drvp->UDMA_mode]); 620 } else { 621 /* 596a or 586b */ 622 udmatim_reg |= APO_UDMA_TIME( 623 chp->ch_channel, 624 drive, 625 via_udma33_tim[drvp->UDMA_mode]); 626 } 627 break; 628 case PCI_VENDOR_AMD: 629 case PCI_VENDOR_NVIDIA: 630 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 631 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 632 break; 633 } 634 /* can use PIO timings, MW DMA unused */ 635 mode = drvp->PIO_mode; 636 } else { 637 /* use Multiword DMA, but only if revision is OK */ 638 s = splbio(); 639 drvp->drive_flags &= ~DRIVE_UDMA; 640 splx(s); 641 #ifndef PCIIDE_AMD756_ENABLEDMA 642 /* 643 * The workaround doesn't seem to be necessary 644 * with all drives, so it can be disabled by 645 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 646 * triggered. 647 */ 648 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 649 sc->sc_pp->ide_product == 650 PCI_PRODUCT_AMD_PBC756_IDE && 651 AMD756_CHIPREV_DISABLEDMA(rev)) { 652 aprint_normal( 653 "%s:%d:%d: multi-word DMA disabled due " 654 "to chip revision\n", 655 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 656 chp->ch_channel, drive); 657 mode = drvp->PIO_mode; 658 s = splbio(); 659 drvp->drive_flags &= ~DRIVE_DMA; 660 splx(s); 661 goto pio; 662 } 663 #endif 664 /* mode = min(pio, dma+2) */ 665 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 666 mode = drvp->PIO_mode; 667 else 668 mode = drvp->DMA_mode + 2; 669 } 670 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 671 672 pio: /* setup PIO mode */ 673 if (mode <= 2) { 674 drvp->DMA_mode = 0; 675 drvp->PIO_mode = 0; 676 mode = 0; 677 } else { 678 drvp->PIO_mode = mode; 679 drvp->DMA_mode = mode - 2; 680 } 681 datatim_reg |= 682 APO_DATATIM_PULSE(chp->ch_channel, drive, 683 apollo_pio_set[mode]) | 684 APO_DATATIM_RECOV(chp->ch_channel, drive, 685 apollo_pio_rec[mode]); 686 } 687 if (idedma_ctl != 0) { 688 /* Add software bits in status register */ 689 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 690 idedma_ctl); 691 } 692 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 693 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 694 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 695 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 696 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 697 } 698 699 static int 700 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 701 { 702 bus_size_t satasize; 703 int maptype, ret; 704 705 if (pciide_chipen(sc, pa) == 0) 706 return 0; 707 708 aprint_verbose("%s: bus-master DMA support present", 709 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 710 pciide_mapreg_dma(sc, pa); 711 aprint_verbose("\n"); 712 713 if (sc->sc_dma_ok) { 714 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 715 sc->sc_wdcdev.irqack = pciide_irqack; 716 } 717 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 718 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 719 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 720 721 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 722 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 723 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 724 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 725 726 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 727 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 728 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 729 730 wdc_allocate_regs(&sc->sc_wdcdev); 731 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 732 PCI_MAPREG_START + 0x14); 733 switch(maptype) { 734 case PCI_MAPREG_TYPE_IO: 735 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 736 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 737 NULL, &satasize); 738 break; 739 case PCI_MAPREG_MEM_TYPE_32BIT: 740 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 741 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 742 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 743 NULL, &satasize); 744 break; 745 default: 746 aprint_error("%s: couldn't map sata regs, unsupported" 747 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 748 maptype); 749 return 0; 750 } 751 if (ret != 0) { 752 aprint_error("%s: couldn't map sata regs\n", 753 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 754 return 0; 755 } 756 return 1; 757 } 758 759 static void 760 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 761 int satareg_shift) 762 { 763 struct pciide_channel *cp; 764 struct ata_channel *wdc_cp; 765 struct wdc_regs *wdr; 766 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 767 int channel; 768 bus_size_t cmdsize, ctlsize; 769 770 if (via_sata_chip_map_common(sc, pa) == 0) 771 return; 772 773 if (interface == 0) { 774 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 775 DEBUG_PROBE); 776 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 777 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 778 } 779 780 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 781 channel++) { 782 cp = &sc->pciide_channels[channel]; 783 if (pciide_chansetup(sc, channel, interface) == 0) 784 continue; 785 wdc_cp = &cp->ata_channel; 786 wdr = CHAN_TO_WDC_REGS(wdc_cp); 787 wdr->sata_iot = sc->sc_ba5_st; 788 wdr->sata_baseioh = sc->sc_ba5_sh; 789 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 790 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 791 &wdr->sata_status) != 0) { 792 aprint_error("%s: couldn't map channel %d " 793 "sata_status regs\n", 794 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 795 wdc_cp->ch_channel); 796 continue; 797 } 798 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 799 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 800 &wdr->sata_error) != 0) { 801 aprint_error("%s: couldn't map channel %d " 802 "sata_error regs\n", 803 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 804 wdc_cp->ch_channel); 805 continue; 806 } 807 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 808 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 809 &wdr->sata_control) != 0) { 810 aprint_error("%s: couldn't map channel %d " 811 "sata_control regs\n", 812 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 813 wdc_cp->ch_channel); 814 continue; 815 } 816 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 817 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 818 pciide_pci_intr); 819 } 820 } 821 822 static void 823 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 824 { 825 via_sata_chip_map(sc, pa, 0); 826 } 827 828 static void 829 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 830 { 831 via_sata_chip_map(sc, pa, 6); 832 } 833 834 static void 835 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 836 { 837 via_sata_chip_map(sc, pa, 7); 838 } 839 840 static void 841 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 842 { 843 struct pciide_channel *cp; 844 struct ata_channel *wdc_cp; 845 struct wdc_regs *wdr; 846 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 847 int channel; 848 bus_size_t cmdsize; 849 pci_intr_handle_t intrhandle; 850 const char *intrstr; 851 int i; 852 853 if (via_sata_chip_map_common(sc, pa) == 0) 854 return; 855 856 if (interface == 0) { 857 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 858 DEBUG_PROBE); 859 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 860 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 861 } 862 863 if (pci_intr_map(pa, &intrhandle) != 0) { 864 aprint_error("%s: couldn't map native-PCI interrupt\n", 865 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 866 return; 867 } 868 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 869 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 870 intrhandle, IPL_BIO, pciide_pci_intr, sc); 871 if (sc->sc_pci_ih == NULL) { 872 aprint_error( 873 "%s: couldn't establish native-PCI interrupt", 874 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 875 if (intrstr != NULL) 876 aprint_error(" at %s", intrstr); 877 aprint_error("\n"); 878 return; 879 } 880 aprint_normal("%s: using %s for native-PCI interrupt\n", 881 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 882 intrstr ? intrstr : "unknown interrupt"); 883 884 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 885 channel++) { 886 cp = &sc->pciide_channels[channel]; 887 if (pciide_chansetup(sc, channel, interface) == 0) 888 continue; 889 cp->ata_channel.ch_ndrive = 1; 890 wdc_cp = &cp->ata_channel; 891 wdr = CHAN_TO_WDC_REGS(wdc_cp); 892 893 wdr->sata_iot = sc->sc_ba5_st; 894 wdr->sata_baseioh = sc->sc_ba5_sh; 895 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 896 (wdc_cp->ch_channel << 6) + 0x0, 1, 897 &wdr->sata_status) != 0) { 898 aprint_error("%s: couldn't map channel %d " 899 "sata_status regs\n", 900 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 901 wdc_cp->ch_channel); 902 continue; 903 } 904 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 905 (wdc_cp->ch_channel << 6) + 0x4, 1, 906 &wdr->sata_error) != 0) { 907 aprint_error("%s: couldn't map channel %d " 908 "sata_error regs\n", 909 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 910 wdc_cp->ch_channel); 911 continue; 912 } 913 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 914 (wdc_cp->ch_channel << 6) + 0x8, 1, 915 &wdr->sata_control) != 0) { 916 aprint_error("%s: couldn't map channel %d " 917 "sata_control regs\n", 918 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 919 wdc_cp->ch_channel); 920 continue; 921 } 922 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 923 924 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 925 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 926 NULL, &cmdsize) != 0) { 927 aprint_error("%s: couldn't map %s channel regs\n", 928 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 929 cp->name); 930 } 931 wdr->ctl_iot = wdr->cmd_iot; 932 for (i = 0; i < WDC_NREG; i++) { 933 if (bus_space_subregion(wdr->cmd_iot, 934 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 935 &wdr->cmd_iohs[i]) != 0) { 936 aprint_error("%s: couldn't subregion %s " 937 "channel cmd regs\n", 938 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 939 cp->name); 940 return; 941 } 942 } 943 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 944 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 945 aprint_error("%s: couldn't map channel %d ctl regs\n", 946 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 947 return; 948 } 949 wdc_init_shadow_regs(wdc_cp); 950 wdcattach(wdc_cp); 951 } 952 } 953
Indexes created Sun Oct 19 02:09:48 GMT 2025