viaide.c revision 1.26.2.1
1 /* $NetBSD: viaide.c,v 1.26.2.1 2006/01/15 10:02:49 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.26.2.1 2006/01/15 10:02:49 yamt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_sata_chip_map(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_setup_channel(struct ata_channel *); 50 51 static int viaide_match(struct device *, struct cfdata *, void *); 52 static void viaide_attach(struct device *, struct device *, void *); 53 static const struct pciide_product_desc * 54 viaide_lookup(pcireg_t); 55 56 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 57 viaide_match, viaide_attach, NULL, NULL); 58 59 static const struct pciide_product_desc pciide_amd_products[] = { 60 { PCI_PRODUCT_AMD_PBC756_IDE, 61 0, 62 "Advanced Micro Devices AMD756 IDE Controller", 63 via_chip_map 64 }, 65 { PCI_PRODUCT_AMD_PBC766_IDE, 66 0, 67 "Advanced Micro Devices AMD766 IDE Controller", 68 via_chip_map 69 }, 70 { PCI_PRODUCT_AMD_PBC768_IDE, 71 0, 72 "Advanced Micro Devices AMD768 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC8111_IDE, 76 0, 77 "Advanced Micro Devices AMD8111 IDE Controller", 78 via_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static const struct pciide_product_desc pciide_nvidia_products[] = { 88 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 89 0, 90 "NVIDIA nForce IDE Controller", 91 via_chip_map 92 }, 93 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 94 0, 95 "NVIDIA nForce2 IDE Controller", 96 via_chip_map 97 }, 98 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 99 0, 100 "NVIDIA nForce2 Ultra 400 IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 104 0, 105 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 106 via_sata_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 109 0, 110 "NVIDIA nForce3 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 114 0, 115 "NVIDIA nForce3 250 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 119 0, 120 "NVIDIA nForce3 250 Serial ATA Controller", 121 via_sata_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 124 0, 125 "NVIDIA nForce4 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 129 0, 130 "NVIDIA nForce4 Serial ATA Controller", 131 via_sata_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 134 0, 135 "NVIDIA nForce4 Serial ATA Controller", 136 via_sata_chip_map 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 139 0, 140 "NVIDIA nForce430 IDE Controller", 141 via_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 144 0, 145 "NVIDIA nForce430 Serial ATA Controller", 146 via_sata_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 149 0, 150 "NVIDIA nForce430 Serial ATA Controller", 151 via_sata_chip_map 152 }, 153 { 0, 154 0, 155 NULL, 156 NULL 157 } 158 }; 159 160 static const struct pciide_product_desc pciide_via_products[] = { 161 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 162 0, 163 NULL, 164 via_chip_map, 165 }, 166 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 167 0, 168 NULL, 169 via_chip_map, 170 }, 171 { PCI_PRODUCT_VIATECH_VT6421_RAID, 172 0, 173 "VIA Technologies VT6421 Serial RAID Controller", 174 via_sata_chip_map, 175 }, 176 { PCI_PRODUCT_VIATECH_VT8237_SATA, 177 0, 178 "VIA Technologies VT8237 SATA Controller", 179 via_sata_chip_map, 180 }, 181 { 0, 182 0, 183 NULL, 184 NULL 185 } 186 }; 187 188 static const struct pciide_product_desc * 189 viaide_lookup(pcireg_t id) 190 { 191 192 switch (PCI_VENDOR(id)) { 193 case PCI_VENDOR_VIATECH: 194 return (pciide_lookup_product(id, pciide_via_products)); 195 196 case PCI_VENDOR_AMD: 197 return (pciide_lookup_product(id, pciide_amd_products)); 198 199 case PCI_VENDOR_NVIDIA: 200 return (pciide_lookup_product(id, pciide_nvidia_products)); 201 } 202 return (NULL); 203 } 204 205 static int 206 viaide_match(struct device *parent, struct cfdata *match, void *aux) 207 { 208 struct pci_attach_args *pa = aux; 209 210 if (viaide_lookup(pa->pa_id) != NULL) 211 return (2); 212 return (0); 213 } 214 215 static void 216 viaide_attach(struct device *parent, struct device *self, void *aux) 217 { 218 struct pci_attach_args *pa = aux; 219 struct pciide_softc *sc = (struct pciide_softc *)self; 220 const struct pciide_product_desc *pp; 221 222 pp = viaide_lookup(pa->pa_id); 223 if (pp == NULL) 224 panic("viaide_attach"); 225 pciide_common_attach(sc, pa, pp); 226 } 227 228 static int 229 via_pcib_match(struct pci_attach_args *pa) 230 { 231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 232 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 233 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 234 return (1); 235 return 0; 236 } 237 238 static void 239 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 240 { 241 struct pciide_channel *cp; 242 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 243 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 244 int channel; 245 u_int32_t ideconf; 246 bus_size_t cmdsize, ctlsize; 247 pcireg_t pcib_id, pcib_class; 248 struct pci_attach_args pcib_pa; 249 250 if (pciide_chipen(sc, pa) == 0) 251 return; 252 253 switch (vendor) { 254 case PCI_VENDOR_VIATECH: 255 /* 256 * get a PCI tag for the ISA bridge. 257 */ 258 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 259 goto unknown; 260 pcib_id = pcib_pa.pa_id; 261 pcib_class = pcib_pa.pa_class; 262 aprint_normal("%s: VIA Technologies ", 263 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 264 switch (PCI_PRODUCT(pcib_id)) { 265 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 266 aprint_normal("VT82C586 (Apollo VP) "); 267 if(PCI_REVISION(pcib_class) >= 0x02) { 268 aprint_normal("ATA33 controller\n"); 269 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 270 } else { 271 aprint_normal("controller\n"); 272 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 273 } 274 break; 275 case PCI_PRODUCT_VIATECH_VT82C596A: 276 aprint_normal("VT82C596A (Apollo Pro) "); 277 if (PCI_REVISION(pcib_class) >= 0x12) { 278 aprint_normal("ATA66 controller\n"); 279 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 280 } else { 281 aprint_normal("ATA33 controller\n"); 282 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 283 } 284 break; 285 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 286 aprint_normal("VT82C686A (Apollo KX133) "); 287 if (PCI_REVISION(pcib_class) >= 0x40) { 288 aprint_normal("ATA100 controller\n"); 289 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 290 } else { 291 aprint_normal("ATA66 controller\n"); 292 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 293 } 294 break; 295 case PCI_PRODUCT_VIATECH_VT8231: 296 aprint_normal("VT8231 ATA100 controller\n"); 297 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 298 break; 299 case PCI_PRODUCT_VIATECH_VT8233: 300 aprint_normal("VT8233 ATA100 controller\n"); 301 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 302 break; 303 case PCI_PRODUCT_VIATECH_VT8233A: 304 aprint_normal("VT8233A ATA133 controller\n"); 305 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 306 break; 307 case PCI_PRODUCT_VIATECH_VT8235: 308 aprint_normal("VT8235 ATA133 controller\n"); 309 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 310 break; 311 case PCI_PRODUCT_VIATECH_VT8237: 312 aprint_normal("VT8237 ATA133 controller\n"); 313 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 314 break; 315 default: 316 unknown: 317 aprint_normal("unknown VIA ATA controller\n"); 318 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 319 } 320 sc->sc_apo_regbase = APO_VIA_REGBASE; 321 break; 322 case PCI_VENDOR_AMD: 323 switch (sc->sc_pp->ide_product) { 324 case PCI_PRODUCT_AMD_PBC8111_IDE: 325 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 326 break; 327 case PCI_PRODUCT_AMD_PBC766_IDE: 328 case PCI_PRODUCT_AMD_PBC768_IDE: 329 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 330 break; 331 default: 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 333 } 334 sc->sc_apo_regbase = APO_AMD_REGBASE; 335 break; 336 case PCI_VENDOR_NVIDIA: 337 switch (sc->sc_pp->ide_product) { 338 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 339 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 340 break; 341 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 342 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 343 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 344 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 345 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 346 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 347 break; 348 } 349 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 350 break; 351 default: 352 panic("via_chip_map: unknown vendor"); 353 } 354 355 aprint_normal("%s: bus-master DMA support present", 356 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 357 pciide_mapreg_dma(sc, pa); 358 aprint_normal("\n"); 359 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 360 if (sc->sc_dma_ok) { 361 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 362 sc->sc_wdcdev.irqack = pciide_irqack; 363 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 364 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 365 } 366 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 367 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 368 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 369 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 370 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 371 372 wdc_allocate_regs(&sc->sc_wdcdev); 373 374 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 375 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 376 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 377 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 378 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 379 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 380 DEBUG_PROBE); 381 382 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 383 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 384 channel++) { 385 cp = &sc->pciide_channels[channel]; 386 if (pciide_chansetup(sc, channel, interface) == 0) 387 continue; 388 389 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 390 aprint_normal("%s: %s channel ignored (disabled)\n", 391 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 392 cp->ata_channel.ch_flags |= ATACH_DISABLED; 393 continue; 394 } 395 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 396 pciide_pci_intr); 397 } 398 } 399 400 static void 401 via_setup_channel(struct ata_channel *chp) 402 { 403 u_int32_t udmatim_reg, datatim_reg; 404 u_int8_t idedma_ctl; 405 int mode, drive, s; 406 struct ata_drive_datas *drvp; 407 struct atac_softc *atac = chp->ch_atac; 408 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 409 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 410 #ifndef PCIIDE_AMD756_ENABLEDMA 411 int rev = PCI_REVISION( 412 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 413 #endif 414 415 idedma_ctl = 0; 416 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 417 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 418 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 419 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 420 421 /* setup DMA if needed */ 422 pciide_channel_dma_setup(cp); 423 424 for (drive = 0; drive < 2; drive++) { 425 drvp = &chp->ch_drive[drive]; 426 /* If no drive, skip */ 427 if ((drvp->drive_flags & DRIVE) == 0) 428 continue; 429 /* add timing values, setup DMA if needed */ 430 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 431 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 432 mode = drvp->PIO_mode; 433 goto pio; 434 } 435 if ((atac->atac_cap & ATAC_CAP_UDMA) && 436 (drvp->drive_flags & DRIVE_UDMA)) { 437 /* use Ultra/DMA */ 438 s = splbio(); 439 drvp->drive_flags &= ~DRIVE_DMA; 440 splx(s); 441 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 442 APO_UDMA_EN_MTH(chp->ch_channel, drive); 443 switch (PCI_VENDOR(sc->sc_pci_id)) { 444 case PCI_VENDOR_VIATECH: 445 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 446 /* 8233a */ 447 udmatim_reg |= APO_UDMA_TIME( 448 chp->ch_channel, 449 drive, 450 via_udma133_tim[drvp->UDMA_mode]); 451 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 452 /* 686b */ 453 udmatim_reg |= APO_UDMA_TIME( 454 chp->ch_channel, 455 drive, 456 via_udma100_tim[drvp->UDMA_mode]); 457 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 458 /* 596b or 686a */ 459 udmatim_reg |= APO_UDMA_CLK66( 460 chp->ch_channel); 461 udmatim_reg |= APO_UDMA_TIME( 462 chp->ch_channel, 463 drive, 464 via_udma66_tim[drvp->UDMA_mode]); 465 } else { 466 /* 596a or 586b */ 467 udmatim_reg |= APO_UDMA_TIME( 468 chp->ch_channel, 469 drive, 470 via_udma33_tim[drvp->UDMA_mode]); 471 } 472 break; 473 case PCI_VENDOR_AMD: 474 case PCI_VENDOR_NVIDIA: 475 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 476 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 477 break; 478 } 479 /* can use PIO timings, MW DMA unused */ 480 mode = drvp->PIO_mode; 481 } else { 482 /* use Multiword DMA, but only if revision is OK */ 483 s = splbio(); 484 drvp->drive_flags &= ~DRIVE_UDMA; 485 splx(s); 486 #ifndef PCIIDE_AMD756_ENABLEDMA 487 /* 488 * The workaround doesn't seem to be necessary 489 * with all drives, so it can be disabled by 490 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 491 * triggered. 492 */ 493 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 494 sc->sc_pp->ide_product == 495 PCI_PRODUCT_AMD_PBC756_IDE && 496 AMD756_CHIPREV_DISABLEDMA(rev)) { 497 aprint_normal( 498 "%s:%d:%d: multi-word DMA disabled due " 499 "to chip revision\n", 500 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 501 chp->ch_channel, drive); 502 mode = drvp->PIO_mode; 503 s = splbio(); 504 drvp->drive_flags &= ~DRIVE_DMA; 505 splx(s); 506 goto pio; 507 } 508 #endif 509 /* mode = min(pio, dma+2) */ 510 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 511 mode = drvp->PIO_mode; 512 else 513 mode = drvp->DMA_mode + 2; 514 } 515 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 516 517 pio: /* setup PIO mode */ 518 if (mode <= 2) { 519 drvp->DMA_mode = 0; 520 drvp->PIO_mode = 0; 521 mode = 0; 522 } else { 523 drvp->PIO_mode = mode; 524 drvp->DMA_mode = mode - 2; 525 } 526 datatim_reg |= 527 APO_DATATIM_PULSE(chp->ch_channel, drive, 528 apollo_pio_set[mode]) | 529 APO_DATATIM_RECOV(chp->ch_channel, drive, 530 apollo_pio_rec[mode]); 531 } 532 if (idedma_ctl != 0) { 533 /* Add software bits in status register */ 534 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 535 idedma_ctl); 536 } 537 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 538 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 539 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 540 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 541 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 542 } 543 544 static void 545 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 546 { 547 struct pciide_channel *cp; 548 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 549 int channel; 550 bus_size_t cmdsize, ctlsize; 551 552 if (pciide_chipen(sc, pa) == 0) 553 return; 554 555 if (interface == 0) { 556 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 557 DEBUG_PROBE); 558 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 559 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 560 } 561 562 aprint_normal("%s: bus-master DMA support present", 563 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 564 pciide_mapreg_dma(sc, pa); 565 aprint_normal("\n"); 566 567 if (sc->sc_dma_ok) { 568 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 569 sc->sc_wdcdev.irqack = pciide_irqack; 570 } 571 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 572 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 573 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 574 575 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 576 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 577 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 578 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 579 580 wdc_allocate_regs(&sc->sc_wdcdev); 581 582 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 583 channel++) { 584 cp = &sc->pciide_channels[channel]; 585 if (pciide_chansetup(sc, channel, interface) == 0) 586 continue; 587 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 588 pciide_pci_intr); 589 } 590 } 591
Indexes created Sun Oct 19 19:09:49 GMT 2025