viaide.c revision 1.28
1 /* $NetBSD: viaide.c,v 1.28 2006/01/31 16:49:26 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.28 2006/01/31 16:49:26 xtraeme Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_sata_chip_map(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_setup_channel(struct ata_channel *); 50 51 static int viaide_match(struct device *, struct cfdata *, void *); 52 static void viaide_attach(struct device *, struct device *, void *); 53 static const struct pciide_product_desc * 54 viaide_lookup(pcireg_t); 55 56 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 57 viaide_match, viaide_attach, NULL, NULL); 58 59 static const struct pciide_product_desc pciide_amd_products[] = { 60 { PCI_PRODUCT_AMD_PBC756_IDE, 61 0, 62 "Advanced Micro Devices AMD756 IDE Controller", 63 via_chip_map 64 }, 65 { PCI_PRODUCT_AMD_PBC766_IDE, 66 0, 67 "Advanced Micro Devices AMD766 IDE Controller", 68 via_chip_map 69 }, 70 { PCI_PRODUCT_AMD_PBC768_IDE, 71 0, 72 "Advanced Micro Devices AMD768 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC8111_IDE, 76 0, 77 "Advanced Micro Devices AMD8111 IDE Controller", 78 via_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static const struct pciide_product_desc pciide_nvidia_products[] = { 88 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 89 0, 90 "NVIDIA nForce IDE Controller", 91 via_chip_map 92 }, 93 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 94 0, 95 "NVIDIA nForce2 IDE Controller", 96 via_chip_map 97 }, 98 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 99 0, 100 "NVIDIA nForce2 Ultra 400 IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 104 0, 105 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 106 via_sata_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 109 0, 110 "NVIDIA nForce3 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 114 0, 115 "NVIDIA nForce3 250 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 119 0, 120 "NVIDIA nForce3 250 Serial ATA Controller", 121 via_sata_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 124 0, 125 "NVIDIA nForce4 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 129 0, 130 "NVIDIA nForce4 Serial ATA Controller", 131 via_sata_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 134 0, 135 "NVIDIA nForce4 Serial ATA Controller", 136 via_sata_chip_map 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 139 0, 140 "NVIDIA nForce430 IDE Controller", 141 via_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 144 0, 145 "NVIDIA nForce430 Serial ATA Controller", 146 via_sata_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 149 0, 150 "NVIDIA nForce430 Serial ATA Controller", 151 via_sata_chip_map 152 }, 153 { 0, 154 0, 155 NULL, 156 NULL 157 } 158 }; 159 160 static const struct pciide_product_desc pciide_via_products[] = { 161 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 162 0, 163 NULL, 164 via_chip_map, 165 }, 166 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 167 0, 168 NULL, 169 via_chip_map, 170 }, 171 { PCI_PRODUCT_VIATECH_VT6421_RAID, 172 0, 173 "VIA Technologies VT6421 Serial RAID Controller", 174 via_sata_chip_map, 175 }, 176 { PCI_PRODUCT_VIATECH_VT8237_SATA, 177 0, 178 "VIA Technologies VT8237 SATA Controller", 179 via_sata_chip_map, 180 }, 181 { 0, 182 0, 183 NULL, 184 NULL 185 } 186 }; 187 188 static const struct pciide_product_desc * 189 viaide_lookup(pcireg_t id) 190 { 191 192 switch (PCI_VENDOR(id)) { 193 case PCI_VENDOR_VIATECH: 194 return (pciide_lookup_product(id, pciide_via_products)); 195 196 case PCI_VENDOR_AMD: 197 return (pciide_lookup_product(id, pciide_amd_products)); 198 199 case PCI_VENDOR_NVIDIA: 200 return (pciide_lookup_product(id, pciide_nvidia_products)); 201 } 202 return (NULL); 203 } 204 205 static int 206 viaide_match(struct device *parent, struct cfdata *match, void *aux) 207 { 208 struct pci_attach_args *pa = aux; 209 210 if (viaide_lookup(pa->pa_id) != NULL) 211 return (2); 212 return (0); 213 } 214 215 static void 216 viaide_attach(struct device *parent, struct device *self, void *aux) 217 { 218 struct pci_attach_args *pa = aux; 219 struct pciide_softc *sc = (struct pciide_softc *)self; 220 const struct pciide_product_desc *pp; 221 222 pp = viaide_lookup(pa->pa_id); 223 if (pp == NULL) 224 panic("viaide_attach"); 225 pciide_common_attach(sc, pa, pp); 226 } 227 228 static int 229 via_pcib_match(struct pci_attach_args *pa) 230 { 231 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 232 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 233 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 234 return (1); 235 return 0; 236 } 237 238 static void 239 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 240 { 241 struct pciide_channel *cp; 242 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 243 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 244 int channel; 245 u_int32_t ideconf; 246 bus_size_t cmdsize, ctlsize; 247 pcireg_t pcib_id, pcib_class; 248 struct pci_attach_args pcib_pa; 249 250 if (pciide_chipen(sc, pa) == 0) 251 return; 252 253 switch (vendor) { 254 case PCI_VENDOR_VIATECH: 255 /* 256 * get a PCI tag for the ISA bridge. 257 */ 258 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 259 goto unknown; 260 pcib_id = pcib_pa.pa_id; 261 pcib_class = pcib_pa.pa_class; 262 aprint_normal("%s: VIA Technologies ", 263 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 264 switch (PCI_PRODUCT(pcib_id)) { 265 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 266 aprint_normal("VT82C586 (Apollo VP) "); 267 if(PCI_REVISION(pcib_class) >= 0x02) { 268 aprint_normal("ATA33 controller\n"); 269 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 270 } else { 271 aprint_normal("controller\n"); 272 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 273 } 274 break; 275 case PCI_PRODUCT_VIATECH_VT82C596A: 276 aprint_normal("VT82C596A (Apollo Pro) "); 277 if (PCI_REVISION(pcib_class) >= 0x12) { 278 aprint_normal("ATA66 controller\n"); 279 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 280 } else { 281 aprint_normal("ATA33 controller\n"); 282 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 283 } 284 break; 285 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 286 aprint_normal("VT82C686A (Apollo KX133) "); 287 if (PCI_REVISION(pcib_class) >= 0x40) { 288 aprint_normal("ATA100 controller\n"); 289 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 290 } else { 291 aprint_normal("ATA66 controller\n"); 292 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 293 } 294 break; 295 case PCI_PRODUCT_VIATECH_VT8231: 296 aprint_normal("VT8231 ATA100 controller\n"); 297 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 298 break; 299 case PCI_PRODUCT_VIATECH_VT8233: 300 aprint_normal("VT8233 ATA100 controller\n"); 301 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 302 break; 303 case PCI_PRODUCT_VIATECH_VT8233A: 304 aprint_normal("VT8233A ATA133 controller\n"); 305 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 306 break; 307 case PCI_PRODUCT_VIATECH_VT8235: 308 aprint_normal("VT8235 ATA133 controller\n"); 309 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 310 break; 311 case PCI_PRODUCT_VIATECH_VT8237: 312 aprint_normal("VT8237 ATA133 controller\n"); 313 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 314 break; 315 default: 316 unknown: 317 aprint_normal("unknown VIA ATA controller\n"); 318 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 319 } 320 sc->sc_apo_regbase = APO_VIA_REGBASE; 321 break; 322 case PCI_VENDOR_AMD: 323 switch (sc->sc_pp->ide_product) { 324 case PCI_PRODUCT_AMD_PBC8111_IDE: 325 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 326 break; 327 case PCI_PRODUCT_AMD_PBC766_IDE: 328 case PCI_PRODUCT_AMD_PBC768_IDE: 329 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 330 break; 331 default: 332 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 333 } 334 sc->sc_apo_regbase = APO_AMD_REGBASE; 335 break; 336 case PCI_VENDOR_NVIDIA: 337 switch (sc->sc_pp->ide_product) { 338 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 339 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 340 break; 341 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 342 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 343 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 344 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 345 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 346 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 347 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 348 break; 349 } 350 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 351 break; 352 default: 353 panic("via_chip_map: unknown vendor"); 354 } 355 356 aprint_normal("%s: bus-master DMA support present", 357 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 358 pciide_mapreg_dma(sc, pa); 359 aprint_normal("\n"); 360 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 361 if (sc->sc_dma_ok) { 362 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 363 sc->sc_wdcdev.irqack = pciide_irqack; 364 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 365 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 366 } 367 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 368 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 369 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 370 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 371 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 372 373 wdc_allocate_regs(&sc->sc_wdcdev); 374 375 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 376 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 377 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 378 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 379 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 380 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 381 DEBUG_PROBE); 382 383 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 384 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 385 channel++) { 386 cp = &sc->pciide_channels[channel]; 387 if (pciide_chansetup(sc, channel, interface) == 0) 388 continue; 389 390 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 391 aprint_normal("%s: %s channel ignored (disabled)\n", 392 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 393 cp->ata_channel.ch_flags |= ATACH_DISABLED; 394 continue; 395 } 396 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 397 pciide_pci_intr); 398 } 399 } 400 401 static void 402 via_setup_channel(struct ata_channel *chp) 403 { 404 u_int32_t udmatim_reg, datatim_reg; 405 u_int8_t idedma_ctl; 406 int mode, drive, s; 407 struct ata_drive_datas *drvp; 408 struct atac_softc *atac = chp->ch_atac; 409 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 410 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 411 #ifndef PCIIDE_AMD756_ENABLEDMA 412 int rev = PCI_REVISION( 413 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 414 #endif 415 416 idedma_ctl = 0; 417 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 418 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 419 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 420 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 421 422 /* setup DMA if needed */ 423 pciide_channel_dma_setup(cp); 424 425 for (drive = 0; drive < 2; drive++) { 426 drvp = &chp->ch_drive[drive]; 427 /* If no drive, skip */ 428 if ((drvp->drive_flags & DRIVE) == 0) 429 continue; 430 /* add timing values, setup DMA if needed */ 431 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 432 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 433 mode = drvp->PIO_mode; 434 goto pio; 435 } 436 if ((atac->atac_cap & ATAC_CAP_UDMA) && 437 (drvp->drive_flags & DRIVE_UDMA)) { 438 /* use Ultra/DMA */ 439 s = splbio(); 440 drvp->drive_flags &= ~DRIVE_DMA; 441 splx(s); 442 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 443 APO_UDMA_EN_MTH(chp->ch_channel, drive); 444 switch (PCI_VENDOR(sc->sc_pci_id)) { 445 case PCI_VENDOR_VIATECH: 446 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 447 /* 8233a */ 448 udmatim_reg |= APO_UDMA_TIME( 449 chp->ch_channel, 450 drive, 451 via_udma133_tim[drvp->UDMA_mode]); 452 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 453 /* 686b */ 454 udmatim_reg |= APO_UDMA_TIME( 455 chp->ch_channel, 456 drive, 457 via_udma100_tim[drvp->UDMA_mode]); 458 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 459 /* 596b or 686a */ 460 udmatim_reg |= APO_UDMA_CLK66( 461 chp->ch_channel); 462 udmatim_reg |= APO_UDMA_TIME( 463 chp->ch_channel, 464 drive, 465 via_udma66_tim[drvp->UDMA_mode]); 466 } else { 467 /* 596a or 586b */ 468 udmatim_reg |= APO_UDMA_TIME( 469 chp->ch_channel, 470 drive, 471 via_udma33_tim[drvp->UDMA_mode]); 472 } 473 break; 474 case PCI_VENDOR_AMD: 475 case PCI_VENDOR_NVIDIA: 476 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 477 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 478 break; 479 } 480 /* can use PIO timings, MW DMA unused */ 481 mode = drvp->PIO_mode; 482 } else { 483 /* use Multiword DMA, but only if revision is OK */ 484 s = splbio(); 485 drvp->drive_flags &= ~DRIVE_UDMA; 486 splx(s); 487 #ifndef PCIIDE_AMD756_ENABLEDMA 488 /* 489 * The workaround doesn't seem to be necessary 490 * with all drives, so it can be disabled by 491 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 492 * triggered. 493 */ 494 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 495 sc->sc_pp->ide_product == 496 PCI_PRODUCT_AMD_PBC756_IDE && 497 AMD756_CHIPREV_DISABLEDMA(rev)) { 498 aprint_normal( 499 "%s:%d:%d: multi-word DMA disabled due " 500 "to chip revision\n", 501 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 502 chp->ch_channel, drive); 503 mode = drvp->PIO_mode; 504 s = splbio(); 505 drvp->drive_flags &= ~DRIVE_DMA; 506 splx(s); 507 goto pio; 508 } 509 #endif 510 /* mode = min(pio, dma+2) */ 511 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 512 mode = drvp->PIO_mode; 513 else 514 mode = drvp->DMA_mode + 2; 515 } 516 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 517 518 pio: /* setup PIO mode */ 519 if (mode <= 2) { 520 drvp->DMA_mode = 0; 521 drvp->PIO_mode = 0; 522 mode = 0; 523 } else { 524 drvp->PIO_mode = mode; 525 drvp->DMA_mode = mode - 2; 526 } 527 datatim_reg |= 528 APO_DATATIM_PULSE(chp->ch_channel, drive, 529 apollo_pio_set[mode]) | 530 APO_DATATIM_RECOV(chp->ch_channel, drive, 531 apollo_pio_rec[mode]); 532 } 533 if (idedma_ctl != 0) { 534 /* Add software bits in status register */ 535 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 536 idedma_ctl); 537 } 538 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 539 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 540 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 541 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 542 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 543 } 544 545 static void 546 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 547 { 548 struct pciide_channel *cp; 549 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 550 int channel; 551 bus_size_t cmdsize, ctlsize; 552 553 if (pciide_chipen(sc, pa) == 0) 554 return; 555 556 if (interface == 0) { 557 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 558 DEBUG_PROBE); 559 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 560 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 561 } 562 563 aprint_normal("%s: bus-master DMA support present", 564 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 565 pciide_mapreg_dma(sc, pa); 566 aprint_normal("\n"); 567 568 if (sc->sc_dma_ok) { 569 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 570 sc->sc_wdcdev.irqack = pciide_irqack; 571 } 572 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 573 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 574 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 575 576 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 577 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 578 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 579 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 580 581 wdc_allocate_regs(&sc->sc_wdcdev); 582 583 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 584 channel++) { 585 cp = &sc->pciide_channels[channel]; 586 if (pciide_chansetup(sc, channel, interface) == 0) 587 continue; 588 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 589 pciide_pci_intr); 590 } 591 } 592
Indexes created Sun Oct 19 18:09:56 GMT 2025