viaide.c revision 1.28.4.1
1 /* $NetBSD: viaide.c,v 1.28.4.1 2006/06/01 22:36:49 kardel Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.28.4.1 2006/06/01 22:36:49 kardel Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_sata_chip_map(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_setup_channel(struct ata_channel *); 50 51 static int viaide_match(struct device *, struct cfdata *, void *); 52 static void viaide_attach(struct device *, struct device *, void *); 53 static const struct pciide_product_desc * 54 viaide_lookup(pcireg_t); 55 56 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 57 viaide_match, viaide_attach, NULL, NULL); 58 59 static const struct pciide_product_desc pciide_amd_products[] = { 60 { PCI_PRODUCT_AMD_PBC756_IDE, 61 0, 62 "Advanced Micro Devices AMD756 IDE Controller", 63 via_chip_map 64 }, 65 { PCI_PRODUCT_AMD_PBC766_IDE, 66 0, 67 "Advanced Micro Devices AMD766 IDE Controller", 68 via_chip_map 69 }, 70 { PCI_PRODUCT_AMD_PBC768_IDE, 71 0, 72 "Advanced Micro Devices AMD768 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC8111_IDE, 76 0, 77 "Advanced Micro Devices AMD8111 IDE Controller", 78 via_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static const struct pciide_product_desc pciide_nvidia_products[] = { 88 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 89 0, 90 "NVIDIA nForce IDE Controller", 91 via_chip_map 92 }, 93 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 94 0, 95 "NVIDIA nForce2 IDE Controller", 96 via_chip_map 97 }, 98 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 99 0, 100 "NVIDIA nForce2 Ultra 400 IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 104 0, 105 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 106 via_sata_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 109 0, 110 "NVIDIA nForce3 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 114 0, 115 "NVIDIA nForce3 250 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 119 0, 120 "NVIDIA nForce3 250 Serial ATA Controller", 121 via_sata_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 124 0, 125 "NVIDIA nForce4 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 129 0, 130 "NVIDIA nForce4 Serial ATA Controller", 131 via_sata_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 134 0, 135 "NVIDIA nForce4 Serial ATA Controller", 136 via_sata_chip_map 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 139 0, 140 "NVIDIA nForce430 IDE Controller", 141 via_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 144 0, 145 "NVIDIA nForce430 Serial ATA Controller", 146 via_sata_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 149 0, 150 "NVIDIA nForce430 Serial ATA Controller", 151 via_sata_chip_map 152 }, 153 { 0, 154 0, 155 NULL, 156 NULL 157 } 158 }; 159 160 static const struct pciide_product_desc pciide_via_products[] = { 161 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 162 0, 163 NULL, 164 via_chip_map, 165 }, 166 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 167 0, 168 NULL, 169 via_chip_map, 170 }, 171 { PCI_PRODUCT_VIATECH_VT6421_RAID, 172 0, 173 "VIA Technologies VT6421 Serial RAID Controller", 174 via_sata_chip_map, 175 }, 176 { PCI_PRODUCT_VIATECH_VT8237_SATA, 177 0, 178 "VIA Technologies VT8237 SATA Controller", 179 via_sata_chip_map, 180 }, 181 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 182 0, 183 "VIA Technologies VT8237R SATA Controller", 184 via_sata_chip_map, 185 }, 186 { 0, 187 0, 188 NULL, 189 NULL 190 } 191 }; 192 193 static const struct pciide_product_desc * 194 viaide_lookup(pcireg_t id) 195 { 196 197 switch (PCI_VENDOR(id)) { 198 case PCI_VENDOR_VIATECH: 199 return (pciide_lookup_product(id, pciide_via_products)); 200 201 case PCI_VENDOR_AMD: 202 return (pciide_lookup_product(id, pciide_amd_products)); 203 204 case PCI_VENDOR_NVIDIA: 205 return (pciide_lookup_product(id, pciide_nvidia_products)); 206 } 207 return (NULL); 208 } 209 210 static int 211 viaide_match(struct device *parent, struct cfdata *match, void *aux) 212 { 213 struct pci_attach_args *pa = aux; 214 215 if (viaide_lookup(pa->pa_id) != NULL) 216 return (2); 217 return (0); 218 } 219 220 static void 221 viaide_attach(struct device *parent, struct device *self, void *aux) 222 { 223 struct pci_attach_args *pa = aux; 224 struct pciide_softc *sc = (struct pciide_softc *)self; 225 const struct pciide_product_desc *pp; 226 227 pp = viaide_lookup(pa->pa_id); 228 if (pp == NULL) 229 panic("viaide_attach"); 230 pciide_common_attach(sc, pa, pp); 231 } 232 233 static int 234 via_pcib_match(struct pci_attach_args *pa) 235 { 236 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 237 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 238 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 239 return (1); 240 return 0; 241 } 242 243 static void 244 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 245 { 246 struct pciide_channel *cp; 247 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 248 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 249 int channel; 250 u_int32_t ideconf; 251 bus_size_t cmdsize, ctlsize; 252 pcireg_t pcib_id, pcib_class; 253 struct pci_attach_args pcib_pa; 254 255 if (pciide_chipen(sc, pa) == 0) 256 return; 257 258 switch (vendor) { 259 case PCI_VENDOR_VIATECH: 260 /* 261 * get a PCI tag for the ISA bridge. 262 */ 263 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 264 goto unknown; 265 pcib_id = pcib_pa.pa_id; 266 pcib_class = pcib_pa.pa_class; 267 aprint_normal("%s: VIA Technologies ", 268 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 269 switch (PCI_PRODUCT(pcib_id)) { 270 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 271 aprint_normal("VT82C586 (Apollo VP) "); 272 if(PCI_REVISION(pcib_class) >= 0x02) { 273 aprint_normal("ATA33 controller\n"); 274 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 275 } else { 276 aprint_normal("controller\n"); 277 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 278 } 279 break; 280 case PCI_PRODUCT_VIATECH_VT82C596A: 281 aprint_normal("VT82C596A (Apollo Pro) "); 282 if (PCI_REVISION(pcib_class) >= 0x12) { 283 aprint_normal("ATA66 controller\n"); 284 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 285 } else { 286 aprint_normal("ATA33 controller\n"); 287 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 288 } 289 break; 290 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 291 aprint_normal("VT82C686A (Apollo KX133) "); 292 if (PCI_REVISION(pcib_class) >= 0x40) { 293 aprint_normal("ATA100 controller\n"); 294 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 295 } else { 296 aprint_normal("ATA66 controller\n"); 297 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 298 } 299 break; 300 case PCI_PRODUCT_VIATECH_VT8231: 301 aprint_normal("VT8231 ATA100 controller\n"); 302 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 303 break; 304 case PCI_PRODUCT_VIATECH_VT8233: 305 aprint_normal("VT8233 ATA100 controller\n"); 306 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 307 break; 308 case PCI_PRODUCT_VIATECH_VT8233A: 309 aprint_normal("VT8233A ATA133 controller\n"); 310 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 311 break; 312 case PCI_PRODUCT_VIATECH_VT8235: 313 aprint_normal("VT8235 ATA133 controller\n"); 314 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 315 break; 316 case PCI_PRODUCT_VIATECH_VT8237: 317 aprint_normal("VT8237 ATA133 controller\n"); 318 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 319 break; 320 default: 321 unknown: 322 aprint_normal("unknown VIA ATA controller\n"); 323 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 324 } 325 sc->sc_apo_regbase = APO_VIA_REGBASE; 326 break; 327 case PCI_VENDOR_AMD: 328 switch (sc->sc_pp->ide_product) { 329 case PCI_PRODUCT_AMD_PBC8111_IDE: 330 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 331 break; 332 case PCI_PRODUCT_AMD_PBC766_IDE: 333 case PCI_PRODUCT_AMD_PBC768_IDE: 334 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 335 break; 336 default: 337 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 338 } 339 sc->sc_apo_regbase = APO_AMD_REGBASE; 340 break; 341 case PCI_VENDOR_NVIDIA: 342 switch (sc->sc_pp->ide_product) { 343 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 344 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 345 break; 346 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 347 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 348 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 349 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 350 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 351 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 352 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 353 break; 354 } 355 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 356 break; 357 default: 358 panic("via_chip_map: unknown vendor"); 359 } 360 361 aprint_normal("%s: bus-master DMA support present", 362 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 363 pciide_mapreg_dma(sc, pa); 364 aprint_normal("\n"); 365 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 366 if (sc->sc_dma_ok) { 367 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 368 sc->sc_wdcdev.irqack = pciide_irqack; 369 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 370 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 371 } 372 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 373 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 374 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 375 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 376 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 377 378 wdc_allocate_regs(&sc->sc_wdcdev); 379 380 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 381 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 382 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 383 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 384 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 385 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 386 DEBUG_PROBE); 387 388 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 389 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 390 channel++) { 391 cp = &sc->pciide_channels[channel]; 392 if (pciide_chansetup(sc, channel, interface) == 0) 393 continue; 394 395 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 396 aprint_normal("%s: %s channel ignored (disabled)\n", 397 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 398 cp->ata_channel.ch_flags |= ATACH_DISABLED; 399 continue; 400 } 401 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 402 pciide_pci_intr); 403 } 404 } 405 406 static void 407 via_setup_channel(struct ata_channel *chp) 408 { 409 u_int32_t udmatim_reg, datatim_reg; 410 u_int8_t idedma_ctl; 411 int mode, drive, s; 412 struct ata_drive_datas *drvp; 413 struct atac_softc *atac = chp->ch_atac; 414 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 415 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 416 #ifndef PCIIDE_AMD756_ENABLEDMA 417 int rev = PCI_REVISION( 418 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 419 #endif 420 421 idedma_ctl = 0; 422 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 423 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 424 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 425 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 426 427 /* setup DMA if needed */ 428 pciide_channel_dma_setup(cp); 429 430 for (drive = 0; drive < 2; drive++) { 431 drvp = &chp->ch_drive[drive]; 432 /* If no drive, skip */ 433 if ((drvp->drive_flags & DRIVE) == 0) 434 continue; 435 /* add timing values, setup DMA if needed */ 436 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 437 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 438 mode = drvp->PIO_mode; 439 goto pio; 440 } 441 if ((atac->atac_cap & ATAC_CAP_UDMA) && 442 (drvp->drive_flags & DRIVE_UDMA)) { 443 /* use Ultra/DMA */ 444 s = splbio(); 445 drvp->drive_flags &= ~DRIVE_DMA; 446 splx(s); 447 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 448 APO_UDMA_EN_MTH(chp->ch_channel, drive); 449 switch (PCI_VENDOR(sc->sc_pci_id)) { 450 case PCI_VENDOR_VIATECH: 451 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 452 /* 8233a */ 453 udmatim_reg |= APO_UDMA_TIME( 454 chp->ch_channel, 455 drive, 456 via_udma133_tim[drvp->UDMA_mode]); 457 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 458 /* 686b */ 459 udmatim_reg |= APO_UDMA_TIME( 460 chp->ch_channel, 461 drive, 462 via_udma100_tim[drvp->UDMA_mode]); 463 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 464 /* 596b or 686a */ 465 udmatim_reg |= APO_UDMA_CLK66( 466 chp->ch_channel); 467 udmatim_reg |= APO_UDMA_TIME( 468 chp->ch_channel, 469 drive, 470 via_udma66_tim[drvp->UDMA_mode]); 471 } else { 472 /* 596a or 586b */ 473 udmatim_reg |= APO_UDMA_TIME( 474 chp->ch_channel, 475 drive, 476 via_udma33_tim[drvp->UDMA_mode]); 477 } 478 break; 479 case PCI_VENDOR_AMD: 480 case PCI_VENDOR_NVIDIA: 481 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 482 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 483 break; 484 } 485 /* can use PIO timings, MW DMA unused */ 486 mode = drvp->PIO_mode; 487 } else { 488 /* use Multiword DMA, but only if revision is OK */ 489 s = splbio(); 490 drvp->drive_flags &= ~DRIVE_UDMA; 491 splx(s); 492 #ifndef PCIIDE_AMD756_ENABLEDMA 493 /* 494 * The workaround doesn't seem to be necessary 495 * with all drives, so it can be disabled by 496 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 497 * triggered. 498 */ 499 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 500 sc->sc_pp->ide_product == 501 PCI_PRODUCT_AMD_PBC756_IDE && 502 AMD756_CHIPREV_DISABLEDMA(rev)) { 503 aprint_normal( 504 "%s:%d:%d: multi-word DMA disabled due " 505 "to chip revision\n", 506 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 507 chp->ch_channel, drive); 508 mode = drvp->PIO_mode; 509 s = splbio(); 510 drvp->drive_flags &= ~DRIVE_DMA; 511 splx(s); 512 goto pio; 513 } 514 #endif 515 /* mode = min(pio, dma+2) */ 516 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 517 mode = drvp->PIO_mode; 518 else 519 mode = drvp->DMA_mode + 2; 520 } 521 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 522 523 pio: /* setup PIO mode */ 524 if (mode <= 2) { 525 drvp->DMA_mode = 0; 526 drvp->PIO_mode = 0; 527 mode = 0; 528 } else { 529 drvp->PIO_mode = mode; 530 drvp->DMA_mode = mode - 2; 531 } 532 datatim_reg |= 533 APO_DATATIM_PULSE(chp->ch_channel, drive, 534 apollo_pio_set[mode]) | 535 APO_DATATIM_RECOV(chp->ch_channel, drive, 536 apollo_pio_rec[mode]); 537 } 538 if (idedma_ctl != 0) { 539 /* Add software bits in status register */ 540 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 541 idedma_ctl); 542 } 543 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 544 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 545 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 546 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 547 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 548 } 549 550 static void 551 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 552 { 553 struct pciide_channel *cp; 554 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 555 int channel; 556 bus_size_t cmdsize, ctlsize; 557 558 if (pciide_chipen(sc, pa) == 0) 559 return; 560 561 if (interface == 0) { 562 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 563 DEBUG_PROBE); 564 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 565 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 566 } 567 568 aprint_normal("%s: bus-master DMA support present", 569 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 570 pciide_mapreg_dma(sc, pa); 571 aprint_normal("\n"); 572 573 if (sc->sc_dma_ok) { 574 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 575 sc->sc_wdcdev.irqack = pciide_irqack; 576 } 577 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 578 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 579 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 580 581 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 582 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 583 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 584 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 585 586 wdc_allocate_regs(&sc->sc_wdcdev); 587 588 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 589 channel++) { 590 cp = &sc->pciide_channels[channel]; 591 if (pciide_chansetup(sc, channel, interface) == 0) 592 continue; 593 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 594 pciide_pci_intr); 595 } 596 } 597
Indexes created Fri Oct 17 09:09:57 GMT 2025