viaide.c revision 1.33
1 /* $NetBSD: viaide.c,v 1.33 2006/09/03 08:42:32 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.33 2006/09/03 08:42:32 xtraeme Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_sata_chip_map(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_setup_channel(struct ata_channel *); 50 51 static int viaide_match(struct device *, struct cfdata *, void *); 52 static void viaide_attach(struct device *, struct device *, void *); 53 static const struct pciide_product_desc * 54 viaide_lookup(pcireg_t); 55 56 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 57 viaide_match, viaide_attach, NULL, NULL); 58 59 static const struct pciide_product_desc pciide_amd_products[] = { 60 { PCI_PRODUCT_AMD_PBC756_IDE, 61 0, 62 "Advanced Micro Devices AMD756 IDE Controller", 63 via_chip_map 64 }, 65 { PCI_PRODUCT_AMD_PBC766_IDE, 66 0, 67 "Advanced Micro Devices AMD766 IDE Controller", 68 via_chip_map 69 }, 70 { PCI_PRODUCT_AMD_PBC768_IDE, 71 0, 72 "Advanced Micro Devices AMD768 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC8111_IDE, 76 0, 77 "Advanced Micro Devices AMD8111 IDE Controller", 78 via_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static const struct pciide_product_desc pciide_nvidia_products[] = { 88 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 89 0, 90 "NVIDIA nForce IDE Controller", 91 via_chip_map 92 }, 93 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 94 0, 95 "NVIDIA nForce2 IDE Controller", 96 via_chip_map 97 }, 98 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 99 0, 100 "NVIDIA nForce2 Ultra 400 IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 104 0, 105 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 106 via_sata_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 109 0, 110 "NVIDIA nForce3 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 114 0, 115 "NVIDIA nForce3 250 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 119 0, 120 "NVIDIA nForce3 250 Serial ATA Controller", 121 via_sata_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 124 0, 125 "NVIDIA nForce3 250 Serial ATA Controller", 126 via_sata_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 129 0, 130 "NVIDIA nForce4 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 134 0, 135 "NVIDIA nForce4 Serial ATA Controller", 136 via_sata_chip_map 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 139 0, 140 "NVIDIA nForce4 Serial ATA Controller", 141 via_sata_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 144 0, 145 "NVIDIA nForce430 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 149 0, 150 "NVIDIA nForce430 Serial ATA Controller", 151 via_sata_chip_map 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 154 0, 155 "NVIDIA nForce430 Serial ATA Controller", 156 via_sata_chip_map 157 }, 158 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 159 0, 160 "NVIDIA MCP04 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 164 0, 165 "NVIDIA MCP04 Serial ATA Controller", 166 via_sata_chip_map 167 }, 168 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 169 0, 170 "NVIDIA MCP04 Serial ATA Controller", 171 via_sata_chip_map 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 174 0, 175 "NVIDIA MCP55 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 179 0, 180 "NVIDIA MCP55 Serial ATA Controller", 181 via_sata_chip_map 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 184 0, 185 "NVIDIA MCP55 Serial ATA Controller", 186 via_sata_chip_map 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 189 0, 190 "NVIDIA MCP61 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 194 0, 195 "NVIDIA MCP65 IDE Controller", 196 via_chip_map 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 199 0, 200 "NVIDIA MCP61 Serial ATA Controller", 201 via_sata_chip_map 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 204 0, 205 "NVIDIA MCP61 Serial ATA Controller", 206 via_sata_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 209 0, 210 "NVIDIA MCP61 Serial ATA Controller", 211 via_sata_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 214 0, 215 "NVIDIA MCP65 Serial ATA Controller", 216 via_sata_chip_map 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 219 0, 220 "NVIDIA MCP65 Serial ATA Controller", 221 via_sata_chip_map 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 224 0, 225 "NVIDIA MCP65 Serial ATA Controller", 226 via_sata_chip_map 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map 232 }, 233 { 0, 234 0, 235 NULL, 236 NULL 237 } 238 }; 239 240 static const struct pciide_product_desc pciide_via_products[] = { 241 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 242 0, 243 NULL, 244 via_chip_map, 245 }, 246 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 247 0, 248 NULL, 249 via_chip_map, 250 }, 251 { PCI_PRODUCT_VIATECH_VT6421_RAID, 252 0, 253 "VIA Technologies VT6421 Serial RAID Controller", 254 via_sata_chip_map, 255 }, 256 { PCI_PRODUCT_VIATECH_VT8237_SATA, 257 0, 258 "VIA Technologies VT8237 SATA Controller", 259 via_sata_chip_map, 260 }, 261 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 262 0, 263 "VIA Technologies VT8237R SATA Controller", 264 via_sata_chip_map, 265 }, 266 { 0, 267 0, 268 NULL, 269 NULL 270 } 271 }; 272 273 static const struct pciide_product_desc * 274 viaide_lookup(pcireg_t id) 275 { 276 277 switch (PCI_VENDOR(id)) { 278 case PCI_VENDOR_VIATECH: 279 return (pciide_lookup_product(id, pciide_via_products)); 280 281 case PCI_VENDOR_AMD: 282 return (pciide_lookup_product(id, pciide_amd_products)); 283 284 case PCI_VENDOR_NVIDIA: 285 return (pciide_lookup_product(id, pciide_nvidia_products)); 286 } 287 return (NULL); 288 } 289 290 static int 291 viaide_match(struct device *parent, struct cfdata *match, void *aux) 292 { 293 struct pci_attach_args *pa = aux; 294 295 if (viaide_lookup(pa->pa_id) != NULL) 296 return (2); 297 return (0); 298 } 299 300 static void 301 viaide_attach(struct device *parent, struct device *self, void *aux) 302 { 303 struct pci_attach_args *pa = aux; 304 struct pciide_softc *sc = (struct pciide_softc *)self; 305 const struct pciide_product_desc *pp; 306 307 pp = viaide_lookup(pa->pa_id); 308 if (pp == NULL) 309 panic("viaide_attach"); 310 pciide_common_attach(sc, pa, pp); 311 } 312 313 static int 314 via_pcib_match(struct pci_attach_args *pa) 315 { 316 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 317 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 318 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 319 return (1); 320 return 0; 321 } 322 323 static void 324 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 325 { 326 struct pciide_channel *cp; 327 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 328 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 329 int channel; 330 u_int32_t ideconf; 331 bus_size_t cmdsize, ctlsize; 332 pcireg_t pcib_id, pcib_class; 333 struct pci_attach_args pcib_pa; 334 335 if (pciide_chipen(sc, pa) == 0) 336 return; 337 338 switch (vendor) { 339 case PCI_VENDOR_VIATECH: 340 /* 341 * get a PCI tag for the ISA bridge. 342 */ 343 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 344 goto unknown; 345 pcib_id = pcib_pa.pa_id; 346 pcib_class = pcib_pa.pa_class; 347 aprint_normal("%s: VIA Technologies ", 348 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 349 switch (PCI_PRODUCT(pcib_id)) { 350 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 351 aprint_normal("VT82C586 (Apollo VP) "); 352 if(PCI_REVISION(pcib_class) >= 0x02) { 353 aprint_normal("ATA33 controller\n"); 354 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 355 } else { 356 aprint_normal("controller\n"); 357 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 358 } 359 break; 360 case PCI_PRODUCT_VIATECH_VT82C596A: 361 aprint_normal("VT82C596A (Apollo Pro) "); 362 if (PCI_REVISION(pcib_class) >= 0x12) { 363 aprint_normal("ATA66 controller\n"); 364 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 365 } else { 366 aprint_normal("ATA33 controller\n"); 367 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 368 } 369 break; 370 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 371 aprint_normal("VT82C686A (Apollo KX133) "); 372 if (PCI_REVISION(pcib_class) >= 0x40) { 373 aprint_normal("ATA100 controller\n"); 374 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 375 } else { 376 aprint_normal("ATA66 controller\n"); 377 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 378 } 379 break; 380 case PCI_PRODUCT_VIATECH_VT8231: 381 aprint_normal("VT8231 ATA100 controller\n"); 382 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 383 break; 384 case PCI_PRODUCT_VIATECH_VT8233: 385 aprint_normal("VT8233 ATA100 controller\n"); 386 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 387 break; 388 case PCI_PRODUCT_VIATECH_VT8233A: 389 aprint_normal("VT8233A ATA133 controller\n"); 390 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 391 break; 392 case PCI_PRODUCT_VIATECH_VT8235: 393 aprint_normal("VT8235 ATA133 controller\n"); 394 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 395 break; 396 case PCI_PRODUCT_VIATECH_VT8237: 397 aprint_normal("VT8237 ATA133 controller\n"); 398 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 399 break; 400 default: 401 unknown: 402 aprint_normal("unknown VIA ATA controller\n"); 403 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 404 } 405 sc->sc_apo_regbase = APO_VIA_REGBASE; 406 break; 407 case PCI_VENDOR_AMD: 408 switch (sc->sc_pp->ide_product) { 409 case PCI_PRODUCT_AMD_PBC8111_IDE: 410 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 411 break; 412 case PCI_PRODUCT_AMD_PBC766_IDE: 413 case PCI_PRODUCT_AMD_PBC768_IDE: 414 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 415 break; 416 default: 417 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 418 } 419 sc->sc_apo_regbase = APO_AMD_REGBASE; 420 break; 421 case PCI_VENDOR_NVIDIA: 422 switch (sc->sc_pp->ide_product) { 423 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 424 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 425 break; 426 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 427 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 428 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 429 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 430 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 431 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 432 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 433 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 434 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 435 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 436 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 437 break; 438 } 439 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 440 break; 441 default: 442 panic("via_chip_map: unknown vendor"); 443 } 444 445 aprint_normal("%s: bus-master DMA support present", 446 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 447 pciide_mapreg_dma(sc, pa); 448 aprint_normal("\n"); 449 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 450 if (sc->sc_dma_ok) { 451 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 452 sc->sc_wdcdev.irqack = pciide_irqack; 453 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 454 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 455 } 456 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 457 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 458 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 459 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 460 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 461 462 wdc_allocate_regs(&sc->sc_wdcdev); 463 464 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 465 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 466 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 467 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 468 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 469 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 470 DEBUG_PROBE); 471 472 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 473 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 474 channel++) { 475 cp = &sc->pciide_channels[channel]; 476 if (pciide_chansetup(sc, channel, interface) == 0) 477 continue; 478 479 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 480 aprint_normal("%s: %s channel ignored (disabled)\n", 481 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 482 cp->ata_channel.ch_flags |= ATACH_DISABLED; 483 continue; 484 } 485 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 486 pciide_pci_intr); 487 } 488 } 489 490 static void 491 via_setup_channel(struct ata_channel *chp) 492 { 493 u_int32_t udmatim_reg, datatim_reg; 494 u_int8_t idedma_ctl; 495 int mode, drive, s; 496 struct ata_drive_datas *drvp; 497 struct atac_softc *atac = chp->ch_atac; 498 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 499 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 500 #ifndef PCIIDE_AMD756_ENABLEDMA 501 int rev = PCI_REVISION( 502 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 503 #endif 504 505 idedma_ctl = 0; 506 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 507 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 508 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 509 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 510 511 /* setup DMA if needed */ 512 pciide_channel_dma_setup(cp); 513 514 for (drive = 0; drive < 2; drive++) { 515 drvp = &chp->ch_drive[drive]; 516 /* If no drive, skip */ 517 if ((drvp->drive_flags & DRIVE) == 0) 518 continue; 519 /* add timing values, setup DMA if needed */ 520 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 521 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 522 mode = drvp->PIO_mode; 523 goto pio; 524 } 525 if ((atac->atac_cap & ATAC_CAP_UDMA) && 526 (drvp->drive_flags & DRIVE_UDMA)) { 527 /* use Ultra/DMA */ 528 s = splbio(); 529 drvp->drive_flags &= ~DRIVE_DMA; 530 splx(s); 531 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 532 APO_UDMA_EN_MTH(chp->ch_channel, drive); 533 switch (PCI_VENDOR(sc->sc_pci_id)) { 534 case PCI_VENDOR_VIATECH: 535 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 536 /* 8233a */ 537 udmatim_reg |= APO_UDMA_TIME( 538 chp->ch_channel, 539 drive, 540 via_udma133_tim[drvp->UDMA_mode]); 541 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 542 /* 686b */ 543 udmatim_reg |= APO_UDMA_TIME( 544 chp->ch_channel, 545 drive, 546 via_udma100_tim[drvp->UDMA_mode]); 547 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 548 /* 596b or 686a */ 549 udmatim_reg |= APO_UDMA_CLK66( 550 chp->ch_channel); 551 udmatim_reg |= APO_UDMA_TIME( 552 chp->ch_channel, 553 drive, 554 via_udma66_tim[drvp->UDMA_mode]); 555 } else { 556 /* 596a or 586b */ 557 udmatim_reg |= APO_UDMA_TIME( 558 chp->ch_channel, 559 drive, 560 via_udma33_tim[drvp->UDMA_mode]); 561 } 562 break; 563 case PCI_VENDOR_AMD: 564 case PCI_VENDOR_NVIDIA: 565 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 566 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 567 break; 568 } 569 /* can use PIO timings, MW DMA unused */ 570 mode = drvp->PIO_mode; 571 } else { 572 /* use Multiword DMA, but only if revision is OK */ 573 s = splbio(); 574 drvp->drive_flags &= ~DRIVE_UDMA; 575 splx(s); 576 #ifndef PCIIDE_AMD756_ENABLEDMA 577 /* 578 * The workaround doesn't seem to be necessary 579 * with all drives, so it can be disabled by 580 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 581 * triggered. 582 */ 583 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 584 sc->sc_pp->ide_product == 585 PCI_PRODUCT_AMD_PBC756_IDE && 586 AMD756_CHIPREV_DISABLEDMA(rev)) { 587 aprint_normal( 588 "%s:%d:%d: multi-word DMA disabled due " 589 "to chip revision\n", 590 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 591 chp->ch_channel, drive); 592 mode = drvp->PIO_mode; 593 s = splbio(); 594 drvp->drive_flags &= ~DRIVE_DMA; 595 splx(s); 596 goto pio; 597 } 598 #endif 599 /* mode = min(pio, dma+2) */ 600 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 601 mode = drvp->PIO_mode; 602 else 603 mode = drvp->DMA_mode + 2; 604 } 605 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 606 607 pio: /* setup PIO mode */ 608 if (mode <= 2) { 609 drvp->DMA_mode = 0; 610 drvp->PIO_mode = 0; 611 mode = 0; 612 } else { 613 drvp->PIO_mode = mode; 614 drvp->DMA_mode = mode - 2; 615 } 616 datatim_reg |= 617 APO_DATATIM_PULSE(chp->ch_channel, drive, 618 apollo_pio_set[mode]) | 619 APO_DATATIM_RECOV(chp->ch_channel, drive, 620 apollo_pio_rec[mode]); 621 } 622 if (idedma_ctl != 0) { 623 /* Add software bits in status register */ 624 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 625 idedma_ctl); 626 } 627 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 628 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 629 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 630 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 631 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 632 } 633 634 static void 635 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 636 { 637 struct pciide_channel *cp; 638 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 639 int channel; 640 bus_size_t cmdsize, ctlsize; 641 642 if (pciide_chipen(sc, pa) == 0) 643 return; 644 645 if (interface == 0) { 646 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 647 DEBUG_PROBE); 648 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 649 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 650 } 651 652 aprint_normal("%s: bus-master DMA support present", 653 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 654 pciide_mapreg_dma(sc, pa); 655 aprint_normal("\n"); 656 657 if (sc->sc_dma_ok) { 658 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 659 sc->sc_wdcdev.irqack = pciide_irqack; 660 } 661 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 662 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 663 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 664 665 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 666 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 667 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 668 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 669 670 wdc_allocate_regs(&sc->sc_wdcdev); 671 672 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 673 channel++) { 674 cp = &sc->pciide_channels[channel]; 675 if (pciide_chansetup(sc, channel, interface) == 0) 676 continue; 677 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 678 pciide_pci_intr); 679 } 680 } 681
Indexes created Sun Oct 19 02:09:48 GMT 2025