viaide.c revision 1.33.4.2
1 /* $NetBSD: viaide.c,v 1.33.4.2 2006/12/10 07:17:47 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.33.4.2 2006/12/10 07:17:47 yamt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { 0, 91 0, 92 NULL, 93 NULL 94 } 95 }; 96 97 static const struct pciide_product_desc pciide_nvidia_products[] = { 98 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 99 0, 100 "NVIDIA nForce IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 104 0, 105 "NVIDIA nForce2 IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 109 0, 110 "NVIDIA nForce2 Ultra 400 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 114 0, 115 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 116 via_sata_chip_map_6 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 119 0, 120 "NVIDIA nForce3 IDE Controller", 121 via_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 124 0, 125 "NVIDIA nForce3 250 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 129 0, 130 "NVIDIA nForce3 250 Serial ATA Controller", 131 via_sata_chip_map_6 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 139 0, 140 "NVIDIA nForce4 IDE Controller", 141 via_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 144 0, 145 "NVIDIA nForce4 Serial ATA Controller", 146 via_sata_chip_map_6 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 154 0, 155 "NVIDIA nForce430 IDE Controller", 156 via_chip_map 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 159 0, 160 "NVIDIA nForce430 Serial ATA Controller", 161 via_sata_chip_map_6 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 169 0, 170 "NVIDIA MCP04 IDE Controller", 171 via_chip_map 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 174 0, 175 "NVIDIA MCP04 Serial ATA Controller", 176 via_sata_chip_map_6 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 184 0, 185 "NVIDIA MCP55 IDE Controller", 186 via_chip_map 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 189 0, 190 "NVIDIA MCP55 Serial ATA Controller", 191 via_sata_chip_map_6 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 199 0, 200 "NVIDIA MCP61 IDE Controller", 201 via_chip_map 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 204 0, 205 "NVIDIA MCP65 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 209 0, 210 "NVIDIA MCP61 Serial ATA Controller", 211 via_sata_chip_map_6 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 214 0, 215 "NVIDIA MCP61 Serial ATA Controller", 216 via_sata_chip_map_6 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 219 0, 220 "NVIDIA MCP61 Serial ATA Controller", 221 via_sata_chip_map_6 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 224 0, 225 "NVIDIA MCP65 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 234 0, 235 "NVIDIA MCP65 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { 0, 244 0, 245 NULL, 246 NULL 247 } 248 }; 249 250 static const struct pciide_product_desc pciide_via_products[] = { 251 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 252 0, 253 NULL, 254 via_chip_map, 255 }, 256 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 257 0, 258 NULL, 259 via_chip_map, 260 }, 261 { PCI_PRODUCT_VIATECH_VT6421_RAID, 262 0, 263 "VIA Technologies VT6421 Serial RAID Controller", 264 via_sata_chip_map_new, 265 }, 266 { PCI_PRODUCT_VIATECH_VT8237_SATA, 267 0, 268 "VIA Technologies VT8237 SATA Controller", 269 via_sata_chip_map_7, 270 }, 271 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 272 0, 273 "VIA Technologies VT8237A SATA Controller", 274 via_sata_chip_map_0, 275 }, 276 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 277 0, 278 "VIA Technologies VT8237R SATA Controller", 279 via_sata_chip_map_0, 280 }, 281 { 0, 282 0, 283 NULL, 284 NULL 285 } 286 }; 287 288 static const struct pciide_product_desc * 289 viaide_lookup(pcireg_t id) 290 { 291 292 switch (PCI_VENDOR(id)) { 293 case PCI_VENDOR_VIATECH: 294 return (pciide_lookup_product(id, pciide_via_products)); 295 296 case PCI_VENDOR_AMD: 297 return (pciide_lookup_product(id, pciide_amd_products)); 298 299 case PCI_VENDOR_NVIDIA: 300 return (pciide_lookup_product(id, pciide_nvidia_products)); 301 } 302 return (NULL); 303 } 304 305 static int 306 viaide_match(struct device *parent, struct cfdata *match, 307 void *aux) 308 { 309 struct pci_attach_args *pa = aux; 310 311 if (viaide_lookup(pa->pa_id) != NULL) 312 return (2); 313 return (0); 314 } 315 316 static void 317 viaide_attach(struct device *parent, struct device *self, void *aux) 318 { 319 struct pci_attach_args *pa = aux; 320 struct pciide_softc *sc = (struct pciide_softc *)self; 321 const struct pciide_product_desc *pp; 322 323 pp = viaide_lookup(pa->pa_id); 324 if (pp == NULL) 325 panic("viaide_attach"); 326 pciide_common_attach(sc, pa, pp); 327 } 328 329 static int 330 via_pcib_match(struct pci_attach_args *pa) 331 { 332 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 333 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 334 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 335 return (1); 336 return 0; 337 } 338 339 static void 340 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 341 { 342 struct pciide_channel *cp; 343 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 344 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 345 int channel; 346 u_int32_t ideconf; 347 bus_size_t cmdsize, ctlsize; 348 pcireg_t pcib_id, pcib_class; 349 struct pci_attach_args pcib_pa; 350 351 if (pciide_chipen(sc, pa) == 0) 352 return; 353 354 switch (vendor) { 355 case PCI_VENDOR_VIATECH: 356 /* 357 * get a PCI tag for the ISA bridge. 358 */ 359 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 360 goto unknown; 361 pcib_id = pcib_pa.pa_id; 362 pcib_class = pcib_pa.pa_class; 363 aprint_normal("%s: VIA Technologies ", 364 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 365 switch (PCI_PRODUCT(pcib_id)) { 366 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 367 aprint_normal("VT82C586 (Apollo VP) "); 368 if(PCI_REVISION(pcib_class) >= 0x02) { 369 aprint_normal("ATA33 controller\n"); 370 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 371 } else { 372 aprint_normal("controller\n"); 373 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 374 } 375 break; 376 case PCI_PRODUCT_VIATECH_VT82C596A: 377 aprint_normal("VT82C596A (Apollo Pro) "); 378 if (PCI_REVISION(pcib_class) >= 0x12) { 379 aprint_normal("ATA66 controller\n"); 380 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 381 } else { 382 aprint_normal("ATA33 controller\n"); 383 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 384 } 385 break; 386 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 387 aprint_normal("VT82C686A (Apollo KX133) "); 388 if (PCI_REVISION(pcib_class) >= 0x40) { 389 aprint_normal("ATA100 controller\n"); 390 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 391 } else { 392 aprint_normal("ATA66 controller\n"); 393 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 394 } 395 break; 396 case PCI_PRODUCT_VIATECH_VT8231: 397 aprint_normal("VT8231 ATA100 controller\n"); 398 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 399 break; 400 case PCI_PRODUCT_VIATECH_VT8233: 401 aprint_normal("VT8233 ATA100 controller\n"); 402 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 403 break; 404 case PCI_PRODUCT_VIATECH_VT8233A: 405 aprint_normal("VT8233A ATA133 controller\n"); 406 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 407 break; 408 case PCI_PRODUCT_VIATECH_VT8235: 409 aprint_normal("VT8235 ATA133 controller\n"); 410 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 411 break; 412 case PCI_PRODUCT_VIATECH_VT8237: 413 aprint_normal("VT8237 ATA133 controller\n"); 414 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 415 break; 416 default: 417 unknown: 418 aprint_normal("unknown VIA ATA controller\n"); 419 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 420 } 421 sc->sc_apo_regbase = APO_VIA_REGBASE; 422 break; 423 case PCI_VENDOR_AMD: 424 switch (sc->sc_pp->ide_product) { 425 case PCI_PRODUCT_AMD_PBC8111_IDE: 426 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 427 break; 428 case PCI_PRODUCT_AMD_PBC766_IDE: 429 case PCI_PRODUCT_AMD_PBC768_IDE: 430 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 431 break; 432 default: 433 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 434 } 435 sc->sc_apo_regbase = APO_AMD_REGBASE; 436 break; 437 case PCI_VENDOR_NVIDIA: 438 switch (sc->sc_pp->ide_product) { 439 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 440 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 441 break; 442 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 443 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 444 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 445 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 446 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 447 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 448 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 449 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 450 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 451 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 452 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 453 break; 454 } 455 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 456 break; 457 default: 458 panic("via_chip_map: unknown vendor"); 459 } 460 461 aprint_normal("%s: bus-master DMA support present", 462 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 463 pciide_mapreg_dma(sc, pa); 464 aprint_normal("\n"); 465 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 466 if (sc->sc_dma_ok) { 467 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 468 sc->sc_wdcdev.irqack = pciide_irqack; 469 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 470 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 471 } 472 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 473 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 474 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 475 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 476 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 477 478 wdc_allocate_regs(&sc->sc_wdcdev); 479 480 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 481 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 482 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 483 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 484 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 485 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 486 DEBUG_PROBE); 487 488 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 489 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 490 channel++) { 491 cp = &sc->pciide_channels[channel]; 492 if (pciide_chansetup(sc, channel, interface) == 0) 493 continue; 494 495 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 496 aprint_normal("%s: %s channel ignored (disabled)\n", 497 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 498 cp->ata_channel.ch_flags |= ATACH_DISABLED; 499 continue; 500 } 501 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 502 pciide_pci_intr); 503 } 504 } 505 506 static void 507 via_setup_channel(struct ata_channel *chp) 508 { 509 u_int32_t udmatim_reg, datatim_reg; 510 u_int8_t idedma_ctl; 511 int mode, drive, s; 512 struct ata_drive_datas *drvp; 513 struct atac_softc *atac = chp->ch_atac; 514 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 515 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 516 #ifndef PCIIDE_AMD756_ENABLEDMA 517 int rev = PCI_REVISION( 518 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 519 #endif 520 521 idedma_ctl = 0; 522 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 523 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 524 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 525 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 526 527 /* setup DMA if needed */ 528 pciide_channel_dma_setup(cp); 529 530 for (drive = 0; drive < 2; drive++) { 531 drvp = &chp->ch_drive[drive]; 532 /* If no drive, skip */ 533 if ((drvp->drive_flags & DRIVE) == 0) 534 continue; 535 /* add timing values, setup DMA if needed */ 536 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 537 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 538 mode = drvp->PIO_mode; 539 goto pio; 540 } 541 if ((atac->atac_cap & ATAC_CAP_UDMA) && 542 (drvp->drive_flags & DRIVE_UDMA)) { 543 /* use Ultra/DMA */ 544 s = splbio(); 545 drvp->drive_flags &= ~DRIVE_DMA; 546 splx(s); 547 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 548 APO_UDMA_EN_MTH(chp->ch_channel, drive); 549 switch (PCI_VENDOR(sc->sc_pci_id)) { 550 case PCI_VENDOR_VIATECH: 551 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 552 /* 8233a */ 553 udmatim_reg |= APO_UDMA_TIME( 554 chp->ch_channel, 555 drive, 556 via_udma133_tim[drvp->UDMA_mode]); 557 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 558 /* 686b */ 559 udmatim_reg |= APO_UDMA_TIME( 560 chp->ch_channel, 561 drive, 562 via_udma100_tim[drvp->UDMA_mode]); 563 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 564 /* 596b or 686a */ 565 udmatim_reg |= APO_UDMA_CLK66( 566 chp->ch_channel); 567 udmatim_reg |= APO_UDMA_TIME( 568 chp->ch_channel, 569 drive, 570 via_udma66_tim[drvp->UDMA_mode]); 571 } else { 572 /* 596a or 586b */ 573 udmatim_reg |= APO_UDMA_TIME( 574 chp->ch_channel, 575 drive, 576 via_udma33_tim[drvp->UDMA_mode]); 577 } 578 break; 579 case PCI_VENDOR_AMD: 580 case PCI_VENDOR_NVIDIA: 581 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 582 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 583 break; 584 } 585 /* can use PIO timings, MW DMA unused */ 586 mode = drvp->PIO_mode; 587 } else { 588 /* use Multiword DMA, but only if revision is OK */ 589 s = splbio(); 590 drvp->drive_flags &= ~DRIVE_UDMA; 591 splx(s); 592 #ifndef PCIIDE_AMD756_ENABLEDMA 593 /* 594 * The workaround doesn't seem to be necessary 595 * with all drives, so it can be disabled by 596 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 597 * triggered. 598 */ 599 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 600 sc->sc_pp->ide_product == 601 PCI_PRODUCT_AMD_PBC756_IDE && 602 AMD756_CHIPREV_DISABLEDMA(rev)) { 603 aprint_normal( 604 "%s:%d:%d: multi-word DMA disabled due " 605 "to chip revision\n", 606 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 607 chp->ch_channel, drive); 608 mode = drvp->PIO_mode; 609 s = splbio(); 610 drvp->drive_flags &= ~DRIVE_DMA; 611 splx(s); 612 goto pio; 613 } 614 #endif 615 /* mode = min(pio, dma+2) */ 616 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 617 mode = drvp->PIO_mode; 618 else 619 mode = drvp->DMA_mode + 2; 620 } 621 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 622 623 pio: /* setup PIO mode */ 624 if (mode <= 2) { 625 drvp->DMA_mode = 0; 626 drvp->PIO_mode = 0; 627 mode = 0; 628 } else { 629 drvp->PIO_mode = mode; 630 drvp->DMA_mode = mode - 2; 631 } 632 datatim_reg |= 633 APO_DATATIM_PULSE(chp->ch_channel, drive, 634 apollo_pio_set[mode]) | 635 APO_DATATIM_RECOV(chp->ch_channel, drive, 636 apollo_pio_rec[mode]); 637 } 638 if (idedma_ctl != 0) { 639 /* Add software bits in status register */ 640 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 641 idedma_ctl); 642 } 643 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 644 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 645 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 646 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 647 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 648 } 649 650 static int 651 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 652 { 653 bus_size_t satasize; 654 int maptype, ret; 655 656 if (pciide_chipen(sc, pa) == 0) 657 return 0; 658 659 aprint_normal("%s: bus-master DMA support present", 660 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 661 pciide_mapreg_dma(sc, pa); 662 aprint_normal("\n"); 663 664 if (sc->sc_dma_ok) { 665 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 666 sc->sc_wdcdev.irqack = pciide_irqack; 667 } 668 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 669 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 670 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 671 672 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 673 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 674 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 675 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 676 677 wdc_allocate_regs(&sc->sc_wdcdev); 678 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 679 PCI_MAPREG_START + 0x14); 680 switch(maptype) { 681 case PCI_MAPREG_TYPE_IO: 682 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 683 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 684 NULL, &satasize); 685 break; 686 case PCI_MAPREG_MEM_TYPE_32BIT: 687 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 688 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 689 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 690 NULL, &satasize); 691 break; 692 default: 693 aprint_error("%s: couldn't map sata regs, unsupported" 694 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 695 maptype); 696 return 0; 697 } 698 if (ret != 0) { 699 aprint_error("%s: couldn't map sata regs\n", 700 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 701 return 0; 702 } 703 return 1; 704 } 705 706 static void 707 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 708 int satareg_shift) 709 { 710 struct pciide_channel *cp; 711 struct ata_channel *wdc_cp; 712 struct wdc_regs *wdr; 713 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 714 int channel; 715 bus_size_t cmdsize, ctlsize; 716 717 if (via_sata_chip_map_common(sc, pa) == 0) 718 return; 719 720 if (interface == 0) { 721 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 722 DEBUG_PROBE); 723 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 724 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 725 } 726 727 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 728 channel++) { 729 cp = &sc->pciide_channels[channel]; 730 if (pciide_chansetup(sc, channel, interface) == 0) 731 continue; 732 wdc_cp = &cp->ata_channel; 733 wdr = CHAN_TO_WDC_REGS(wdc_cp); 734 wdr->sata_iot = sc->sc_ba5_st; 735 wdr->sata_baseioh = sc->sc_ba5_sh; 736 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 737 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 738 &wdr->sata_status) != 0) { 739 aprint_error("%s: couldn't map channel %d " 740 "sata_status regs\n", 741 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 742 wdc_cp->ch_channel); 743 continue; 744 } 745 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 746 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 747 &wdr->sata_error) != 0) { 748 aprint_error("%s: couldn't map channel %d " 749 "sata_error regs\n", 750 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 751 wdc_cp->ch_channel); 752 continue; 753 } 754 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 755 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 756 &wdr->sata_control) != 0) { 757 aprint_error("%s: couldn't map channel %d " 758 "sata_control regs\n", 759 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 760 wdc_cp->ch_channel); 761 continue; 762 } 763 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 764 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 765 pciide_pci_intr); 766 } 767 } 768 769 static void 770 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 771 { 772 via_sata_chip_map(sc, pa, 0); 773 } 774 775 static void 776 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 777 { 778 via_sata_chip_map(sc, pa, 6); 779 } 780 781 static void 782 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 783 { 784 via_sata_chip_map(sc, pa, 7); 785 } 786 787 static void 788 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 789 { 790 struct pciide_channel *cp; 791 struct ata_channel *wdc_cp; 792 struct wdc_regs *wdr; 793 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 794 int channel; 795 bus_size_t cmdsize; 796 pci_intr_handle_t intrhandle; 797 const char *intrstr; 798 int i; 799 800 if (via_sata_chip_map_common(sc, pa) == 0) 801 return; 802 803 if (interface == 0) { 804 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 805 DEBUG_PROBE); 806 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 807 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 808 } 809 810 if (pci_intr_map(pa, &intrhandle) != 0) { 811 aprint_error("%s: couldn't map native-PCI interrupt\n", 812 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 813 return; 814 } 815 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 816 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 817 intrhandle, IPL_BIO, pciide_pci_intr, sc); 818 if (sc->sc_pci_ih == NULL) { 819 aprint_error( 820 "%s: couldn't establish native-PCI interrupt", 821 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 822 if (intrstr != NULL) 823 aprint_error(" at %s", intrstr); 824 aprint_error("\n"); 825 return; 826 } 827 aprint_normal("%s: using %s for native-PCI interrupt\n", 828 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 829 intrstr ? intrstr : "unknown interrupt"); 830 831 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 832 channel++) { 833 cp = &sc->pciide_channels[channel]; 834 if (pciide_chansetup(sc, channel, interface) == 0) 835 continue; 836 cp->ata_channel.ch_ndrive = 1; 837 wdc_cp = &cp->ata_channel; 838 wdr = CHAN_TO_WDC_REGS(wdc_cp); 839 840 wdr->sata_iot = sc->sc_ba5_st; 841 wdr->sata_baseioh = sc->sc_ba5_sh; 842 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 843 (wdc_cp->ch_channel << 6) + 0x0, 1, 844 &wdr->sata_status) != 0) { 845 aprint_error("%s: couldn't map channel %d " 846 "sata_status regs\n", 847 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 848 wdc_cp->ch_channel); 849 continue; 850 } 851 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 852 (wdc_cp->ch_channel << 6) + 0x4, 1, 853 &wdr->sata_error) != 0) { 854 aprint_error("%s: couldn't map channel %d " 855 "sata_error regs\n", 856 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 857 wdc_cp->ch_channel); 858 continue; 859 } 860 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 861 (wdc_cp->ch_channel << 6) + 0x8, 1, 862 &wdr->sata_control) != 0) { 863 aprint_error("%s: couldn't map channel %d " 864 "sata_control regs\n", 865 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 866 wdc_cp->ch_channel); 867 continue; 868 } 869 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 870 871 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 872 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 873 NULL, &cmdsize) != 0) { 874 aprint_error("%s: couldn't map %s channel regs\n", 875 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 876 cp->name); 877 } 878 wdr->ctl_iot = wdr->cmd_iot; 879 for (i = 0; i < WDC_NREG; i++) { 880 if (bus_space_subregion(wdr->cmd_iot, 881 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 882 &wdr->cmd_iohs[i]) != 0) { 883 aprint_error("%s: couldn't subregion %s " 884 "channel cmd regs\n", 885 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 886 cp->name); 887 return; 888 } 889 } 890 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 891 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 892 aprint_error("%s: couldn't map channel %d ctl regs\n", 893 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 894 return; 895 } 896 wdc_init_shadow_regs(wdc_cp); 897 wdcattach(wdc_cp); 898 } 899 } 900
Indexes created Sun Oct 19 02:09:48 GMT 2025