viaide.c revision 1.34
1 /* $NetBSD: viaide.c,v 1.34 2006/10/12 01:31:33 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.34 2006/10/12 01:31:33 christos Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_sata_chip_map(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_setup_channel(struct ata_channel *); 50 51 static int viaide_match(struct device *, struct cfdata *, void *); 52 static void viaide_attach(struct device *, struct device *, void *); 53 static const struct pciide_product_desc * 54 viaide_lookup(pcireg_t); 55 56 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 57 viaide_match, viaide_attach, NULL, NULL); 58 59 static const struct pciide_product_desc pciide_amd_products[] = { 60 { PCI_PRODUCT_AMD_PBC756_IDE, 61 0, 62 "Advanced Micro Devices AMD756 IDE Controller", 63 via_chip_map 64 }, 65 { PCI_PRODUCT_AMD_PBC766_IDE, 66 0, 67 "Advanced Micro Devices AMD766 IDE Controller", 68 via_chip_map 69 }, 70 { PCI_PRODUCT_AMD_PBC768_IDE, 71 0, 72 "Advanced Micro Devices AMD768 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC8111_IDE, 76 0, 77 "Advanced Micro Devices AMD8111 IDE Controller", 78 via_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static const struct pciide_product_desc pciide_nvidia_products[] = { 88 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 89 0, 90 "NVIDIA nForce IDE Controller", 91 via_chip_map 92 }, 93 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 94 0, 95 "NVIDIA nForce2 IDE Controller", 96 via_chip_map 97 }, 98 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 99 0, 100 "NVIDIA nForce2 Ultra 400 IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 104 0, 105 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 106 via_sata_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 109 0, 110 "NVIDIA nForce3 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 114 0, 115 "NVIDIA nForce3 250 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 119 0, 120 "NVIDIA nForce3 250 Serial ATA Controller", 121 via_sata_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 124 0, 125 "NVIDIA nForce3 250 Serial ATA Controller", 126 via_sata_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 129 0, 130 "NVIDIA nForce4 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 134 0, 135 "NVIDIA nForce4 Serial ATA Controller", 136 via_sata_chip_map 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 139 0, 140 "NVIDIA nForce4 Serial ATA Controller", 141 via_sata_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 144 0, 145 "NVIDIA nForce430 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 149 0, 150 "NVIDIA nForce430 Serial ATA Controller", 151 via_sata_chip_map 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 154 0, 155 "NVIDIA nForce430 Serial ATA Controller", 156 via_sata_chip_map 157 }, 158 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 159 0, 160 "NVIDIA MCP04 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 164 0, 165 "NVIDIA MCP04 Serial ATA Controller", 166 via_sata_chip_map 167 }, 168 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 169 0, 170 "NVIDIA MCP04 Serial ATA Controller", 171 via_sata_chip_map 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 174 0, 175 "NVIDIA MCP55 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 179 0, 180 "NVIDIA MCP55 Serial ATA Controller", 181 via_sata_chip_map 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 184 0, 185 "NVIDIA MCP55 Serial ATA Controller", 186 via_sata_chip_map 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 189 0, 190 "NVIDIA MCP61 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 194 0, 195 "NVIDIA MCP65 IDE Controller", 196 via_chip_map 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 199 0, 200 "NVIDIA MCP61 Serial ATA Controller", 201 via_sata_chip_map 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 204 0, 205 "NVIDIA MCP61 Serial ATA Controller", 206 via_sata_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 209 0, 210 "NVIDIA MCP61 Serial ATA Controller", 211 via_sata_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 214 0, 215 "NVIDIA MCP65 Serial ATA Controller", 216 via_sata_chip_map 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 219 0, 220 "NVIDIA MCP65 Serial ATA Controller", 221 via_sata_chip_map 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 224 0, 225 "NVIDIA MCP65 Serial ATA Controller", 226 via_sata_chip_map 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map 232 }, 233 { 0, 234 0, 235 NULL, 236 NULL 237 } 238 }; 239 240 static const struct pciide_product_desc pciide_via_products[] = { 241 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 242 0, 243 NULL, 244 via_chip_map, 245 }, 246 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 247 0, 248 NULL, 249 via_chip_map, 250 }, 251 { PCI_PRODUCT_VIATECH_VT6421_RAID, 252 0, 253 "VIA Technologies VT6421 Serial RAID Controller", 254 via_sata_chip_map, 255 }, 256 { PCI_PRODUCT_VIATECH_VT8237_SATA, 257 0, 258 "VIA Technologies VT8237 SATA Controller", 259 via_sata_chip_map, 260 }, 261 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 262 0, 263 "VIA Technologies VT8237R SATA Controller", 264 via_sata_chip_map, 265 }, 266 { 0, 267 0, 268 NULL, 269 NULL 270 } 271 }; 272 273 static const struct pciide_product_desc * 274 viaide_lookup(pcireg_t id) 275 { 276 277 switch (PCI_VENDOR(id)) { 278 case PCI_VENDOR_VIATECH: 279 return (pciide_lookup_product(id, pciide_via_products)); 280 281 case PCI_VENDOR_AMD: 282 return (pciide_lookup_product(id, pciide_amd_products)); 283 284 case PCI_VENDOR_NVIDIA: 285 return (pciide_lookup_product(id, pciide_nvidia_products)); 286 } 287 return (NULL); 288 } 289 290 static int 291 viaide_match(struct device *parent __unused, struct cfdata *match __unused, 292 void *aux) 293 { 294 struct pci_attach_args *pa = aux; 295 296 if (viaide_lookup(pa->pa_id) != NULL) 297 return (2); 298 return (0); 299 } 300 301 static void 302 viaide_attach(struct device *parent __unused, struct device *self, void *aux) 303 { 304 struct pci_attach_args *pa = aux; 305 struct pciide_softc *sc = (struct pciide_softc *)self; 306 const struct pciide_product_desc *pp; 307 308 pp = viaide_lookup(pa->pa_id); 309 if (pp == NULL) 310 panic("viaide_attach"); 311 pciide_common_attach(sc, pa, pp); 312 } 313 314 static int 315 via_pcib_match(struct pci_attach_args *pa) 316 { 317 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 318 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 319 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 320 return (1); 321 return 0; 322 } 323 324 static void 325 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 326 { 327 struct pciide_channel *cp; 328 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 329 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 330 int channel; 331 u_int32_t ideconf; 332 bus_size_t cmdsize, ctlsize; 333 pcireg_t pcib_id, pcib_class; 334 struct pci_attach_args pcib_pa; 335 336 if (pciide_chipen(sc, pa) == 0) 337 return; 338 339 switch (vendor) { 340 case PCI_VENDOR_VIATECH: 341 /* 342 * get a PCI tag for the ISA bridge. 343 */ 344 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 345 goto unknown; 346 pcib_id = pcib_pa.pa_id; 347 pcib_class = pcib_pa.pa_class; 348 aprint_normal("%s: VIA Technologies ", 349 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 350 switch (PCI_PRODUCT(pcib_id)) { 351 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 352 aprint_normal("VT82C586 (Apollo VP) "); 353 if(PCI_REVISION(pcib_class) >= 0x02) { 354 aprint_normal("ATA33 controller\n"); 355 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 356 } else { 357 aprint_normal("controller\n"); 358 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 359 } 360 break; 361 case PCI_PRODUCT_VIATECH_VT82C596A: 362 aprint_normal("VT82C596A (Apollo Pro) "); 363 if (PCI_REVISION(pcib_class) >= 0x12) { 364 aprint_normal("ATA66 controller\n"); 365 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 366 } else { 367 aprint_normal("ATA33 controller\n"); 368 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 369 } 370 break; 371 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 372 aprint_normal("VT82C686A (Apollo KX133) "); 373 if (PCI_REVISION(pcib_class) >= 0x40) { 374 aprint_normal("ATA100 controller\n"); 375 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 376 } else { 377 aprint_normal("ATA66 controller\n"); 378 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 379 } 380 break; 381 case PCI_PRODUCT_VIATECH_VT8231: 382 aprint_normal("VT8231 ATA100 controller\n"); 383 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 384 break; 385 case PCI_PRODUCT_VIATECH_VT8233: 386 aprint_normal("VT8233 ATA100 controller\n"); 387 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 388 break; 389 case PCI_PRODUCT_VIATECH_VT8233A: 390 aprint_normal("VT8233A ATA133 controller\n"); 391 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 392 break; 393 case PCI_PRODUCT_VIATECH_VT8235: 394 aprint_normal("VT8235 ATA133 controller\n"); 395 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 396 break; 397 case PCI_PRODUCT_VIATECH_VT8237: 398 aprint_normal("VT8237 ATA133 controller\n"); 399 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 400 break; 401 default: 402 unknown: 403 aprint_normal("unknown VIA ATA controller\n"); 404 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 405 } 406 sc->sc_apo_regbase = APO_VIA_REGBASE; 407 break; 408 case PCI_VENDOR_AMD: 409 switch (sc->sc_pp->ide_product) { 410 case PCI_PRODUCT_AMD_PBC8111_IDE: 411 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 412 break; 413 case PCI_PRODUCT_AMD_PBC766_IDE: 414 case PCI_PRODUCT_AMD_PBC768_IDE: 415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 416 break; 417 default: 418 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 419 } 420 sc->sc_apo_regbase = APO_AMD_REGBASE; 421 break; 422 case PCI_VENDOR_NVIDIA: 423 switch (sc->sc_pp->ide_product) { 424 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 425 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 426 break; 427 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 428 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 429 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 430 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 431 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 432 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 433 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 434 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 435 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 436 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 437 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 438 break; 439 } 440 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 441 break; 442 default: 443 panic("via_chip_map: unknown vendor"); 444 } 445 446 aprint_normal("%s: bus-master DMA support present", 447 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 448 pciide_mapreg_dma(sc, pa); 449 aprint_normal("\n"); 450 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 451 if (sc->sc_dma_ok) { 452 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 453 sc->sc_wdcdev.irqack = pciide_irqack; 454 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 455 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 456 } 457 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 458 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 459 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 460 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 461 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 462 463 wdc_allocate_regs(&sc->sc_wdcdev); 464 465 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 466 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 467 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 468 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 469 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 470 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 471 DEBUG_PROBE); 472 473 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 474 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 475 channel++) { 476 cp = &sc->pciide_channels[channel]; 477 if (pciide_chansetup(sc, channel, interface) == 0) 478 continue; 479 480 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 481 aprint_normal("%s: %s channel ignored (disabled)\n", 482 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 483 cp->ata_channel.ch_flags |= ATACH_DISABLED; 484 continue; 485 } 486 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 487 pciide_pci_intr); 488 } 489 } 490 491 static void 492 via_setup_channel(struct ata_channel *chp) 493 { 494 u_int32_t udmatim_reg, datatim_reg; 495 u_int8_t idedma_ctl; 496 int mode, drive, s; 497 struct ata_drive_datas *drvp; 498 struct atac_softc *atac = chp->ch_atac; 499 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 500 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 501 #ifndef PCIIDE_AMD756_ENABLEDMA 502 int rev = PCI_REVISION( 503 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 504 #endif 505 506 idedma_ctl = 0; 507 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 508 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 509 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 510 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 511 512 /* setup DMA if needed */ 513 pciide_channel_dma_setup(cp); 514 515 for (drive = 0; drive < 2; drive++) { 516 drvp = &chp->ch_drive[drive]; 517 /* If no drive, skip */ 518 if ((drvp->drive_flags & DRIVE) == 0) 519 continue; 520 /* add timing values, setup DMA if needed */ 521 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 522 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 523 mode = drvp->PIO_mode; 524 goto pio; 525 } 526 if ((atac->atac_cap & ATAC_CAP_UDMA) && 527 (drvp->drive_flags & DRIVE_UDMA)) { 528 /* use Ultra/DMA */ 529 s = splbio(); 530 drvp->drive_flags &= ~DRIVE_DMA; 531 splx(s); 532 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 533 APO_UDMA_EN_MTH(chp->ch_channel, drive); 534 switch (PCI_VENDOR(sc->sc_pci_id)) { 535 case PCI_VENDOR_VIATECH: 536 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 537 /* 8233a */ 538 udmatim_reg |= APO_UDMA_TIME( 539 chp->ch_channel, 540 drive, 541 via_udma133_tim[drvp->UDMA_mode]); 542 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 543 /* 686b */ 544 udmatim_reg |= APO_UDMA_TIME( 545 chp->ch_channel, 546 drive, 547 via_udma100_tim[drvp->UDMA_mode]); 548 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 549 /* 596b or 686a */ 550 udmatim_reg |= APO_UDMA_CLK66( 551 chp->ch_channel); 552 udmatim_reg |= APO_UDMA_TIME( 553 chp->ch_channel, 554 drive, 555 via_udma66_tim[drvp->UDMA_mode]); 556 } else { 557 /* 596a or 586b */ 558 udmatim_reg |= APO_UDMA_TIME( 559 chp->ch_channel, 560 drive, 561 via_udma33_tim[drvp->UDMA_mode]); 562 } 563 break; 564 case PCI_VENDOR_AMD: 565 case PCI_VENDOR_NVIDIA: 566 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 567 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 568 break; 569 } 570 /* can use PIO timings, MW DMA unused */ 571 mode = drvp->PIO_mode; 572 } else { 573 /* use Multiword DMA, but only if revision is OK */ 574 s = splbio(); 575 drvp->drive_flags &= ~DRIVE_UDMA; 576 splx(s); 577 #ifndef PCIIDE_AMD756_ENABLEDMA 578 /* 579 * The workaround doesn't seem to be necessary 580 * with all drives, so it can be disabled by 581 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 582 * triggered. 583 */ 584 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 585 sc->sc_pp->ide_product == 586 PCI_PRODUCT_AMD_PBC756_IDE && 587 AMD756_CHIPREV_DISABLEDMA(rev)) { 588 aprint_normal( 589 "%s:%d:%d: multi-word DMA disabled due " 590 "to chip revision\n", 591 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 592 chp->ch_channel, drive); 593 mode = drvp->PIO_mode; 594 s = splbio(); 595 drvp->drive_flags &= ~DRIVE_DMA; 596 splx(s); 597 goto pio; 598 } 599 #endif 600 /* mode = min(pio, dma+2) */ 601 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 602 mode = drvp->PIO_mode; 603 else 604 mode = drvp->DMA_mode + 2; 605 } 606 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 607 608 pio: /* setup PIO mode */ 609 if (mode <= 2) { 610 drvp->DMA_mode = 0; 611 drvp->PIO_mode = 0; 612 mode = 0; 613 } else { 614 drvp->PIO_mode = mode; 615 drvp->DMA_mode = mode - 2; 616 } 617 datatim_reg |= 618 APO_DATATIM_PULSE(chp->ch_channel, drive, 619 apollo_pio_set[mode]) | 620 APO_DATATIM_RECOV(chp->ch_channel, drive, 621 apollo_pio_rec[mode]); 622 } 623 if (idedma_ctl != 0) { 624 /* Add software bits in status register */ 625 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 626 idedma_ctl); 627 } 628 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 629 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 630 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 631 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 632 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 633 } 634 635 static void 636 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 637 { 638 struct pciide_channel *cp; 639 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 640 int channel; 641 bus_size_t cmdsize, ctlsize; 642 643 if (pciide_chipen(sc, pa) == 0) 644 return; 645 646 if (interface == 0) { 647 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 648 DEBUG_PROBE); 649 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 650 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 651 } 652 653 aprint_normal("%s: bus-master DMA support present", 654 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 655 pciide_mapreg_dma(sc, pa); 656 aprint_normal("\n"); 657 658 if (sc->sc_dma_ok) { 659 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 660 sc->sc_wdcdev.irqack = pciide_irqack; 661 } 662 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 663 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 664 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 665 666 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 667 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 668 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 669 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 670 671 wdc_allocate_regs(&sc->sc_wdcdev); 672 673 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 674 channel++) { 675 cp = &sc->pciide_channels[channel]; 676 if (pciide_chansetup(sc, channel, interface) == 0) 677 continue; 678 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 679 pciide_pci_intr); 680 } 681 } 682
Indexes created Sat Oct 18 17:09:52 GMT 2025