viaide.c revision 1.37.2.2
1 /* $NetBSD: viaide.c,v 1.37.2.2 2007/03/31 16:27:56 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.37.2.2 2007/03/31 16:27:56 bouyer Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { 0, 91 0, 92 NULL, 93 NULL 94 } 95 }; 96 97 static const struct pciide_product_desc pciide_nvidia_products[] = { 98 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 99 0, 100 "NVIDIA nForce IDE Controller", 101 via_chip_map 102 }, 103 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 104 0, 105 "NVIDIA nForce2 IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 109 0, 110 "NVIDIA nForce2 Ultra 400 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 114 0, 115 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 116 via_sata_chip_map_6 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 119 0, 120 "NVIDIA nForce3 IDE Controller", 121 via_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 124 0, 125 "NVIDIA nForce3 250 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 129 0, 130 "NVIDIA nForce3 250 Serial ATA Controller", 131 via_sata_chip_map_6 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 139 0, 140 "NVIDIA nForce4 IDE Controller", 141 via_chip_map 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 144 0, 145 "NVIDIA nForce4 Serial ATA Controller", 146 via_sata_chip_map_6 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 154 0, 155 "NVIDIA nForce430 IDE Controller", 156 via_chip_map 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 159 0, 160 "NVIDIA nForce430 Serial ATA Controller", 161 via_sata_chip_map_6 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 169 0, 170 "NVIDIA MCP04 IDE Controller", 171 via_chip_map 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 174 0, 175 "NVIDIA MCP04 Serial ATA Controller", 176 via_sata_chip_map_6 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 184 0, 185 "NVIDIA MCP55 IDE Controller", 186 via_chip_map 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 189 0, 190 "NVIDIA MCP55 Serial ATA Controller", 191 via_sata_chip_map_6 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 199 0, 200 "NVIDIA MCP61 IDE Controller", 201 via_chip_map 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 204 0, 205 "NVIDIA MCP65 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 209 0, 210 "NVIDIA MCP61 Serial ATA Controller", 211 via_sata_chip_map_6 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 214 0, 215 "NVIDIA MCP61 Serial ATA Controller", 216 via_sata_chip_map_6 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 219 0, 220 "NVIDIA MCP61 Serial ATA Controller", 221 via_sata_chip_map_6 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 224 0, 225 "NVIDIA MCP65 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 234 0, 235 "NVIDIA MCP65 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { 0, 244 0, 245 NULL, 246 NULL 247 } 248 }; 249 250 static const struct pciide_product_desc pciide_via_products[] = { 251 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 252 0, 253 NULL, 254 via_chip_map, 255 }, 256 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 257 0, 258 NULL, 259 via_chip_map, 260 }, 261 { PCI_PRODUCT_VIATECH_VT6421_RAID, 262 0, 263 "VIA Technologies VT6421 Serial RAID Controller", 264 via_sata_chip_map_new, 265 }, 266 { PCI_PRODUCT_VIATECH_VT8237_SATA, 267 0, 268 "VIA Technologies VT8237 SATA Controller", 269 via_sata_chip_map_7, 270 }, 271 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 272 0, 273 "VIA Technologies VT8237A SATA Controller", 274 via_sata_chip_map_7, 275 }, 276 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 277 0, 278 "VIA Technologies VT8237R SATA Controller", 279 via_sata_chip_map_0, 280 }, 281 { 0, 282 0, 283 NULL, 284 NULL 285 } 286 }; 287 288 static const struct pciide_product_desc * 289 viaide_lookup(pcireg_t id) 290 { 291 292 switch (PCI_VENDOR(id)) { 293 case PCI_VENDOR_VIATECH: 294 return (pciide_lookup_product(id, pciide_via_products)); 295 296 case PCI_VENDOR_AMD: 297 return (pciide_lookup_product(id, pciide_amd_products)); 298 299 case PCI_VENDOR_NVIDIA: 300 return (pciide_lookup_product(id, pciide_nvidia_products)); 301 } 302 return (NULL); 303 } 304 305 static int 306 viaide_match(struct device *parent, struct cfdata *match, 307 void *aux) 308 { 309 struct pci_attach_args *pa = aux; 310 311 if (viaide_lookup(pa->pa_id) != NULL) 312 return (2); 313 return (0); 314 } 315 316 static void 317 viaide_attach(struct device *parent, struct device *self, void *aux) 318 { 319 struct pci_attach_args *pa = aux; 320 struct pciide_softc *sc = (struct pciide_softc *)self; 321 const struct pciide_product_desc *pp; 322 323 pp = viaide_lookup(pa->pa_id); 324 if (pp == NULL) 325 panic("viaide_attach"); 326 pciide_common_attach(sc, pa, pp); 327 } 328 329 static int 330 via_pcib_match(struct pci_attach_args *pa) 331 { 332 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 333 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 334 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 335 return (1); 336 return 0; 337 } 338 339 static void 340 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 341 { 342 struct pciide_channel *cp; 343 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 344 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 345 int channel; 346 u_int32_t ideconf; 347 bus_size_t cmdsize, ctlsize; 348 pcireg_t pcib_id, pcib_class; 349 struct pci_attach_args pcib_pa; 350 351 if (pciide_chipen(sc, pa) == 0) 352 return; 353 354 switch (vendor) { 355 case PCI_VENDOR_VIATECH: 356 /* 357 * get a PCI tag for the ISA bridge. 358 */ 359 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 360 goto unknown; 361 pcib_id = pcib_pa.pa_id; 362 pcib_class = pcib_pa.pa_class; 363 aprint_normal("%s: VIA Technologies ", 364 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 365 switch (PCI_PRODUCT(pcib_id)) { 366 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 367 aprint_normal("VT82C586 (Apollo VP) "); 368 if(PCI_REVISION(pcib_class) >= 0x02) { 369 aprint_normal("ATA33 controller\n"); 370 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 371 } else { 372 aprint_normal("controller\n"); 373 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 374 } 375 break; 376 case PCI_PRODUCT_VIATECH_VT82C596A: 377 aprint_normal("VT82C596A (Apollo Pro) "); 378 if (PCI_REVISION(pcib_class) >= 0x12) { 379 aprint_normal("ATA66 controller\n"); 380 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 381 } else { 382 aprint_normal("ATA33 controller\n"); 383 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 384 } 385 break; 386 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 387 aprint_normal("VT82C686A (Apollo KX133) "); 388 if (PCI_REVISION(pcib_class) >= 0x40) { 389 aprint_normal("ATA100 controller\n"); 390 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 391 } else { 392 aprint_normal("ATA66 controller\n"); 393 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 394 } 395 break; 396 case PCI_PRODUCT_VIATECH_VT8231: 397 aprint_normal("VT8231 ATA100 controller\n"); 398 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 399 break; 400 case PCI_PRODUCT_VIATECH_VT8233: 401 aprint_normal("VT8233 ATA100 controller\n"); 402 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 403 break; 404 case PCI_PRODUCT_VIATECH_VT8233A: 405 aprint_normal("VT8233A ATA133 controller\n"); 406 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 407 break; 408 case PCI_PRODUCT_VIATECH_VT8235: 409 aprint_normal("VT8235 ATA133 controller\n"); 410 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 411 break; 412 case PCI_PRODUCT_VIATECH_VT8237: 413 aprint_normal("VT8237 ATA133 controller\n"); 414 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 415 break; 416 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 417 aprint_normal("VT8237A ATA133 controller\n"); 418 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 419 break; 420 default: 421 unknown: 422 aprint_normal("unknown VIA ATA controller\n"); 423 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 424 } 425 sc->sc_apo_regbase = APO_VIA_REGBASE; 426 break; 427 case PCI_VENDOR_AMD: 428 switch (sc->sc_pp->ide_product) { 429 case PCI_PRODUCT_AMD_PBC8111_IDE: 430 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 431 break; 432 case PCI_PRODUCT_AMD_PBC766_IDE: 433 case PCI_PRODUCT_AMD_PBC768_IDE: 434 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 435 break; 436 default: 437 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 438 } 439 sc->sc_apo_regbase = APO_AMD_REGBASE; 440 break; 441 case PCI_VENDOR_NVIDIA: 442 switch (sc->sc_pp->ide_product) { 443 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 444 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 445 break; 446 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 447 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 448 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 449 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 450 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 451 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 452 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 453 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 454 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 455 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 456 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 457 break; 458 } 459 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 460 break; 461 default: 462 panic("via_chip_map: unknown vendor"); 463 } 464 465 aprint_normal("%s: bus-master DMA support present", 466 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 467 pciide_mapreg_dma(sc, pa); 468 aprint_normal("\n"); 469 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 470 if (sc->sc_dma_ok) { 471 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 472 sc->sc_wdcdev.irqack = pciide_irqack; 473 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 474 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 475 } 476 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 477 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 478 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 479 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 480 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 481 482 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 483 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 484 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 485 486 wdc_allocate_regs(&sc->sc_wdcdev); 487 488 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 489 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 490 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 491 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 492 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 493 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 494 DEBUG_PROBE); 495 496 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 497 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 498 channel++) { 499 cp = &sc->pciide_channels[channel]; 500 if (pciide_chansetup(sc, channel, interface) == 0) 501 continue; 502 503 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 504 aprint_normal("%s: %s channel ignored (disabled)\n", 505 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 506 cp->ata_channel.ch_flags |= ATACH_DISABLED; 507 continue; 508 } 509 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 510 pciide_pci_intr); 511 } 512 } 513 514 static void 515 via_setup_channel(struct ata_channel *chp) 516 { 517 u_int32_t udmatim_reg, datatim_reg; 518 u_int8_t idedma_ctl; 519 int mode, drive, s; 520 struct ata_drive_datas *drvp; 521 struct atac_softc *atac = chp->ch_atac; 522 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 523 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 524 #ifndef PCIIDE_AMD756_ENABLEDMA 525 int rev = PCI_REVISION( 526 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 527 #endif 528 529 idedma_ctl = 0; 530 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 531 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 532 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 533 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 534 535 /* setup DMA if needed */ 536 pciide_channel_dma_setup(cp); 537 538 for (drive = 0; drive < 2; drive++) { 539 drvp = &chp->ch_drive[drive]; 540 /* If no drive, skip */ 541 if ((drvp->drive_flags & DRIVE) == 0) 542 continue; 543 /* add timing values, setup DMA if needed */ 544 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 545 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 546 mode = drvp->PIO_mode; 547 goto pio; 548 } 549 if ((atac->atac_cap & ATAC_CAP_UDMA) && 550 (drvp->drive_flags & DRIVE_UDMA)) { 551 /* use Ultra/DMA */ 552 s = splbio(); 553 drvp->drive_flags &= ~DRIVE_DMA; 554 splx(s); 555 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 556 APO_UDMA_EN_MTH(chp->ch_channel, drive); 557 switch (PCI_VENDOR(sc->sc_pci_id)) { 558 case PCI_VENDOR_VIATECH: 559 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 560 /* 8233a */ 561 udmatim_reg |= APO_UDMA_TIME( 562 chp->ch_channel, 563 drive, 564 via_udma133_tim[drvp->UDMA_mode]); 565 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 566 /* 686b */ 567 udmatim_reg |= APO_UDMA_TIME( 568 chp->ch_channel, 569 drive, 570 via_udma100_tim[drvp->UDMA_mode]); 571 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 572 /* 596b or 686a */ 573 udmatim_reg |= APO_UDMA_CLK66( 574 chp->ch_channel); 575 udmatim_reg |= APO_UDMA_TIME( 576 chp->ch_channel, 577 drive, 578 via_udma66_tim[drvp->UDMA_mode]); 579 } else { 580 /* 596a or 586b */ 581 udmatim_reg |= APO_UDMA_TIME( 582 chp->ch_channel, 583 drive, 584 via_udma33_tim[drvp->UDMA_mode]); 585 } 586 break; 587 case PCI_VENDOR_AMD: 588 case PCI_VENDOR_NVIDIA: 589 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 590 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 591 break; 592 } 593 /* can use PIO timings, MW DMA unused */ 594 mode = drvp->PIO_mode; 595 } else { 596 /* use Multiword DMA, but only if revision is OK */ 597 s = splbio(); 598 drvp->drive_flags &= ~DRIVE_UDMA; 599 splx(s); 600 #ifndef PCIIDE_AMD756_ENABLEDMA 601 /* 602 * The workaround doesn't seem to be necessary 603 * with all drives, so it can be disabled by 604 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 605 * triggered. 606 */ 607 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 608 sc->sc_pp->ide_product == 609 PCI_PRODUCT_AMD_PBC756_IDE && 610 AMD756_CHIPREV_DISABLEDMA(rev)) { 611 aprint_normal( 612 "%s:%d:%d: multi-word DMA disabled due " 613 "to chip revision\n", 614 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 615 chp->ch_channel, drive); 616 mode = drvp->PIO_mode; 617 s = splbio(); 618 drvp->drive_flags &= ~DRIVE_DMA; 619 splx(s); 620 goto pio; 621 } 622 #endif 623 /* mode = min(pio, dma+2) */ 624 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 625 mode = drvp->PIO_mode; 626 else 627 mode = drvp->DMA_mode + 2; 628 } 629 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 630 631 pio: /* setup PIO mode */ 632 if (mode <= 2) { 633 drvp->DMA_mode = 0; 634 drvp->PIO_mode = 0; 635 mode = 0; 636 } else { 637 drvp->PIO_mode = mode; 638 drvp->DMA_mode = mode - 2; 639 } 640 datatim_reg |= 641 APO_DATATIM_PULSE(chp->ch_channel, drive, 642 apollo_pio_set[mode]) | 643 APO_DATATIM_RECOV(chp->ch_channel, drive, 644 apollo_pio_rec[mode]); 645 } 646 if (idedma_ctl != 0) { 647 /* Add software bits in status register */ 648 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 649 idedma_ctl); 650 } 651 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 652 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 653 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 654 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 655 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 656 } 657 658 static int 659 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 660 { 661 bus_size_t satasize; 662 int maptype, ret; 663 664 if (pciide_chipen(sc, pa) == 0) 665 return 0; 666 667 aprint_normal("%s: bus-master DMA support present", 668 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 669 pciide_mapreg_dma(sc, pa); 670 aprint_normal("\n"); 671 672 if (sc->sc_dma_ok) { 673 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 674 sc->sc_wdcdev.irqack = pciide_irqack; 675 } 676 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 677 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 678 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 679 680 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 681 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 682 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 683 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 684 685 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 686 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 687 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 688 689 wdc_allocate_regs(&sc->sc_wdcdev); 690 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 691 PCI_MAPREG_START + 0x14); 692 switch(maptype) { 693 case PCI_MAPREG_TYPE_IO: 694 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 695 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 696 NULL, &satasize); 697 break; 698 case PCI_MAPREG_MEM_TYPE_32BIT: 699 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 700 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 701 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 702 NULL, &satasize); 703 break; 704 default: 705 aprint_error("%s: couldn't map sata regs, unsupported" 706 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 707 maptype); 708 return 0; 709 } 710 if (ret != 0) { 711 aprint_error("%s: couldn't map sata regs\n", 712 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 713 return 0; 714 } 715 return 1; 716 } 717 718 static void 719 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 720 int satareg_shift) 721 { 722 struct pciide_channel *cp; 723 struct ata_channel *wdc_cp; 724 struct wdc_regs *wdr; 725 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 726 int channel; 727 bus_size_t cmdsize, ctlsize; 728 729 if (via_sata_chip_map_common(sc, pa) == 0) 730 return; 731 732 if (interface == 0) { 733 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 734 DEBUG_PROBE); 735 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 736 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 737 } 738 739 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 740 channel++) { 741 cp = &sc->pciide_channels[channel]; 742 if (pciide_chansetup(sc, channel, interface) == 0) 743 continue; 744 wdc_cp = &cp->ata_channel; 745 wdr = CHAN_TO_WDC_REGS(wdc_cp); 746 wdr->sata_iot = sc->sc_ba5_st; 747 wdr->sata_baseioh = sc->sc_ba5_sh; 748 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 749 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 750 &wdr->sata_status) != 0) { 751 aprint_error("%s: couldn't map channel %d " 752 "sata_status regs\n", 753 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 754 wdc_cp->ch_channel); 755 continue; 756 } 757 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 758 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 759 &wdr->sata_error) != 0) { 760 aprint_error("%s: couldn't map channel %d " 761 "sata_error regs\n", 762 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 763 wdc_cp->ch_channel); 764 continue; 765 } 766 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 767 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 768 &wdr->sata_control) != 0) { 769 aprint_error("%s: couldn't map channel %d " 770 "sata_control regs\n", 771 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 772 wdc_cp->ch_channel); 773 continue; 774 } 775 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 776 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 777 pciide_pci_intr); 778 } 779 } 780 781 static void 782 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 783 { 784 via_sata_chip_map(sc, pa, 0); 785 } 786 787 static void 788 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 789 { 790 via_sata_chip_map(sc, pa, 6); 791 } 792 793 static void 794 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 795 { 796 via_sata_chip_map(sc, pa, 7); 797 } 798 799 static void 800 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 801 { 802 struct pciide_channel *cp; 803 struct ata_channel *wdc_cp; 804 struct wdc_regs *wdr; 805 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 806 int channel; 807 bus_size_t cmdsize; 808 pci_intr_handle_t intrhandle; 809 const char *intrstr; 810 int i; 811 812 if (via_sata_chip_map_common(sc, pa) == 0) 813 return; 814 815 if (interface == 0) { 816 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 817 DEBUG_PROBE); 818 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 819 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 820 } 821 822 if (pci_intr_map(pa, &intrhandle) != 0) { 823 aprint_error("%s: couldn't map native-PCI interrupt\n", 824 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 825 return; 826 } 827 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 828 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 829 intrhandle, IPL_BIO, pciide_pci_intr, sc); 830 if (sc->sc_pci_ih == NULL) { 831 aprint_error( 832 "%s: couldn't establish native-PCI interrupt", 833 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 834 if (intrstr != NULL) 835 aprint_error(" at %s", intrstr); 836 aprint_error("\n"); 837 return; 838 } 839 aprint_normal("%s: using %s for native-PCI interrupt\n", 840 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 841 intrstr ? intrstr : "unknown interrupt"); 842 843 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 844 channel++) { 845 cp = &sc->pciide_channels[channel]; 846 if (pciide_chansetup(sc, channel, interface) == 0) 847 continue; 848 cp->ata_channel.ch_ndrive = 1; 849 wdc_cp = &cp->ata_channel; 850 wdr = CHAN_TO_WDC_REGS(wdc_cp); 851 852 wdr->sata_iot = sc->sc_ba5_st; 853 wdr->sata_baseioh = sc->sc_ba5_sh; 854 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 855 (wdc_cp->ch_channel << 6) + 0x0, 1, 856 &wdr->sata_status) != 0) { 857 aprint_error("%s: couldn't map channel %d " 858 "sata_status regs\n", 859 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 860 wdc_cp->ch_channel); 861 continue; 862 } 863 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 864 (wdc_cp->ch_channel << 6) + 0x4, 1, 865 &wdr->sata_error) != 0) { 866 aprint_error("%s: couldn't map channel %d " 867 "sata_error regs\n", 868 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 869 wdc_cp->ch_channel); 870 continue; 871 } 872 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 873 (wdc_cp->ch_channel << 6) + 0x8, 1, 874 &wdr->sata_control) != 0) { 875 aprint_error("%s: couldn't map channel %d " 876 "sata_control regs\n", 877 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 878 wdc_cp->ch_channel); 879 continue; 880 } 881 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 882 883 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 884 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 885 NULL, &cmdsize) != 0) { 886 aprint_error("%s: couldn't map %s channel regs\n", 887 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 888 cp->name); 889 } 890 wdr->ctl_iot = wdr->cmd_iot; 891 for (i = 0; i < WDC_NREG; i++) { 892 if (bus_space_subregion(wdr->cmd_iot, 893 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 894 &wdr->cmd_iohs[i]) != 0) { 895 aprint_error("%s: couldn't subregion %s " 896 "channel cmd regs\n", 897 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 898 cp->name); 899 return; 900 } 901 } 902 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 903 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 904 aprint_error("%s: couldn't map channel %d ctl regs\n", 905 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 906 return; 907 } 908 wdc_init_shadow_regs(wdc_cp); 909 wdcattach(wdc_cp); 910 } 911 } 912
Indexes created Wed Oct 22 13:09:56 GMT 2025