viaide.c revision 1.37.2.2.2.2
1 /* $NetBSD: viaide.c,v 1.37.2.2.2.2 2007/10/29 00:45:20 wrstuden Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.37.2.2.2.2 2007/10/29 00:45:20 wrstuden Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_AMD_CS5536_IDE, 91 0, 92 "Advanced Micro Devices CS5536 IDE Controller", 93 via_chip_map 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static const struct pciide_product_desc pciide_nvidia_products[] = { 103 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 104 0, 105 "NVIDIA nForce IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 109 0, 110 "NVIDIA nForce2 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 114 0, 115 "NVIDIA nForce2 Ultra 400 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 119 0, 120 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 121 via_sata_chip_map_6 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 124 0, 125 "NVIDIA nForce3 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 129 0, 130 "NVIDIA nForce3 250 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 139 0, 140 "NVIDIA nForce3 250 Serial ATA Controller", 141 via_sata_chip_map_6 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 144 0, 145 "NVIDIA nForce4 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 154 0, 155 "NVIDIA nForce4 Serial ATA Controller", 156 via_sata_chip_map_6 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 159 0, 160 "NVIDIA nForce430 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 169 0, 170 "NVIDIA nForce430 Serial ATA Controller", 171 via_sata_chip_map_6 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 174 0, 175 "NVIDIA MCP04 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 184 0, 185 "NVIDIA MCP04 Serial ATA Controller", 186 via_sata_chip_map_6 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 189 0, 190 "NVIDIA MCP55 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 199 0, 200 "NVIDIA MCP55 Serial ATA Controller", 201 via_sata_chip_map_6 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 204 0, 205 "NVIDIA MCP61 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 209 0, 210 "NVIDIA MCP65 IDE Controller", 211 via_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 214 0, 215 "NVIDIA MCP61 Serial ATA Controller", 216 via_sata_chip_map_6 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 219 0, 220 "NVIDIA MCP61 Serial ATA Controller", 221 via_sata_chip_map_6 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 224 0, 225 "NVIDIA MCP61 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 234 0, 235 "NVIDIA MCP65 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 244 0, 245 "NVIDIA MCP65 Serial ATA Controller", 246 via_sata_chip_map_6 247 }, 248 { 0, 249 0, 250 NULL, 251 NULL 252 } 253 }; 254 255 static const struct pciide_product_desc pciide_via_products[] = { 256 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 257 0, 258 NULL, 259 via_chip_map, 260 }, 261 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 262 0, 263 NULL, 264 via_chip_map, 265 }, 266 { PCI_PRODUCT_VIATECH_VT6421_RAID, 267 0, 268 "VIA Technologies VT6421 Serial RAID Controller", 269 via_sata_chip_map_new, 270 }, 271 { PCI_PRODUCT_VIATECH_VT8237_SATA, 272 0, 273 "VIA Technologies VT8237 SATA Controller", 274 via_sata_chip_map_7, 275 }, 276 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 277 0, 278 "VIA Technologies VT8237A SATA Controller", 279 via_sata_chip_map_7, 280 }, 281 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 282 0, 283 "VIA Technologies VT8237R SATA Controller", 284 via_sata_chip_map_0, 285 }, 286 { 0, 287 0, 288 NULL, 289 NULL 290 } 291 }; 292 293 static const struct pciide_product_desc * 294 viaide_lookup(pcireg_t id) 295 { 296 297 switch (PCI_VENDOR(id)) { 298 case PCI_VENDOR_VIATECH: 299 return (pciide_lookup_product(id, pciide_via_products)); 300 301 case PCI_VENDOR_AMD: 302 return (pciide_lookup_product(id, pciide_amd_products)); 303 304 case PCI_VENDOR_NVIDIA: 305 return (pciide_lookup_product(id, pciide_nvidia_products)); 306 } 307 return (NULL); 308 } 309 310 static int 311 viaide_match(struct device *parent, struct cfdata *match, 312 void *aux) 313 { 314 struct pci_attach_args *pa = aux; 315 316 if (viaide_lookup(pa->pa_id) != NULL) 317 return (2); 318 return (0); 319 } 320 321 static void 322 viaide_attach(struct device *parent, struct device *self, void *aux) 323 { 324 struct pci_attach_args *pa = aux; 325 struct pciide_softc *sc = (struct pciide_softc *)self; 326 const struct pciide_product_desc *pp; 327 328 pp = viaide_lookup(pa->pa_id); 329 if (pp == NULL) 330 panic("viaide_attach"); 331 pciide_common_attach(sc, pa, pp); 332 } 333 334 static int 335 via_pcib_match(struct pci_attach_args *pa) 336 { 337 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 338 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 339 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 340 return (1); 341 return 0; 342 } 343 344 static void 345 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 346 { 347 struct pciide_channel *cp; 348 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 349 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 350 int channel; 351 u_int32_t ideconf; 352 bus_size_t cmdsize, ctlsize; 353 pcireg_t pcib_id, pcib_class; 354 struct pci_attach_args pcib_pa; 355 356 if (pciide_chipen(sc, pa) == 0) 357 return; 358 359 switch (vendor) { 360 case PCI_VENDOR_VIATECH: 361 /* 362 * get a PCI tag for the ISA bridge. 363 */ 364 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 365 goto unknown; 366 pcib_id = pcib_pa.pa_id; 367 pcib_class = pcib_pa.pa_class; 368 aprint_normal("%s: VIA Technologies ", 369 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 370 switch (PCI_PRODUCT(pcib_id)) { 371 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 372 aprint_normal("VT82C586 (Apollo VP) "); 373 if(PCI_REVISION(pcib_class) >= 0x02) { 374 aprint_normal("ATA33 controller\n"); 375 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 376 } else { 377 aprint_normal("controller\n"); 378 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 379 } 380 break; 381 case PCI_PRODUCT_VIATECH_VT82C596A: 382 aprint_normal("VT82C596A (Apollo Pro) "); 383 if (PCI_REVISION(pcib_class) >= 0x12) { 384 aprint_normal("ATA66 controller\n"); 385 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 386 } else { 387 aprint_normal("ATA33 controller\n"); 388 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 389 } 390 break; 391 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 392 aprint_normal("VT82C686A (Apollo KX133) "); 393 if (PCI_REVISION(pcib_class) >= 0x40) { 394 aprint_normal("ATA100 controller\n"); 395 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 396 } else { 397 aprint_normal("ATA66 controller\n"); 398 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 399 } 400 break; 401 case PCI_PRODUCT_VIATECH_VT8231: 402 aprint_normal("VT8231 ATA100 controller\n"); 403 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 404 break; 405 case PCI_PRODUCT_VIATECH_VT8233: 406 aprint_normal("VT8233 ATA100 controller\n"); 407 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 408 break; 409 case PCI_PRODUCT_VIATECH_VT8233A: 410 aprint_normal("VT8233A ATA133 controller\n"); 411 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 412 break; 413 case PCI_PRODUCT_VIATECH_VT8235: 414 aprint_normal("VT8235 ATA133 controller\n"); 415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 416 break; 417 case PCI_PRODUCT_VIATECH_VT8237: 418 aprint_normal("VT8237 ATA133 controller\n"); 419 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 420 break; 421 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 422 aprint_normal("VT8237A ATA133 controller\n"); 423 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 424 break; 425 default: 426 unknown: 427 aprint_normal("unknown VIA ATA controller\n"); 428 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 429 } 430 sc->sc_apo_regbase = APO_VIA_REGBASE; 431 break; 432 case PCI_VENDOR_AMD: 433 switch (sc->sc_pp->ide_product) { 434 case PCI_PRODUCT_AMD_PBC8111_IDE: 435 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 436 break; 437 case PCI_PRODUCT_AMD_CS5536_IDE: 438 case PCI_PRODUCT_AMD_PBC766_IDE: 439 case PCI_PRODUCT_AMD_PBC768_IDE: 440 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 441 break; 442 default: 443 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 444 } 445 sc->sc_apo_regbase = APO_AMD_REGBASE; 446 break; 447 case PCI_VENDOR_NVIDIA: 448 switch (sc->sc_pp->ide_product) { 449 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 450 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 451 break; 452 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 453 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 454 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 455 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 456 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 457 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 458 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 459 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 460 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 461 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 462 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 463 break; 464 } 465 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 466 break; 467 default: 468 panic("via_chip_map: unknown vendor"); 469 } 470 471 aprint_normal("%s: bus-master DMA support present", 472 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 473 pciide_mapreg_dma(sc, pa); 474 aprint_normal("\n"); 475 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 476 if (sc->sc_dma_ok) { 477 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 478 sc->sc_wdcdev.irqack = pciide_irqack; 479 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 480 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 481 } 482 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 483 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 484 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 485 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 486 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 487 488 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 489 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 490 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 491 492 wdc_allocate_regs(&sc->sc_wdcdev); 493 494 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 495 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 496 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 497 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 498 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 499 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 500 DEBUG_PROBE); 501 502 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 503 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 504 channel++) { 505 cp = &sc->pciide_channels[channel]; 506 if (pciide_chansetup(sc, channel, interface) == 0) 507 continue; 508 509 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 510 aprint_normal("%s: %s channel ignored (disabled)\n", 511 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 512 cp->ata_channel.ch_flags |= ATACH_DISABLED; 513 continue; 514 } 515 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 516 pciide_pci_intr); 517 } 518 } 519 520 static void 521 via_setup_channel(struct ata_channel *chp) 522 { 523 u_int32_t udmatim_reg, datatim_reg; 524 u_int8_t idedma_ctl; 525 int mode, drive, s; 526 struct ata_drive_datas *drvp; 527 struct atac_softc *atac = chp->ch_atac; 528 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 529 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 530 #ifndef PCIIDE_AMD756_ENABLEDMA 531 int rev = PCI_REVISION( 532 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 533 #endif 534 535 idedma_ctl = 0; 536 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 537 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 538 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 539 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 540 541 /* setup DMA if needed */ 542 pciide_channel_dma_setup(cp); 543 544 for (drive = 0; drive < 2; drive++) { 545 drvp = &chp->ch_drive[drive]; 546 /* If no drive, skip */ 547 if ((drvp->drive_flags & DRIVE) == 0) 548 continue; 549 /* add timing values, setup DMA if needed */ 550 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 551 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 552 mode = drvp->PIO_mode; 553 goto pio; 554 } 555 if ((atac->atac_cap & ATAC_CAP_UDMA) && 556 (drvp->drive_flags & DRIVE_UDMA)) { 557 /* use Ultra/DMA */ 558 s = splbio(); 559 drvp->drive_flags &= ~DRIVE_DMA; 560 splx(s); 561 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 562 APO_UDMA_EN_MTH(chp->ch_channel, drive); 563 switch (PCI_VENDOR(sc->sc_pci_id)) { 564 case PCI_VENDOR_VIATECH: 565 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 566 /* 8233a */ 567 udmatim_reg |= APO_UDMA_TIME( 568 chp->ch_channel, 569 drive, 570 via_udma133_tim[drvp->UDMA_mode]); 571 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 572 /* 686b */ 573 udmatim_reg |= APO_UDMA_TIME( 574 chp->ch_channel, 575 drive, 576 via_udma100_tim[drvp->UDMA_mode]); 577 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 578 /* 596b or 686a */ 579 udmatim_reg |= APO_UDMA_CLK66( 580 chp->ch_channel); 581 udmatim_reg |= APO_UDMA_TIME( 582 chp->ch_channel, 583 drive, 584 via_udma66_tim[drvp->UDMA_mode]); 585 } else { 586 /* 596a or 586b */ 587 udmatim_reg |= APO_UDMA_TIME( 588 chp->ch_channel, 589 drive, 590 via_udma33_tim[drvp->UDMA_mode]); 591 } 592 break; 593 case PCI_VENDOR_AMD: 594 case PCI_VENDOR_NVIDIA: 595 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 596 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 597 break; 598 } 599 /* can use PIO timings, MW DMA unused */ 600 mode = drvp->PIO_mode; 601 } else { 602 /* use Multiword DMA, but only if revision is OK */ 603 s = splbio(); 604 drvp->drive_flags &= ~DRIVE_UDMA; 605 splx(s); 606 #ifndef PCIIDE_AMD756_ENABLEDMA 607 /* 608 * The workaround doesn't seem to be necessary 609 * with all drives, so it can be disabled by 610 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 611 * triggered. 612 */ 613 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 614 sc->sc_pp->ide_product == 615 PCI_PRODUCT_AMD_PBC756_IDE && 616 AMD756_CHIPREV_DISABLEDMA(rev)) { 617 aprint_normal( 618 "%s:%d:%d: multi-word DMA disabled due " 619 "to chip revision\n", 620 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 621 chp->ch_channel, drive); 622 mode = drvp->PIO_mode; 623 s = splbio(); 624 drvp->drive_flags &= ~DRIVE_DMA; 625 splx(s); 626 goto pio; 627 } 628 #endif 629 /* mode = min(pio, dma+2) */ 630 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 631 mode = drvp->PIO_mode; 632 else 633 mode = drvp->DMA_mode + 2; 634 } 635 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 636 637 pio: /* setup PIO mode */ 638 if (mode <= 2) { 639 drvp->DMA_mode = 0; 640 drvp->PIO_mode = 0; 641 mode = 0; 642 } else { 643 drvp->PIO_mode = mode; 644 drvp->DMA_mode = mode - 2; 645 } 646 datatim_reg |= 647 APO_DATATIM_PULSE(chp->ch_channel, drive, 648 apollo_pio_set[mode]) | 649 APO_DATATIM_RECOV(chp->ch_channel, drive, 650 apollo_pio_rec[mode]); 651 } 652 if (idedma_ctl != 0) { 653 /* Add software bits in status register */ 654 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 655 idedma_ctl); 656 } 657 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 658 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 659 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 660 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 661 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 662 } 663 664 static int 665 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 666 { 667 bus_size_t satasize; 668 int maptype, ret; 669 670 if (pciide_chipen(sc, pa) == 0) 671 return 0; 672 673 aprint_normal("%s: bus-master DMA support present", 674 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 675 pciide_mapreg_dma(sc, pa); 676 aprint_normal("\n"); 677 678 if (sc->sc_dma_ok) { 679 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 680 sc->sc_wdcdev.irqack = pciide_irqack; 681 } 682 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 683 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 684 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 685 686 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 687 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 688 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 689 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 690 691 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 692 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 693 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 694 695 wdc_allocate_regs(&sc->sc_wdcdev); 696 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 697 PCI_MAPREG_START + 0x14); 698 switch(maptype) { 699 case PCI_MAPREG_TYPE_IO: 700 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 701 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 702 NULL, &satasize); 703 break; 704 case PCI_MAPREG_MEM_TYPE_32BIT: 705 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 706 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 707 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 708 NULL, &satasize); 709 break; 710 default: 711 aprint_error("%s: couldn't map sata regs, unsupported" 712 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 713 maptype); 714 return 0; 715 } 716 if (ret != 0) { 717 aprint_error("%s: couldn't map sata regs\n", 718 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 719 return 0; 720 } 721 return 1; 722 } 723 724 static void 725 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 726 int satareg_shift) 727 { 728 struct pciide_channel *cp; 729 struct ata_channel *wdc_cp; 730 struct wdc_regs *wdr; 731 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 732 int channel; 733 bus_size_t cmdsize, ctlsize; 734 735 if (via_sata_chip_map_common(sc, pa) == 0) 736 return; 737 738 if (interface == 0) { 739 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 740 DEBUG_PROBE); 741 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 742 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 743 } 744 745 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 746 channel++) { 747 cp = &sc->pciide_channels[channel]; 748 if (pciide_chansetup(sc, channel, interface) == 0) 749 continue; 750 wdc_cp = &cp->ata_channel; 751 wdr = CHAN_TO_WDC_REGS(wdc_cp); 752 wdr->sata_iot = sc->sc_ba5_st; 753 wdr->sata_baseioh = sc->sc_ba5_sh; 754 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 755 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 756 &wdr->sata_status) != 0) { 757 aprint_error("%s: couldn't map channel %d " 758 "sata_status regs\n", 759 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 760 wdc_cp->ch_channel); 761 continue; 762 } 763 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 764 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 765 &wdr->sata_error) != 0) { 766 aprint_error("%s: couldn't map channel %d " 767 "sata_error regs\n", 768 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 769 wdc_cp->ch_channel); 770 continue; 771 } 772 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 773 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 774 &wdr->sata_control) != 0) { 775 aprint_error("%s: couldn't map channel %d " 776 "sata_control regs\n", 777 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 778 wdc_cp->ch_channel); 779 continue; 780 } 781 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 782 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 783 pciide_pci_intr); 784 } 785 } 786 787 static void 788 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 789 { 790 via_sata_chip_map(sc, pa, 0); 791 } 792 793 static void 794 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 795 { 796 via_sata_chip_map(sc, pa, 6); 797 } 798 799 static void 800 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 801 { 802 via_sata_chip_map(sc, pa, 7); 803 } 804 805 static void 806 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 807 { 808 struct pciide_channel *cp; 809 struct ata_channel *wdc_cp; 810 struct wdc_regs *wdr; 811 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 812 int channel; 813 bus_size_t cmdsize; 814 pci_intr_handle_t intrhandle; 815 const char *intrstr; 816 int i; 817 818 if (via_sata_chip_map_common(sc, pa) == 0) 819 return; 820 821 if (interface == 0) { 822 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 823 DEBUG_PROBE); 824 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 825 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 826 } 827 828 if (pci_intr_map(pa, &intrhandle) != 0) { 829 aprint_error("%s: couldn't map native-PCI interrupt\n", 830 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 831 return; 832 } 833 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 834 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 835 intrhandle, IPL_BIO, pciide_pci_intr, sc); 836 if (sc->sc_pci_ih == NULL) { 837 aprint_error( 838 "%s: couldn't establish native-PCI interrupt", 839 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 840 if (intrstr != NULL) 841 aprint_error(" at %s", intrstr); 842 aprint_error("\n"); 843 return; 844 } 845 aprint_normal("%s: using %s for native-PCI interrupt\n", 846 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 847 intrstr ? intrstr : "unknown interrupt"); 848 849 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 850 channel++) { 851 cp = &sc->pciide_channels[channel]; 852 if (pciide_chansetup(sc, channel, interface) == 0) 853 continue; 854 cp->ata_channel.ch_ndrive = 1; 855 wdc_cp = &cp->ata_channel; 856 wdr = CHAN_TO_WDC_REGS(wdc_cp); 857 858 wdr->sata_iot = sc->sc_ba5_st; 859 wdr->sata_baseioh = sc->sc_ba5_sh; 860 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 861 (wdc_cp->ch_channel << 6) + 0x0, 1, 862 &wdr->sata_status) != 0) { 863 aprint_error("%s: couldn't map channel %d " 864 "sata_status regs\n", 865 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 866 wdc_cp->ch_channel); 867 continue; 868 } 869 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 870 (wdc_cp->ch_channel << 6) + 0x4, 1, 871 &wdr->sata_error) != 0) { 872 aprint_error("%s: couldn't map channel %d " 873 "sata_error regs\n", 874 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 875 wdc_cp->ch_channel); 876 continue; 877 } 878 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 879 (wdc_cp->ch_channel << 6) + 0x8, 1, 880 &wdr->sata_control) != 0) { 881 aprint_error("%s: couldn't map channel %d " 882 "sata_control regs\n", 883 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 884 wdc_cp->ch_channel); 885 continue; 886 } 887 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 888 889 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 890 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 891 NULL, &cmdsize) != 0) { 892 aprint_error("%s: couldn't map %s channel regs\n", 893 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 894 cp->name); 895 } 896 wdr->ctl_iot = wdr->cmd_iot; 897 for (i = 0; i < WDC_NREG; i++) { 898 if (bus_space_subregion(wdr->cmd_iot, 899 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 900 &wdr->cmd_iohs[i]) != 0) { 901 aprint_error("%s: couldn't subregion %s " 902 "channel cmd regs\n", 903 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 904 cp->name); 905 return; 906 } 907 } 908 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 909 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 910 aprint_error("%s: couldn't map channel %d ctl regs\n", 911 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 912 return; 913 } 914 wdc_init_shadow_regs(wdc_cp); 915 wdcattach(wdc_cp); 916 } 917 } 918
Indexes created Mon Oct 20 08:09:54 GMT 2025