viaide.c revision 1.38
1 /* $NetBSD: viaide.c,v 1.38 2007/01/21 05:00:34 isaki Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.38 2007/01/21 05:00:34 isaki Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_AMD_CS5536_IDE, 91 0, 92 "Advanced Micro Devices CS5536 IDE Controller", 93 via_chip_map 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static const struct pciide_product_desc pciide_nvidia_products[] = { 103 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 104 0, 105 "NVIDIA nForce IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 109 0, 110 "NVIDIA nForce2 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 114 0, 115 "NVIDIA nForce2 Ultra 400 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 119 0, 120 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 121 via_sata_chip_map_6 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 124 0, 125 "NVIDIA nForce3 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 129 0, 130 "NVIDIA nForce3 250 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 139 0, 140 "NVIDIA nForce3 250 Serial ATA Controller", 141 via_sata_chip_map_6 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 144 0, 145 "NVIDIA nForce4 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 154 0, 155 "NVIDIA nForce4 Serial ATA Controller", 156 via_sata_chip_map_6 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 159 0, 160 "NVIDIA nForce430 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 169 0, 170 "NVIDIA nForce430 Serial ATA Controller", 171 via_sata_chip_map_6 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 174 0, 175 "NVIDIA MCP04 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 184 0, 185 "NVIDIA MCP04 Serial ATA Controller", 186 via_sata_chip_map_6 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 189 0, 190 "NVIDIA MCP55 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 199 0, 200 "NVIDIA MCP55 Serial ATA Controller", 201 via_sata_chip_map_6 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 204 0, 205 "NVIDIA MCP61 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 209 0, 210 "NVIDIA MCP65 IDE Controller", 211 via_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 214 0, 215 "NVIDIA MCP61 Serial ATA Controller", 216 via_sata_chip_map_6 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 219 0, 220 "NVIDIA MCP61 Serial ATA Controller", 221 via_sata_chip_map_6 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 224 0, 225 "NVIDIA MCP61 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 234 0, 235 "NVIDIA MCP65 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 244 0, 245 "NVIDIA MCP65 Serial ATA Controller", 246 via_sata_chip_map_6 247 }, 248 { 0, 249 0, 250 NULL, 251 NULL 252 } 253 }; 254 255 static const struct pciide_product_desc pciide_via_products[] = { 256 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 257 0, 258 NULL, 259 via_chip_map, 260 }, 261 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 262 0, 263 NULL, 264 via_chip_map, 265 }, 266 { PCI_PRODUCT_VIATECH_VT6421_RAID, 267 0, 268 "VIA Technologies VT6421 Serial RAID Controller", 269 via_sata_chip_map_new, 270 }, 271 { PCI_PRODUCT_VIATECH_VT8237_SATA, 272 0, 273 "VIA Technologies VT8237 SATA Controller", 274 via_sata_chip_map_7, 275 }, 276 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 277 0, 278 "VIA Technologies VT8237A SATA Controller", 279 via_sata_chip_map_0, 280 }, 281 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 282 0, 283 "VIA Technologies VT8237R SATA Controller", 284 via_sata_chip_map_0, 285 }, 286 { 0, 287 0, 288 NULL, 289 NULL 290 } 291 }; 292 293 static const struct pciide_product_desc * 294 viaide_lookup(pcireg_t id) 295 { 296 297 switch (PCI_VENDOR(id)) { 298 case PCI_VENDOR_VIATECH: 299 return (pciide_lookup_product(id, pciide_via_products)); 300 301 case PCI_VENDOR_AMD: 302 return (pciide_lookup_product(id, pciide_amd_products)); 303 304 case PCI_VENDOR_NVIDIA: 305 return (pciide_lookup_product(id, pciide_nvidia_products)); 306 } 307 return (NULL); 308 } 309 310 static int 311 viaide_match(struct device *parent, struct cfdata *match, 312 void *aux) 313 { 314 struct pci_attach_args *pa = aux; 315 316 if (viaide_lookup(pa->pa_id) != NULL) 317 return (2); 318 return (0); 319 } 320 321 static void 322 viaide_attach(struct device *parent, struct device *self, void *aux) 323 { 324 struct pci_attach_args *pa = aux; 325 struct pciide_softc *sc = (struct pciide_softc *)self; 326 const struct pciide_product_desc *pp; 327 328 pp = viaide_lookup(pa->pa_id); 329 if (pp == NULL) 330 panic("viaide_attach"); 331 pciide_common_attach(sc, pa, pp); 332 } 333 334 static int 335 via_pcib_match(struct pci_attach_args *pa) 336 { 337 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 338 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 339 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 340 return (1); 341 return 0; 342 } 343 344 static void 345 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 346 { 347 struct pciide_channel *cp; 348 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 349 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 350 int channel; 351 u_int32_t ideconf; 352 bus_size_t cmdsize, ctlsize; 353 pcireg_t pcib_id, pcib_class; 354 struct pci_attach_args pcib_pa; 355 356 if (pciide_chipen(sc, pa) == 0) 357 return; 358 359 switch (vendor) { 360 case PCI_VENDOR_VIATECH: 361 /* 362 * get a PCI tag for the ISA bridge. 363 */ 364 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 365 goto unknown; 366 pcib_id = pcib_pa.pa_id; 367 pcib_class = pcib_pa.pa_class; 368 aprint_normal("%s: VIA Technologies ", 369 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 370 switch (PCI_PRODUCT(pcib_id)) { 371 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 372 aprint_normal("VT82C586 (Apollo VP) "); 373 if(PCI_REVISION(pcib_class) >= 0x02) { 374 aprint_normal("ATA33 controller\n"); 375 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 376 } else { 377 aprint_normal("controller\n"); 378 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 379 } 380 break; 381 case PCI_PRODUCT_VIATECH_VT82C596A: 382 aprint_normal("VT82C596A (Apollo Pro) "); 383 if (PCI_REVISION(pcib_class) >= 0x12) { 384 aprint_normal("ATA66 controller\n"); 385 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 386 } else { 387 aprint_normal("ATA33 controller\n"); 388 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 389 } 390 break; 391 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 392 aprint_normal("VT82C686A (Apollo KX133) "); 393 if (PCI_REVISION(pcib_class) >= 0x40) { 394 aprint_normal("ATA100 controller\n"); 395 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 396 } else { 397 aprint_normal("ATA66 controller\n"); 398 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 399 } 400 break; 401 case PCI_PRODUCT_VIATECH_VT8231: 402 aprint_normal("VT8231 ATA100 controller\n"); 403 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 404 break; 405 case PCI_PRODUCT_VIATECH_VT8233: 406 aprint_normal("VT8233 ATA100 controller\n"); 407 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 408 break; 409 case PCI_PRODUCT_VIATECH_VT8233A: 410 aprint_normal("VT8233A ATA133 controller\n"); 411 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 412 break; 413 case PCI_PRODUCT_VIATECH_VT8235: 414 aprint_normal("VT8235 ATA133 controller\n"); 415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 416 break; 417 case PCI_PRODUCT_VIATECH_VT8237: 418 aprint_normal("VT8237 ATA133 controller\n"); 419 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 420 break; 421 default: 422 unknown: 423 aprint_normal("unknown VIA ATA controller\n"); 424 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 425 } 426 sc->sc_apo_regbase = APO_VIA_REGBASE; 427 break; 428 case PCI_VENDOR_AMD: 429 switch (sc->sc_pp->ide_product) { 430 case PCI_PRODUCT_AMD_PBC8111_IDE: 431 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 432 break; 433 case PCI_PRODUCT_AMD_PBC766_IDE: 434 case PCI_PRODUCT_AMD_PBC768_IDE: 435 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 436 break; 437 default: 438 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 439 } 440 sc->sc_apo_regbase = APO_AMD_REGBASE; 441 break; 442 case PCI_VENDOR_NVIDIA: 443 switch (sc->sc_pp->ide_product) { 444 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 445 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 446 break; 447 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 448 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 449 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 450 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 451 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 452 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 453 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 454 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 455 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 456 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 457 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 458 break; 459 } 460 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 461 break; 462 default: 463 panic("via_chip_map: unknown vendor"); 464 } 465 466 aprint_normal("%s: bus-master DMA support present", 467 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 468 pciide_mapreg_dma(sc, pa); 469 aprint_normal("\n"); 470 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 471 if (sc->sc_dma_ok) { 472 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 473 sc->sc_wdcdev.irqack = pciide_irqack; 474 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 475 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 476 } 477 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 478 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 479 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 480 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 481 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 482 483 wdc_allocate_regs(&sc->sc_wdcdev); 484 485 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 486 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 487 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 488 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 489 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 490 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 491 DEBUG_PROBE); 492 493 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 494 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 495 channel++) { 496 cp = &sc->pciide_channels[channel]; 497 if (pciide_chansetup(sc, channel, interface) == 0) 498 continue; 499 500 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 501 aprint_normal("%s: %s channel ignored (disabled)\n", 502 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 503 cp->ata_channel.ch_flags |= ATACH_DISABLED; 504 continue; 505 } 506 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 507 pciide_pci_intr); 508 } 509 } 510 511 static void 512 via_setup_channel(struct ata_channel *chp) 513 { 514 u_int32_t udmatim_reg, datatim_reg; 515 u_int8_t idedma_ctl; 516 int mode, drive, s; 517 struct ata_drive_datas *drvp; 518 struct atac_softc *atac = chp->ch_atac; 519 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 520 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 521 #ifndef PCIIDE_AMD756_ENABLEDMA 522 int rev = PCI_REVISION( 523 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 524 #endif 525 526 idedma_ctl = 0; 527 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 528 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 529 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 530 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 531 532 /* setup DMA if needed */ 533 pciide_channel_dma_setup(cp); 534 535 for (drive = 0; drive < 2; drive++) { 536 drvp = &chp->ch_drive[drive]; 537 /* If no drive, skip */ 538 if ((drvp->drive_flags & DRIVE) == 0) 539 continue; 540 /* add timing values, setup DMA if needed */ 541 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 542 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 543 mode = drvp->PIO_mode; 544 goto pio; 545 } 546 if ((atac->atac_cap & ATAC_CAP_UDMA) && 547 (drvp->drive_flags & DRIVE_UDMA)) { 548 /* use Ultra/DMA */ 549 s = splbio(); 550 drvp->drive_flags &= ~DRIVE_DMA; 551 splx(s); 552 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 553 APO_UDMA_EN_MTH(chp->ch_channel, drive); 554 switch (PCI_VENDOR(sc->sc_pci_id)) { 555 case PCI_VENDOR_VIATECH: 556 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 557 /* 8233a */ 558 udmatim_reg |= APO_UDMA_TIME( 559 chp->ch_channel, 560 drive, 561 via_udma133_tim[drvp->UDMA_mode]); 562 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 563 /* 686b */ 564 udmatim_reg |= APO_UDMA_TIME( 565 chp->ch_channel, 566 drive, 567 via_udma100_tim[drvp->UDMA_mode]); 568 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 569 /* 596b or 686a */ 570 udmatim_reg |= APO_UDMA_CLK66( 571 chp->ch_channel); 572 udmatim_reg |= APO_UDMA_TIME( 573 chp->ch_channel, 574 drive, 575 via_udma66_tim[drvp->UDMA_mode]); 576 } else { 577 /* 596a or 586b */ 578 udmatim_reg |= APO_UDMA_TIME( 579 chp->ch_channel, 580 drive, 581 via_udma33_tim[drvp->UDMA_mode]); 582 } 583 break; 584 case PCI_VENDOR_AMD: 585 case PCI_VENDOR_NVIDIA: 586 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 587 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 588 break; 589 } 590 /* can use PIO timings, MW DMA unused */ 591 mode = drvp->PIO_mode; 592 } else { 593 /* use Multiword DMA, but only if revision is OK */ 594 s = splbio(); 595 drvp->drive_flags &= ~DRIVE_UDMA; 596 splx(s); 597 #ifndef PCIIDE_AMD756_ENABLEDMA 598 /* 599 * The workaround doesn't seem to be necessary 600 * with all drives, so it can be disabled by 601 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 602 * triggered. 603 */ 604 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 605 sc->sc_pp->ide_product == 606 PCI_PRODUCT_AMD_PBC756_IDE && 607 AMD756_CHIPREV_DISABLEDMA(rev)) { 608 aprint_normal( 609 "%s:%d:%d: multi-word DMA disabled due " 610 "to chip revision\n", 611 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 612 chp->ch_channel, drive); 613 mode = drvp->PIO_mode; 614 s = splbio(); 615 drvp->drive_flags &= ~DRIVE_DMA; 616 splx(s); 617 goto pio; 618 } 619 #endif 620 /* mode = min(pio, dma+2) */ 621 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 622 mode = drvp->PIO_mode; 623 else 624 mode = drvp->DMA_mode + 2; 625 } 626 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 627 628 pio: /* setup PIO mode */ 629 if (mode <= 2) { 630 drvp->DMA_mode = 0; 631 drvp->PIO_mode = 0; 632 mode = 0; 633 } else { 634 drvp->PIO_mode = mode; 635 drvp->DMA_mode = mode - 2; 636 } 637 datatim_reg |= 638 APO_DATATIM_PULSE(chp->ch_channel, drive, 639 apollo_pio_set[mode]) | 640 APO_DATATIM_RECOV(chp->ch_channel, drive, 641 apollo_pio_rec[mode]); 642 } 643 if (idedma_ctl != 0) { 644 /* Add software bits in status register */ 645 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 646 idedma_ctl); 647 } 648 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 649 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 650 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 651 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 652 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 653 } 654 655 static int 656 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 657 { 658 bus_size_t satasize; 659 int maptype, ret; 660 661 if (pciide_chipen(sc, pa) == 0) 662 return 0; 663 664 aprint_normal("%s: bus-master DMA support present", 665 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 666 pciide_mapreg_dma(sc, pa); 667 aprint_normal("\n"); 668 669 if (sc->sc_dma_ok) { 670 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 671 sc->sc_wdcdev.irqack = pciide_irqack; 672 } 673 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 674 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 675 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 676 677 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 678 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 679 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 680 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 681 682 wdc_allocate_regs(&sc->sc_wdcdev); 683 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 684 PCI_MAPREG_START + 0x14); 685 switch(maptype) { 686 case PCI_MAPREG_TYPE_IO: 687 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 688 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 689 NULL, &satasize); 690 break; 691 case PCI_MAPREG_MEM_TYPE_32BIT: 692 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 693 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 694 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 695 NULL, &satasize); 696 break; 697 default: 698 aprint_error("%s: couldn't map sata regs, unsupported" 699 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 700 maptype); 701 return 0; 702 } 703 if (ret != 0) { 704 aprint_error("%s: couldn't map sata regs\n", 705 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 706 return 0; 707 } 708 return 1; 709 } 710 711 static void 712 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 713 int satareg_shift) 714 { 715 struct pciide_channel *cp; 716 struct ata_channel *wdc_cp; 717 struct wdc_regs *wdr; 718 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 719 int channel; 720 bus_size_t cmdsize, ctlsize; 721 722 if (via_sata_chip_map_common(sc, pa) == 0) 723 return; 724 725 if (interface == 0) { 726 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 727 DEBUG_PROBE); 728 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 729 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 730 } 731 732 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 733 channel++) { 734 cp = &sc->pciide_channels[channel]; 735 if (pciide_chansetup(sc, channel, interface) == 0) 736 continue; 737 wdc_cp = &cp->ata_channel; 738 wdr = CHAN_TO_WDC_REGS(wdc_cp); 739 wdr->sata_iot = sc->sc_ba5_st; 740 wdr->sata_baseioh = sc->sc_ba5_sh; 741 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 742 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 743 &wdr->sata_status) != 0) { 744 aprint_error("%s: couldn't map channel %d " 745 "sata_status regs\n", 746 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 747 wdc_cp->ch_channel); 748 continue; 749 } 750 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 751 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 752 &wdr->sata_error) != 0) { 753 aprint_error("%s: couldn't map channel %d " 754 "sata_error regs\n", 755 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 756 wdc_cp->ch_channel); 757 continue; 758 } 759 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 760 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 761 &wdr->sata_control) != 0) { 762 aprint_error("%s: couldn't map channel %d " 763 "sata_control regs\n", 764 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 765 wdc_cp->ch_channel); 766 continue; 767 } 768 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 769 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 770 pciide_pci_intr); 771 } 772 } 773 774 static void 775 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 776 { 777 via_sata_chip_map(sc, pa, 0); 778 } 779 780 static void 781 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 782 { 783 via_sata_chip_map(sc, pa, 6); 784 } 785 786 static void 787 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 788 { 789 via_sata_chip_map(sc, pa, 7); 790 } 791 792 static void 793 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 794 { 795 struct pciide_channel *cp; 796 struct ata_channel *wdc_cp; 797 struct wdc_regs *wdr; 798 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 799 int channel; 800 bus_size_t cmdsize; 801 pci_intr_handle_t intrhandle; 802 const char *intrstr; 803 int i; 804 805 if (via_sata_chip_map_common(sc, pa) == 0) 806 return; 807 808 if (interface == 0) { 809 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 810 DEBUG_PROBE); 811 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 812 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 813 } 814 815 if (pci_intr_map(pa, &intrhandle) != 0) { 816 aprint_error("%s: couldn't map native-PCI interrupt\n", 817 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 818 return; 819 } 820 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 821 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 822 intrhandle, IPL_BIO, pciide_pci_intr, sc); 823 if (sc->sc_pci_ih == NULL) { 824 aprint_error( 825 "%s: couldn't establish native-PCI interrupt", 826 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 827 if (intrstr != NULL) 828 aprint_error(" at %s", intrstr); 829 aprint_error("\n"); 830 return; 831 } 832 aprint_normal("%s: using %s for native-PCI interrupt\n", 833 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 834 intrstr ? intrstr : "unknown interrupt"); 835 836 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 837 channel++) { 838 cp = &sc->pciide_channels[channel]; 839 if (pciide_chansetup(sc, channel, interface) == 0) 840 continue; 841 cp->ata_channel.ch_ndrive = 1; 842 wdc_cp = &cp->ata_channel; 843 wdr = CHAN_TO_WDC_REGS(wdc_cp); 844 845 wdr->sata_iot = sc->sc_ba5_st; 846 wdr->sata_baseioh = sc->sc_ba5_sh; 847 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 848 (wdc_cp->ch_channel << 6) + 0x0, 1, 849 &wdr->sata_status) != 0) { 850 aprint_error("%s: couldn't map channel %d " 851 "sata_status regs\n", 852 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 853 wdc_cp->ch_channel); 854 continue; 855 } 856 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 857 (wdc_cp->ch_channel << 6) + 0x4, 1, 858 &wdr->sata_error) != 0) { 859 aprint_error("%s: couldn't map channel %d " 860 "sata_error regs\n", 861 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 862 wdc_cp->ch_channel); 863 continue; 864 } 865 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 866 (wdc_cp->ch_channel << 6) + 0x8, 1, 867 &wdr->sata_control) != 0) { 868 aprint_error("%s: couldn't map channel %d " 869 "sata_control regs\n", 870 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 871 wdc_cp->ch_channel); 872 continue; 873 } 874 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 875 876 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 877 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 878 NULL, &cmdsize) != 0) { 879 aprint_error("%s: couldn't map %s channel regs\n", 880 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 881 cp->name); 882 } 883 wdr->ctl_iot = wdr->cmd_iot; 884 for (i = 0; i < WDC_NREG; i++) { 885 if (bus_space_subregion(wdr->cmd_iot, 886 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 887 &wdr->cmd_iohs[i]) != 0) { 888 aprint_error("%s: couldn't subregion %s " 889 "channel cmd regs\n", 890 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 891 cp->name); 892 return; 893 } 894 } 895 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 896 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 897 aprint_error("%s: couldn't map channel %d ctl regs\n", 898 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 899 return; 900 } 901 wdc_init_shadow_regs(wdc_cp); 902 wdcattach(wdc_cp); 903 } 904 } 905
Indexes created Sat Oct 18 17:09:52 GMT 2025