viaide.c revision 1.40.10.1
1 /* $NetBSD: viaide.c,v 1.40.10.1 2007/03/29 19:27:53 reinoud Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.40.10.1 2007/03/29 19:27:53 reinoud Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_AMD_CS5536_IDE, 91 0, 92 "Advanced Micro Devices CS5536 IDE Controller", 93 via_chip_map 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static const struct pciide_product_desc pciide_nvidia_products[] = { 103 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 104 0, 105 "NVIDIA nForce IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 109 0, 110 "NVIDIA nForce2 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 114 0, 115 "NVIDIA nForce2 Ultra 400 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 119 0, 120 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 121 via_sata_chip_map_6 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 124 0, 125 "NVIDIA nForce3 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 129 0, 130 "NVIDIA nForce3 250 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 139 0, 140 "NVIDIA nForce3 250 Serial ATA Controller", 141 via_sata_chip_map_6 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 144 0, 145 "NVIDIA nForce4 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 154 0, 155 "NVIDIA nForce4 Serial ATA Controller", 156 via_sata_chip_map_6 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 159 0, 160 "NVIDIA nForce430 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 169 0, 170 "NVIDIA nForce430 Serial ATA Controller", 171 via_sata_chip_map_6 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 174 0, 175 "NVIDIA MCP04 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 184 0, 185 "NVIDIA MCP04 Serial ATA Controller", 186 via_sata_chip_map_6 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 189 0, 190 "NVIDIA MCP55 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 199 0, 200 "NVIDIA MCP55 Serial ATA Controller", 201 via_sata_chip_map_6 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 204 0, 205 "NVIDIA MCP61 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 209 0, 210 "NVIDIA MCP65 IDE Controller", 211 via_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 214 0, 215 "NVIDIA MCP61 Serial ATA Controller", 216 via_sata_chip_map_6 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 219 0, 220 "NVIDIA MCP61 Serial ATA Controller", 221 via_sata_chip_map_6 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 224 0, 225 "NVIDIA MCP61 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 229 0, 230 "NVIDIA MCP65 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 234 0, 235 "NVIDIA MCP65 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 244 0, 245 "NVIDIA MCP65 Serial ATA Controller", 246 via_sata_chip_map_6 247 }, 248 { 0, 249 0, 250 NULL, 251 NULL 252 } 253 }; 254 255 static const struct pciide_product_desc pciide_via_products[] = { 256 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 257 0, 258 NULL, 259 via_chip_map, 260 }, 261 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 262 0, 263 NULL, 264 via_chip_map, 265 }, 266 { PCI_PRODUCT_VIATECH_VT6421_RAID, 267 0, 268 "VIA Technologies VT6421 Serial RAID Controller", 269 via_sata_chip_map_new, 270 }, 271 { PCI_PRODUCT_VIATECH_VT8237_SATA, 272 0, 273 "VIA Technologies VT8237 SATA Controller", 274 via_sata_chip_map_7, 275 }, 276 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 277 0, 278 "VIA Technologies VT8237A SATA Controller", 279 via_sata_chip_map_7, 280 }, 281 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 282 0, 283 "VIA Technologies VT8237R SATA Controller", 284 via_sata_chip_map_0, 285 }, 286 { 0, 287 0, 288 NULL, 289 NULL 290 } 291 }; 292 293 static const struct pciide_product_desc * 294 viaide_lookup(pcireg_t id) 295 { 296 297 switch (PCI_VENDOR(id)) { 298 case PCI_VENDOR_VIATECH: 299 return (pciide_lookup_product(id, pciide_via_products)); 300 301 case PCI_VENDOR_AMD: 302 return (pciide_lookup_product(id, pciide_amd_products)); 303 304 case PCI_VENDOR_NVIDIA: 305 return (pciide_lookup_product(id, pciide_nvidia_products)); 306 } 307 return (NULL); 308 } 309 310 static int 311 viaide_match(struct device *parent, struct cfdata *match, 312 void *aux) 313 { 314 struct pci_attach_args *pa = aux; 315 316 if (viaide_lookup(pa->pa_id) != NULL) 317 return (2); 318 return (0); 319 } 320 321 static void 322 viaide_attach(struct device *parent, struct device *self, void *aux) 323 { 324 struct pci_attach_args *pa = aux; 325 struct pciide_softc *sc = (struct pciide_softc *)self; 326 const struct pciide_product_desc *pp; 327 328 pp = viaide_lookup(pa->pa_id); 329 if (pp == NULL) 330 panic("viaide_attach"); 331 pciide_common_attach(sc, pa, pp); 332 } 333 334 static int 335 via_pcib_match(struct pci_attach_args *pa) 336 { 337 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 338 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 339 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 340 return (1); 341 return 0; 342 } 343 344 static void 345 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 346 { 347 struct pciide_channel *cp; 348 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 349 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 350 int channel; 351 u_int32_t ideconf; 352 bus_size_t cmdsize, ctlsize; 353 pcireg_t pcib_id, pcib_class; 354 struct pci_attach_args pcib_pa; 355 356 if (pciide_chipen(sc, pa) == 0) 357 return; 358 359 switch (vendor) { 360 case PCI_VENDOR_VIATECH: 361 /* 362 * get a PCI tag for the ISA bridge. 363 */ 364 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 365 goto unknown; 366 pcib_id = pcib_pa.pa_id; 367 pcib_class = pcib_pa.pa_class; 368 aprint_normal("%s: VIA Technologies ", 369 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 370 switch (PCI_PRODUCT(pcib_id)) { 371 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 372 aprint_normal("VT82C586 (Apollo VP) "); 373 if(PCI_REVISION(pcib_class) >= 0x02) { 374 aprint_normal("ATA33 controller\n"); 375 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 376 } else { 377 aprint_normal("controller\n"); 378 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 379 } 380 break; 381 case PCI_PRODUCT_VIATECH_VT82C596A: 382 aprint_normal("VT82C596A (Apollo Pro) "); 383 if (PCI_REVISION(pcib_class) >= 0x12) { 384 aprint_normal("ATA66 controller\n"); 385 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 386 } else { 387 aprint_normal("ATA33 controller\n"); 388 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 389 } 390 break; 391 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 392 aprint_normal("VT82C686A (Apollo KX133) "); 393 if (PCI_REVISION(pcib_class) >= 0x40) { 394 aprint_normal("ATA100 controller\n"); 395 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 396 } else { 397 aprint_normal("ATA66 controller\n"); 398 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 399 } 400 break; 401 case PCI_PRODUCT_VIATECH_VT8231: 402 aprint_normal("VT8231 ATA100 controller\n"); 403 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 404 break; 405 case PCI_PRODUCT_VIATECH_VT8233: 406 aprint_normal("VT8233 ATA100 controller\n"); 407 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 408 break; 409 case PCI_PRODUCT_VIATECH_VT8233A: 410 aprint_normal("VT8233A ATA133 controller\n"); 411 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 412 break; 413 case PCI_PRODUCT_VIATECH_VT8235: 414 aprint_normal("VT8235 ATA133 controller\n"); 415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 416 break; 417 case PCI_PRODUCT_VIATECH_VT8237: 418 aprint_normal("VT8237 ATA133 controller\n"); 419 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 420 break; 421 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 422 aprint_normal("VT8237A ATA133 controller\n"); 423 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 424 break; 425 default: 426 unknown: 427 aprint_normal("unknown VIA ATA controller\n"); 428 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 429 } 430 sc->sc_apo_regbase = APO_VIA_REGBASE; 431 break; 432 case PCI_VENDOR_AMD: 433 switch (sc->sc_pp->ide_product) { 434 case PCI_PRODUCT_AMD_PBC8111_IDE: 435 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 436 break; 437 case PCI_PRODUCT_AMD_PBC766_IDE: 438 case PCI_PRODUCT_AMD_PBC768_IDE: 439 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 440 break; 441 default: 442 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 443 } 444 sc->sc_apo_regbase = APO_AMD_REGBASE; 445 break; 446 case PCI_VENDOR_NVIDIA: 447 switch (sc->sc_pp->ide_product) { 448 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 449 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 450 break; 451 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 452 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 453 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 454 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 455 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 456 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 457 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 458 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 459 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 460 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 461 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 462 break; 463 } 464 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 465 break; 466 default: 467 panic("via_chip_map: unknown vendor"); 468 } 469 470 aprint_verbose("%s: bus-master DMA support present", 471 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 472 pciide_mapreg_dma(sc, pa); 473 aprint_verbose("\n"); 474 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 475 if (sc->sc_dma_ok) { 476 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 477 sc->sc_wdcdev.irqack = pciide_irqack; 478 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 479 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 480 } 481 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 482 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 483 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 484 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 485 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 486 487 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 488 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 489 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 490 491 wdc_allocate_regs(&sc->sc_wdcdev); 492 493 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 494 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 495 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 496 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 497 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 498 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 499 DEBUG_PROBE); 500 501 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 502 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 503 channel++) { 504 cp = &sc->pciide_channels[channel]; 505 if (pciide_chansetup(sc, channel, interface) == 0) 506 continue; 507 508 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 509 aprint_normal("%s: %s channel ignored (disabled)\n", 510 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 511 cp->ata_channel.ch_flags |= ATACH_DISABLED; 512 continue; 513 } 514 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 515 pciide_pci_intr); 516 } 517 } 518 519 static void 520 via_setup_channel(struct ata_channel *chp) 521 { 522 u_int32_t udmatim_reg, datatim_reg; 523 u_int8_t idedma_ctl; 524 int mode, drive, s; 525 struct ata_drive_datas *drvp; 526 struct atac_softc *atac = chp->ch_atac; 527 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 528 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 529 #ifndef PCIIDE_AMD756_ENABLEDMA 530 int rev = PCI_REVISION( 531 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 532 #endif 533 534 idedma_ctl = 0; 535 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 536 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 537 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 538 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 539 540 /* setup DMA if needed */ 541 pciide_channel_dma_setup(cp); 542 543 for (drive = 0; drive < 2; drive++) { 544 drvp = &chp->ch_drive[drive]; 545 /* If no drive, skip */ 546 if ((drvp->drive_flags & DRIVE) == 0) 547 continue; 548 /* add timing values, setup DMA if needed */ 549 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 550 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 551 mode = drvp->PIO_mode; 552 goto pio; 553 } 554 if ((atac->atac_cap & ATAC_CAP_UDMA) && 555 (drvp->drive_flags & DRIVE_UDMA)) { 556 /* use Ultra/DMA */ 557 s = splbio(); 558 drvp->drive_flags &= ~DRIVE_DMA; 559 splx(s); 560 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 561 APO_UDMA_EN_MTH(chp->ch_channel, drive); 562 switch (PCI_VENDOR(sc->sc_pci_id)) { 563 case PCI_VENDOR_VIATECH: 564 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 565 /* 8233a */ 566 udmatim_reg |= APO_UDMA_TIME( 567 chp->ch_channel, 568 drive, 569 via_udma133_tim[drvp->UDMA_mode]); 570 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 571 /* 686b */ 572 udmatim_reg |= APO_UDMA_TIME( 573 chp->ch_channel, 574 drive, 575 via_udma100_tim[drvp->UDMA_mode]); 576 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 577 /* 596b or 686a */ 578 udmatim_reg |= APO_UDMA_CLK66( 579 chp->ch_channel); 580 udmatim_reg |= APO_UDMA_TIME( 581 chp->ch_channel, 582 drive, 583 via_udma66_tim[drvp->UDMA_mode]); 584 } else { 585 /* 596a or 586b */ 586 udmatim_reg |= APO_UDMA_TIME( 587 chp->ch_channel, 588 drive, 589 via_udma33_tim[drvp->UDMA_mode]); 590 } 591 break; 592 case PCI_VENDOR_AMD: 593 case PCI_VENDOR_NVIDIA: 594 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 595 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 596 break; 597 } 598 /* can use PIO timings, MW DMA unused */ 599 mode = drvp->PIO_mode; 600 } else { 601 /* use Multiword DMA, but only if revision is OK */ 602 s = splbio(); 603 drvp->drive_flags &= ~DRIVE_UDMA; 604 splx(s); 605 #ifndef PCIIDE_AMD756_ENABLEDMA 606 /* 607 * The workaround doesn't seem to be necessary 608 * with all drives, so it can be disabled by 609 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 610 * triggered. 611 */ 612 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 613 sc->sc_pp->ide_product == 614 PCI_PRODUCT_AMD_PBC756_IDE && 615 AMD756_CHIPREV_DISABLEDMA(rev)) { 616 aprint_normal( 617 "%s:%d:%d: multi-word DMA disabled due " 618 "to chip revision\n", 619 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 620 chp->ch_channel, drive); 621 mode = drvp->PIO_mode; 622 s = splbio(); 623 drvp->drive_flags &= ~DRIVE_DMA; 624 splx(s); 625 goto pio; 626 } 627 #endif 628 /* mode = min(pio, dma+2) */ 629 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 630 mode = drvp->PIO_mode; 631 else 632 mode = drvp->DMA_mode + 2; 633 } 634 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 635 636 pio: /* setup PIO mode */ 637 if (mode <= 2) { 638 drvp->DMA_mode = 0; 639 drvp->PIO_mode = 0; 640 mode = 0; 641 } else { 642 drvp->PIO_mode = mode; 643 drvp->DMA_mode = mode - 2; 644 } 645 datatim_reg |= 646 APO_DATATIM_PULSE(chp->ch_channel, drive, 647 apollo_pio_set[mode]) | 648 APO_DATATIM_RECOV(chp->ch_channel, drive, 649 apollo_pio_rec[mode]); 650 } 651 if (idedma_ctl != 0) { 652 /* Add software bits in status register */ 653 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 654 idedma_ctl); 655 } 656 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 657 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 658 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 659 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 660 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 661 } 662 663 static int 664 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 665 { 666 bus_size_t satasize; 667 int maptype, ret; 668 669 if (pciide_chipen(sc, pa) == 0) 670 return 0; 671 672 aprint_verbose("%s: bus-master DMA support present", 673 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 674 pciide_mapreg_dma(sc, pa); 675 aprint_verbose("\n"); 676 677 if (sc->sc_dma_ok) { 678 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 679 sc->sc_wdcdev.irqack = pciide_irqack; 680 } 681 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 682 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 683 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 684 685 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 686 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 687 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 688 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 689 690 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 691 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 692 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 693 694 wdc_allocate_regs(&sc->sc_wdcdev); 695 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 696 PCI_MAPREG_START + 0x14); 697 switch(maptype) { 698 case PCI_MAPREG_TYPE_IO: 699 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 700 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 701 NULL, &satasize); 702 break; 703 case PCI_MAPREG_MEM_TYPE_32BIT: 704 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 705 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 706 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 707 NULL, &satasize); 708 break; 709 default: 710 aprint_error("%s: couldn't map sata regs, unsupported" 711 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 712 maptype); 713 return 0; 714 } 715 if (ret != 0) { 716 aprint_error("%s: couldn't map sata regs\n", 717 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 718 return 0; 719 } 720 return 1; 721 } 722 723 static void 724 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 725 int satareg_shift) 726 { 727 struct pciide_channel *cp; 728 struct ata_channel *wdc_cp; 729 struct wdc_regs *wdr; 730 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 731 int channel; 732 bus_size_t cmdsize, ctlsize; 733 734 if (via_sata_chip_map_common(sc, pa) == 0) 735 return; 736 737 if (interface == 0) { 738 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 739 DEBUG_PROBE); 740 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 741 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 742 } 743 744 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 745 channel++) { 746 cp = &sc->pciide_channels[channel]; 747 if (pciide_chansetup(sc, channel, interface) == 0) 748 continue; 749 wdc_cp = &cp->ata_channel; 750 wdr = CHAN_TO_WDC_REGS(wdc_cp); 751 wdr->sata_iot = sc->sc_ba5_st; 752 wdr->sata_baseioh = sc->sc_ba5_sh; 753 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 754 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 755 &wdr->sata_status) != 0) { 756 aprint_error("%s: couldn't map channel %d " 757 "sata_status regs\n", 758 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 759 wdc_cp->ch_channel); 760 continue; 761 } 762 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 763 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 764 &wdr->sata_error) != 0) { 765 aprint_error("%s: couldn't map channel %d " 766 "sata_error regs\n", 767 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 768 wdc_cp->ch_channel); 769 continue; 770 } 771 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 772 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 773 &wdr->sata_control) != 0) { 774 aprint_error("%s: couldn't map channel %d " 775 "sata_control regs\n", 776 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 777 wdc_cp->ch_channel); 778 continue; 779 } 780 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 781 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 782 pciide_pci_intr); 783 } 784 } 785 786 static void 787 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 788 { 789 via_sata_chip_map(sc, pa, 0); 790 } 791 792 static void 793 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 794 { 795 via_sata_chip_map(sc, pa, 6); 796 } 797 798 static void 799 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 800 { 801 via_sata_chip_map(sc, pa, 7); 802 } 803 804 static void 805 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 806 { 807 struct pciide_channel *cp; 808 struct ata_channel *wdc_cp; 809 struct wdc_regs *wdr; 810 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 811 int channel; 812 bus_size_t cmdsize; 813 pci_intr_handle_t intrhandle; 814 const char *intrstr; 815 int i; 816 817 if (via_sata_chip_map_common(sc, pa) == 0) 818 return; 819 820 if (interface == 0) { 821 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 822 DEBUG_PROBE); 823 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 824 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 825 } 826 827 if (pci_intr_map(pa, &intrhandle) != 0) { 828 aprint_error("%s: couldn't map native-PCI interrupt\n", 829 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 830 return; 831 } 832 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 833 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 834 intrhandle, IPL_BIO, pciide_pci_intr, sc); 835 if (sc->sc_pci_ih == NULL) { 836 aprint_error( 837 "%s: couldn't establish native-PCI interrupt", 838 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 839 if (intrstr != NULL) 840 aprint_error(" at %s", intrstr); 841 aprint_error("\n"); 842 return; 843 } 844 aprint_normal("%s: using %s for native-PCI interrupt\n", 845 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 846 intrstr ? intrstr : "unknown interrupt"); 847 848 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 849 channel++) { 850 cp = &sc->pciide_channels[channel]; 851 if (pciide_chansetup(sc, channel, interface) == 0) 852 continue; 853 cp->ata_channel.ch_ndrive = 1; 854 wdc_cp = &cp->ata_channel; 855 wdr = CHAN_TO_WDC_REGS(wdc_cp); 856 857 wdr->sata_iot = sc->sc_ba5_st; 858 wdr->sata_baseioh = sc->sc_ba5_sh; 859 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 860 (wdc_cp->ch_channel << 6) + 0x0, 1, 861 &wdr->sata_status) != 0) { 862 aprint_error("%s: couldn't map channel %d " 863 "sata_status regs\n", 864 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 865 wdc_cp->ch_channel); 866 continue; 867 } 868 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 869 (wdc_cp->ch_channel << 6) + 0x4, 1, 870 &wdr->sata_error) != 0) { 871 aprint_error("%s: couldn't map channel %d " 872 "sata_error regs\n", 873 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 874 wdc_cp->ch_channel); 875 continue; 876 } 877 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 878 (wdc_cp->ch_channel << 6) + 0x8, 1, 879 &wdr->sata_control) != 0) { 880 aprint_error("%s: couldn't map channel %d " 881 "sata_control regs\n", 882 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 883 wdc_cp->ch_channel); 884 continue; 885 } 886 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 887 888 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 889 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 890 NULL, &cmdsize) != 0) { 891 aprint_error("%s: couldn't map %s channel regs\n", 892 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 893 cp->name); 894 } 895 wdr->ctl_iot = wdr->cmd_iot; 896 for (i = 0; i < WDC_NREG; i++) { 897 if (bus_space_subregion(wdr->cmd_iot, 898 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 899 &wdr->cmd_iohs[i]) != 0) { 900 aprint_error("%s: couldn't subregion %s " 901 "channel cmd regs\n", 902 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 903 cp->name); 904 return; 905 } 906 } 907 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 908 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 909 aprint_error("%s: couldn't map channel %d ctl regs\n", 910 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 911 return; 912 } 913 wdc_init_shadow_regs(wdc_cp); 914 wdcattach(wdc_cp); 915 } 916 } 917
Indexes created Sun Oct 19 02:09:48 GMT 2025