viaide.c revision 1.41.8.1 1 /* $NetBSD: viaide.c,v 1.41.8.1 2007/09/03 16:48:24 jmcneill Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.41.8.1 2007/09/03 16:48:24 jmcneill Exp $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcidevs.h>
41 #include <dev/pci/pciidereg.h>
42 #include <dev/pci/pciidevar.h>
43 #include <dev/pci/pciide_apollo_reg.h>
44
45 static int via_pcib_match(struct pci_attach_args *);
46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
47 static int via_sata_chip_map_common(struct pciide_softc *,
48 struct pci_attach_args *);
49 static void via_sata_chip_map(struct pciide_softc *,
50 struct pci_attach_args *, int);
51 static void via_sata_chip_map_0(struct pciide_softc *,
52 struct pci_attach_args *);
53 static void via_sata_chip_map_6(struct pciide_softc *,
54 struct pci_attach_args *);
55 static void via_sata_chip_map_7(struct pciide_softc *,
56 struct pci_attach_args *);
57 static void via_sata_chip_map_new(struct pciide_softc *,
58 struct pci_attach_args *);
59 static void via_setup_channel(struct ata_channel *);
60
61 static int viaide_match(struct device *, struct cfdata *, void *);
62 static void viaide_attach(struct device *, struct device *, void *);
63 static const struct pciide_product_desc *
64 viaide_lookup(pcireg_t);
65
66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
67 viaide_match, viaide_attach, NULL, NULL);
68
69 static const struct pciide_product_desc pciide_amd_products[] = {
70 { PCI_PRODUCT_AMD_PBC756_IDE,
71 0,
72 "Advanced Micro Devices AMD756 IDE Controller",
73 via_chip_map
74 },
75 { PCI_PRODUCT_AMD_PBC766_IDE,
76 0,
77 "Advanced Micro Devices AMD766 IDE Controller",
78 via_chip_map
79 },
80 { PCI_PRODUCT_AMD_PBC768_IDE,
81 0,
82 "Advanced Micro Devices AMD768 IDE Controller",
83 via_chip_map
84 },
85 { PCI_PRODUCT_AMD_PBC8111_IDE,
86 0,
87 "Advanced Micro Devices AMD8111 IDE Controller",
88 via_chip_map
89 },
90 { PCI_PRODUCT_AMD_CS5536_IDE,
91 0,
92 "Advanced Micro Devices CS5536 IDE Controller",
93 via_chip_map
94 },
95 { 0,
96 0,
97 NULL,
98 NULL
99 }
100 };
101
102 static const struct pciide_product_desc pciide_nvidia_products[] = {
103 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
104 0,
105 "NVIDIA nForce IDE Controller",
106 via_chip_map
107 },
108 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
109 0,
110 "NVIDIA nForce2 IDE Controller",
111 via_chip_map
112 },
113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
114 0,
115 "NVIDIA nForce2 Ultra 400 IDE Controller",
116 via_chip_map
117 },
118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
119 0,
120 "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
121 via_sata_chip_map_6
122 },
123 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
124 0,
125 "NVIDIA nForce3 IDE Controller",
126 via_chip_map
127 },
128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
129 0,
130 "NVIDIA nForce3 250 IDE Controller",
131 via_chip_map
132 },
133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
134 0,
135 "NVIDIA nForce3 250 Serial ATA Controller",
136 via_sata_chip_map_6
137 },
138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
139 0,
140 "NVIDIA nForce3 250 Serial ATA Controller",
141 via_sata_chip_map_6
142 },
143 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
144 0,
145 "NVIDIA nForce4 IDE Controller",
146 via_chip_map
147 },
148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
149 0,
150 "NVIDIA nForce4 Serial ATA Controller",
151 via_sata_chip_map_6
152 },
153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
154 0,
155 "NVIDIA nForce4 Serial ATA Controller",
156 via_sata_chip_map_6
157 },
158 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
159 0,
160 "NVIDIA nForce430 IDE Controller",
161 via_chip_map
162 },
163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
164 0,
165 "NVIDIA nForce430 Serial ATA Controller",
166 via_sata_chip_map_6
167 },
168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
169 0,
170 "NVIDIA nForce430 Serial ATA Controller",
171 via_sata_chip_map_6
172 },
173 { PCI_PRODUCT_NVIDIA_MCP04_IDE,
174 0,
175 "NVIDIA MCP04 IDE Controller",
176 via_chip_map
177 },
178 { PCI_PRODUCT_NVIDIA_MCP04_SATA,
179 0,
180 "NVIDIA MCP04 Serial ATA Controller",
181 via_sata_chip_map_6
182 },
183 { PCI_PRODUCT_NVIDIA_MCP04_SATA2,
184 0,
185 "NVIDIA MCP04 Serial ATA Controller",
186 via_sata_chip_map_6
187 },
188 { PCI_PRODUCT_NVIDIA_MCP55_IDE,
189 0,
190 "NVIDIA MCP55 IDE Controller",
191 via_chip_map
192 },
193 { PCI_PRODUCT_NVIDIA_MCP55_SATA,
194 0,
195 "NVIDIA MCP55 Serial ATA Controller",
196 via_sata_chip_map_6
197 },
198 { PCI_PRODUCT_NVIDIA_MCP55_SATA2,
199 0,
200 "NVIDIA MCP55 Serial ATA Controller",
201 via_sata_chip_map_6
202 },
203 { PCI_PRODUCT_NVIDIA_MCP61_IDE,
204 0,
205 "NVIDIA MCP61 IDE Controller",
206 via_chip_map
207 },
208 { PCI_PRODUCT_NVIDIA_MCP65_IDE,
209 0,
210 "NVIDIA MCP65 IDE Controller",
211 via_chip_map
212 },
213 { PCI_PRODUCT_NVIDIA_MCP61_SATA,
214 0,
215 "NVIDIA MCP61 Serial ATA Controller",
216 via_sata_chip_map_6
217 },
218 { PCI_PRODUCT_NVIDIA_MCP61_SATA2,
219 0,
220 "NVIDIA MCP61 Serial ATA Controller",
221 via_sata_chip_map_6
222 },
223 { PCI_PRODUCT_NVIDIA_MCP61_SATA3,
224 0,
225 "NVIDIA MCP61 Serial ATA Controller",
226 via_sata_chip_map_6
227 },
228 { PCI_PRODUCT_NVIDIA_MCP65_SATA,
229 0,
230 "NVIDIA MCP65 Serial ATA Controller",
231 via_sata_chip_map_6
232 },
233 { PCI_PRODUCT_NVIDIA_MCP65_SATA2,
234 0,
235 "NVIDIA MCP65 Serial ATA Controller",
236 via_sata_chip_map_6
237 },
238 { PCI_PRODUCT_NVIDIA_MCP65_SATA3,
239 0,
240 "NVIDIA MCP65 Serial ATA Controller",
241 via_sata_chip_map_6
242 },
243 { PCI_PRODUCT_NVIDIA_MCP65_SATA4,
244 0,
245 "NVIDIA MCP65 Serial ATA Controller",
246 via_sata_chip_map_6
247 },
248 { PCI_PRODUCT_NVIDIA_MCP67_IDE,
249 0,
250 "NVIDIA MCP67 IDE Controller",
251 via_chip_map,
252 },
253 { PCI_PRODUCT_NVIDIA_MCP67_SATA,
254 0,
255 "NVIDIA MCP67 Serial ATA Controller",
256 via_sata_chip_map_6,
257 },
258 { PCI_PRODUCT_NVIDIA_MCP67_SATA2,
259 0,
260 "NVIDIA MCP67 Serial ATA Controller",
261 via_sata_chip_map_6,
262 },
263 { PCI_PRODUCT_NVIDIA_MCP67_SATA3,
264 0,
265 "NVIDIA MCP67 Serial ATA Controller",
266 via_sata_chip_map_6,
267 },
268 { PCI_PRODUCT_NVIDIA_MCP67_SATA4,
269 0,
270 "NVIDIA MCP67 Serial ATA Controller",
271 via_sata_chip_map_6,
272 },
273 { 0,
274 0,
275 NULL,
276 NULL
277 }
278 };
279
280 static const struct pciide_product_desc pciide_via_products[] = {
281 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
282 0,
283 NULL,
284 via_chip_map,
285 },
286 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
287 0,
288 NULL,
289 via_chip_map,
290 },
291 { PCI_PRODUCT_VIATECH_CX700_IDE,
292 0,
293 NULL,
294 via_chip_map,
295 },
296 { PCI_PRODUCT_VIATECH_VT6421_RAID,
297 0,
298 "VIA Technologies VT6421 Serial RAID Controller",
299 via_sata_chip_map_new,
300 },
301 { PCI_PRODUCT_VIATECH_VT8237_SATA,
302 0,
303 "VIA Technologies VT8237 SATA Controller",
304 via_sata_chip_map_7,
305 },
306 { PCI_PRODUCT_VIATECH_VT8237A_SATA,
307 0,
308 "VIA Technologies VT8237A SATA Controller",
309 via_sata_chip_map_7,
310 },
311 { PCI_PRODUCT_VIATECH_VT8237R_SATA,
312 0,
313 "VIA Technologies VT8237R SATA Controller",
314 via_sata_chip_map_0,
315 },
316 { 0,
317 0,
318 NULL,
319 NULL
320 }
321 };
322
323 static const struct pciide_product_desc *
324 viaide_lookup(pcireg_t id)
325 {
326
327 switch (PCI_VENDOR(id)) {
328 case PCI_VENDOR_VIATECH:
329 return (pciide_lookup_product(id, pciide_via_products));
330
331 case PCI_VENDOR_AMD:
332 return (pciide_lookup_product(id, pciide_amd_products));
333
334 case PCI_VENDOR_NVIDIA:
335 return (pciide_lookup_product(id, pciide_nvidia_products));
336 }
337 return (NULL);
338 }
339
340 static int
341 viaide_match(struct device *parent, struct cfdata *match,
342 void *aux)
343 {
344 struct pci_attach_args *pa = aux;
345
346 if (viaide_lookup(pa->pa_id) != NULL)
347 return (2);
348 return (0);
349 }
350
351 static void
352 viaide_attach(struct device *parent, struct device *self, void *aux)
353 {
354 struct pci_attach_args *pa = aux;
355 struct pciide_softc *sc = (struct pciide_softc *)self;
356 const struct pciide_product_desc *pp;
357
358 pp = viaide_lookup(pa->pa_id);
359 if (pp == NULL)
360 panic("viaide_attach");
361 pciide_common_attach(sc, pa, pp);
362 }
363
364 static int
365 via_pcib_match(struct pci_attach_args *pa)
366 {
367 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
368 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
369 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
370 return (1);
371 return 0;
372 }
373
374 static void
375 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
376 {
377 struct pciide_channel *cp;
378 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
379 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
380 int channel;
381 u_int32_t ideconf;
382 bus_size_t cmdsize, ctlsize;
383 pcireg_t pcib_id, pcib_class;
384 struct pci_attach_args pcib_pa;
385
386 if (pciide_chipen(sc, pa) == 0)
387 return;
388
389 switch (vendor) {
390 case PCI_VENDOR_VIATECH:
391 /*
392 * get a PCI tag for the ISA bridge.
393 */
394 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
395 goto unknown;
396 pcib_id = pcib_pa.pa_id;
397 pcib_class = pcib_pa.pa_class;
398 aprint_normal("%s: VIA Technologies ",
399 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
400 switch (PCI_PRODUCT(pcib_id)) {
401 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
402 aprint_normal("VT82C586 (Apollo VP) ");
403 if(PCI_REVISION(pcib_class) >= 0x02) {
404 aprint_normal("ATA33 controller\n");
405 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
406 } else {
407 aprint_normal("controller\n");
408 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
409 }
410 break;
411 case PCI_PRODUCT_VIATECH_VT82C596A:
412 aprint_normal("VT82C596A (Apollo Pro) ");
413 if (PCI_REVISION(pcib_class) >= 0x12) {
414 aprint_normal("ATA66 controller\n");
415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
416 } else {
417 aprint_normal("ATA33 controller\n");
418 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
419 }
420 break;
421 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
422 aprint_normal("VT82C686A (Apollo KX133) ");
423 if (PCI_REVISION(pcib_class) >= 0x40) {
424 aprint_normal("ATA100 controller\n");
425 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
426 } else {
427 aprint_normal("ATA66 controller\n");
428 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
429 }
430 break;
431 case PCI_PRODUCT_VIATECH_VT8231:
432 aprint_normal("VT8231 ATA100 controller\n");
433 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
434 break;
435 case PCI_PRODUCT_VIATECH_VT8233:
436 aprint_normal("VT8233 ATA100 controller\n");
437 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
438 break;
439 case PCI_PRODUCT_VIATECH_VT8233A:
440 aprint_normal("VT8233A ATA133 controller\n");
441 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
442 break;
443 case PCI_PRODUCT_VIATECH_VT8235:
444 aprint_normal("VT8235 ATA133 controller\n");
445 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
446 break;
447 case PCI_PRODUCT_VIATECH_VT8237:
448 aprint_normal("VT8237 ATA133 controller\n");
449 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
450 break;
451 case PCI_PRODUCT_VIATECH_VT8237A_ISA:
452 aprint_normal("VT8237A ATA133 controller\n");
453 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
454 break;
455 case PCI_PRODUCT_VIATECH_CX700_IDE:
456 aprint_normal("CX700 ATA133 controller\n");
457 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
458 break;
459 default:
460 unknown:
461 aprint_normal("unknown VIA ATA controller\n");
462 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
463 }
464 sc->sc_apo_regbase = APO_VIA_REGBASE;
465 break;
466 case PCI_VENDOR_AMD:
467 switch (sc->sc_pp->ide_product) {
468 case PCI_PRODUCT_AMD_PBC8111_IDE:
469 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
470 break;
471 case PCI_PRODUCT_AMD_PBC766_IDE:
472 case PCI_PRODUCT_AMD_PBC768_IDE:
473 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
474 break;
475 default:
476 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
477 }
478 sc->sc_apo_regbase = APO_AMD_REGBASE;
479 break;
480 case PCI_VENDOR_NVIDIA:
481 switch (sc->sc_pp->ide_product) {
482 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
483 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
484 break;
485 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
486 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
487 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
488 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
489 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
490 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
491 case PCI_PRODUCT_NVIDIA_MCP04_IDE:
492 case PCI_PRODUCT_NVIDIA_MCP55_IDE:
493 case PCI_PRODUCT_NVIDIA_MCP61_IDE:
494 case PCI_PRODUCT_NVIDIA_MCP65_IDE:
495 case PCI_PRODUCT_NVIDIA_MCP67_IDE:
496 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
497 break;
498 }
499 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
500 break;
501 default:
502 panic("via_chip_map: unknown vendor");
503 }
504
505 aprint_verbose("%s: bus-master DMA support present",
506 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
507 pciide_mapreg_dma(sc, pa);
508 aprint_verbose("\n");
509 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
510 if (sc->sc_dma_ok) {
511 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
512 sc->sc_wdcdev.irqack = pciide_irqack;
513 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
514 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
515 }
516 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
517 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
518 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
519 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
520 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
521
522 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
523 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
524 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
525
526 wdc_allocate_regs(&sc->sc_wdcdev);
527
528 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
529 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
530 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
531 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
532 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
533 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
534 DEBUG_PROBE);
535
536 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
537 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
538 channel++) {
539 cp = &sc->pciide_channels[channel];
540 if (pciide_chansetup(sc, channel, interface) == 0)
541 continue;
542
543 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
544 aprint_normal("%s: %s channel ignored (disabled)\n",
545 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
546 cp->ata_channel.ch_flags |= ATACH_DISABLED;
547 continue;
548 }
549 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
550 pciide_pci_intr);
551 }
552 }
553
554 static void
555 via_setup_channel(struct ata_channel *chp)
556 {
557 u_int32_t udmatim_reg, datatim_reg;
558 u_int8_t idedma_ctl;
559 int mode, drive, s;
560 struct ata_drive_datas *drvp;
561 struct atac_softc *atac = chp->ch_atac;
562 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
563 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
564 #ifndef PCIIDE_AMD756_ENABLEDMA
565 int rev = PCI_REVISION(
566 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
567 #endif
568
569 idedma_ctl = 0;
570 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
571 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
572 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
573 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
574
575 /* setup DMA if needed */
576 pciide_channel_dma_setup(cp);
577
578 for (drive = 0; drive < 2; drive++) {
579 drvp = &chp->ch_drive[drive];
580 /* If no drive, skip */
581 if ((drvp->drive_flags & DRIVE) == 0)
582 continue;
583 /* add timing values, setup DMA if needed */
584 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
585 (drvp->drive_flags & DRIVE_UDMA) == 0)) {
586 mode = drvp->PIO_mode;
587 goto pio;
588 }
589 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
590 (drvp->drive_flags & DRIVE_UDMA)) {
591 /* use Ultra/DMA */
592 s = splbio();
593 drvp->drive_flags &= ~DRIVE_DMA;
594 splx(s);
595 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
596 APO_UDMA_EN_MTH(chp->ch_channel, drive);
597 switch (PCI_VENDOR(sc->sc_pci_id)) {
598 case PCI_VENDOR_VIATECH:
599 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
600 /* 8233a */
601 udmatim_reg |= APO_UDMA_TIME(
602 chp->ch_channel,
603 drive,
604 via_udma133_tim[drvp->UDMA_mode]);
605 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
606 /* 686b */
607 udmatim_reg |= APO_UDMA_TIME(
608 chp->ch_channel,
609 drive,
610 via_udma100_tim[drvp->UDMA_mode]);
611 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
612 /* 596b or 686a */
613 udmatim_reg |= APO_UDMA_CLK66(
614 chp->ch_channel);
615 udmatim_reg |= APO_UDMA_TIME(
616 chp->ch_channel,
617 drive,
618 via_udma66_tim[drvp->UDMA_mode]);
619 } else {
620 /* 596a or 586b */
621 udmatim_reg |= APO_UDMA_TIME(
622 chp->ch_channel,
623 drive,
624 via_udma33_tim[drvp->UDMA_mode]);
625 }
626 break;
627 case PCI_VENDOR_AMD:
628 case PCI_VENDOR_NVIDIA:
629 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
630 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
631 break;
632 }
633 /* can use PIO timings, MW DMA unused */
634 mode = drvp->PIO_mode;
635 } else {
636 /* use Multiword DMA, but only if revision is OK */
637 s = splbio();
638 drvp->drive_flags &= ~DRIVE_UDMA;
639 splx(s);
640 #ifndef PCIIDE_AMD756_ENABLEDMA
641 /*
642 * The workaround doesn't seem to be necessary
643 * with all drives, so it can be disabled by
644 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
645 * triggered.
646 */
647 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
648 sc->sc_pp->ide_product ==
649 PCI_PRODUCT_AMD_PBC756_IDE &&
650 AMD756_CHIPREV_DISABLEDMA(rev)) {
651 aprint_normal(
652 "%s:%d:%d: multi-word DMA disabled due "
653 "to chip revision\n",
654 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
655 chp->ch_channel, drive);
656 mode = drvp->PIO_mode;
657 s = splbio();
658 drvp->drive_flags &= ~DRIVE_DMA;
659 splx(s);
660 goto pio;
661 }
662 #endif
663 /* mode = min(pio, dma+2) */
664 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
665 mode = drvp->PIO_mode;
666 else
667 mode = drvp->DMA_mode + 2;
668 }
669 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
670
671 pio: /* setup PIO mode */
672 if (mode <= 2) {
673 drvp->DMA_mode = 0;
674 drvp->PIO_mode = 0;
675 mode = 0;
676 } else {
677 drvp->PIO_mode = mode;
678 drvp->DMA_mode = mode - 2;
679 }
680 datatim_reg |=
681 APO_DATATIM_PULSE(chp->ch_channel, drive,
682 apollo_pio_set[mode]) |
683 APO_DATATIM_RECOV(chp->ch_channel, drive,
684 apollo_pio_rec[mode]);
685 }
686 if (idedma_ctl != 0) {
687 /* Add software bits in status register */
688 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
689 idedma_ctl);
690 }
691 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
692 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
693 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
694 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
695 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
696 }
697
698 static int
699 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa)
700 {
701 bus_size_t satasize;
702 int maptype, ret;
703
704 if (pciide_chipen(sc, pa) == 0)
705 return 0;
706
707 aprint_verbose("%s: bus-master DMA support present",
708 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
709 pciide_mapreg_dma(sc, pa);
710 aprint_verbose("\n");
711
712 if (sc->sc_dma_ok) {
713 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
714 sc->sc_wdcdev.irqack = pciide_irqack;
715 }
716 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
717 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
718 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
719
720 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
721 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
722 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
723 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
724
725 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
726 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
727 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
728
729 wdc_allocate_regs(&sc->sc_wdcdev);
730 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
731 PCI_MAPREG_START + 0x14);
732 switch(maptype) {
733 case PCI_MAPREG_TYPE_IO:
734 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
735 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
736 NULL, &satasize);
737 break;
738 case PCI_MAPREG_MEM_TYPE_32BIT:
739 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
740 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
741 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
742 NULL, &satasize);
743 break;
744 default:
745 aprint_error("%s: couldn't map sata regs, unsupported"
746 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
747 maptype);
748 return 0;
749 }
750 if (ret != 0) {
751 aprint_error("%s: couldn't map sata regs\n",
752 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
753 return 0;
754 }
755 return 1;
756 }
757
758 static void
759 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa,
760 int satareg_shift)
761 {
762 struct pciide_channel *cp;
763 struct ata_channel *wdc_cp;
764 struct wdc_regs *wdr;
765 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
766 int channel;
767 bus_size_t cmdsize, ctlsize;
768
769 if (via_sata_chip_map_common(sc, pa) == 0)
770 return;
771
772 if (interface == 0) {
773 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
774 DEBUG_PROBE);
775 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
776 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
777 }
778
779 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
780 channel++) {
781 cp = &sc->pciide_channels[channel];
782 if (pciide_chansetup(sc, channel, interface) == 0)
783 continue;
784 wdc_cp = &cp->ata_channel;
785 wdr = CHAN_TO_WDC_REGS(wdc_cp);
786 wdr->sata_iot = sc->sc_ba5_st;
787 wdr->sata_baseioh = sc->sc_ba5_sh;
788 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
789 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1,
790 &wdr->sata_status) != 0) {
791 aprint_error("%s: couldn't map channel %d "
792 "sata_status regs\n",
793 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
794 wdc_cp->ch_channel);
795 continue;
796 }
797 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
798 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1,
799 &wdr->sata_error) != 0) {
800 aprint_error("%s: couldn't map channel %d "
801 "sata_error regs\n",
802 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
803 wdc_cp->ch_channel);
804 continue;
805 }
806 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
807 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1,
808 &wdr->sata_control) != 0) {
809 aprint_error("%s: couldn't map channel %d "
810 "sata_control regs\n",
811 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
812 wdc_cp->ch_channel);
813 continue;
814 }
815 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
816 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
817 pciide_pci_intr);
818 }
819 }
820
821 static void
822 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa)
823 {
824 via_sata_chip_map(sc, pa, 0);
825 }
826
827 static void
828 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa)
829 {
830 via_sata_chip_map(sc, pa, 6);
831 }
832
833 static void
834 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa)
835 {
836 via_sata_chip_map(sc, pa, 7);
837 }
838
839 static void
840 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa)
841 {
842 struct pciide_channel *cp;
843 struct ata_channel *wdc_cp;
844 struct wdc_regs *wdr;
845 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
846 int channel;
847 bus_size_t cmdsize;
848 pci_intr_handle_t intrhandle;
849 const char *intrstr;
850 int i;
851
852 if (via_sata_chip_map_common(sc, pa) == 0)
853 return;
854
855 if (interface == 0) {
856 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
857 DEBUG_PROBE);
858 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
859 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
860 }
861
862 if (pci_intr_map(pa, &intrhandle) != 0) {
863 aprint_error("%s: couldn't map native-PCI interrupt\n",
864 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
865 return;
866 }
867 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
868 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
869 intrhandle, IPL_BIO, pciide_pci_intr, sc);
870 if (sc->sc_pci_ih == NULL) {
871 aprint_error(
872 "%s: couldn't establish native-PCI interrupt",
873 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
874 if (intrstr != NULL)
875 aprint_error(" at %s", intrstr);
876 aprint_error("\n");
877 return;
878 }
879 aprint_normal("%s: using %s for native-PCI interrupt\n",
880 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
881 intrstr ? intrstr : "unknown interrupt");
882
883 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
884 channel++) {
885 cp = &sc->pciide_channels[channel];
886 if (pciide_chansetup(sc, channel, interface) == 0)
887 continue;
888 cp->ata_channel.ch_ndrive = 1;
889 wdc_cp = &cp->ata_channel;
890 wdr = CHAN_TO_WDC_REGS(wdc_cp);
891
892 wdr->sata_iot = sc->sc_ba5_st;
893 wdr->sata_baseioh = sc->sc_ba5_sh;
894 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
895 (wdc_cp->ch_channel << 6) + 0x0, 1,
896 &wdr->sata_status) != 0) {
897 aprint_error("%s: couldn't map channel %d "
898 "sata_status regs\n",
899 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
900 wdc_cp->ch_channel);
901 continue;
902 }
903 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
904 (wdc_cp->ch_channel << 6) + 0x4, 1,
905 &wdr->sata_error) != 0) {
906 aprint_error("%s: couldn't map channel %d "
907 "sata_error regs\n",
908 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
909 wdc_cp->ch_channel);
910 continue;
911 }
912 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
913 (wdc_cp->ch_channel << 6) + 0x8, 1,
914 &wdr->sata_control) != 0) {
915 aprint_error("%s: couldn't map channel %d "
916 "sata_control regs\n",
917 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
918 wdc_cp->ch_channel);
919 continue;
920 }
921 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
922
923 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))),
924 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
925 NULL, &cmdsize) != 0) {
926 aprint_error("%s: couldn't map %s channel regs\n",
927 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
928 cp->name);
929 }
930 wdr->ctl_iot = wdr->cmd_iot;
931 for (i = 0; i < WDC_NREG; i++) {
932 if (bus_space_subregion(wdr->cmd_iot,
933 wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
934 &wdr->cmd_iohs[i]) != 0) {
935 aprint_error("%s: couldn't subregion %s "
936 "channel cmd regs\n",
937 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
938 cp->name);
939 return;
940 }
941 }
942 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
943 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) {
944 aprint_error("%s: couldn't map channel %d ctl regs\n",
945 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel);
946 return;
947 }
948 wdc_init_shadow_regs(wdc_cp);
949 wdcattach(wdc_cp);
950 }
951 }
952