viaide.c revision 1.41.8.3
1 /* $NetBSD: viaide.c,v 1.41.8.3 2007/11/14 19:04:32 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.41.8.3 2007/11/14 19:04:32 joerg Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_AMD_CS5536_IDE, 91 0, 92 "Advanced Micro Devices CS5536 IDE Controller", 93 via_chip_map 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static const struct pciide_product_desc pciide_nvidia_products[] = { 103 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 104 0, 105 "NVIDIA nForce IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 109 0, 110 "NVIDIA nForce2 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 114 0, 115 "NVIDIA nForce2 Ultra 400 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 119 0, 120 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 121 via_sata_chip_map_6 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 124 0, 125 "NVIDIA nForce3 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 129 0, 130 "NVIDIA nForce3 250 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 139 0, 140 "NVIDIA nForce3 250 Serial ATA Controller", 141 via_sata_chip_map_6 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 144 0, 145 "NVIDIA nForce4 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 154 0, 155 "NVIDIA nForce4 Serial ATA Controller", 156 via_sata_chip_map_6 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 159 0, 160 "NVIDIA nForce430 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 169 0, 170 "NVIDIA nForce430 Serial ATA Controller", 171 via_sata_chip_map_6 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 174 0, 175 "NVIDIA MCP04 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 184 0, 185 "NVIDIA MCP04 Serial ATA Controller", 186 via_sata_chip_map_6 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 189 0, 190 "NVIDIA MCP55 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 199 0, 200 "NVIDIA MCP55 Serial ATA Controller", 201 via_sata_chip_map_6 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 204 0, 205 "NVIDIA MCP61 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 209 0, 210 "NVIDIA MCP65 IDE Controller", 211 via_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 214 0, 215 "NVIDIA MCP73 IDE Controller", 216 via_chip_map 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 219 0, 220 "NVIDIA MCP77 IDE Controller", 221 via_chip_map 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 224 0, 225 "NVIDIA MCP61 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 229 0, 230 "NVIDIA MCP61 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 234 0, 235 "NVIDIA MCP61 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 244 0, 245 "NVIDIA MCP65 Serial ATA Controller", 246 via_sata_chip_map_6 247 }, 248 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 249 0, 250 "NVIDIA MCP65 Serial ATA Controller", 251 via_sata_chip_map_6 252 }, 253 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 254 0, 255 "NVIDIA MCP65 Serial ATA Controller", 256 via_sata_chip_map_6 257 }, 258 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 259 0, 260 "NVIDIA MCP67 IDE Controller", 261 via_chip_map, 262 }, 263 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 264 0, 265 "NVIDIA MCP67 Serial ATA Controller", 266 via_sata_chip_map_6, 267 }, 268 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 269 0, 270 "NVIDIA MCP67 Serial ATA Controller", 271 via_sata_chip_map_6, 272 }, 273 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 274 0, 275 "NVIDIA MCP67 Serial ATA Controller", 276 via_sata_chip_map_6, 277 }, 278 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 279 0, 280 "NVIDIA MCP67 Serial ATA Controller", 281 via_sata_chip_map_6, 282 }, 283 { 0, 284 0, 285 NULL, 286 NULL 287 } 288 }; 289 290 static const struct pciide_product_desc pciide_via_products[] = { 291 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 292 0, 293 NULL, 294 via_chip_map, 295 }, 296 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 297 0, 298 NULL, 299 via_chip_map, 300 }, 301 { PCI_PRODUCT_VIATECH_CX700_IDE, 302 0, 303 NULL, 304 via_chip_map, 305 }, 306 { PCI_PRODUCT_VIATECH_VT6421_RAID, 307 0, 308 "VIA Technologies VT6421 Serial RAID Controller", 309 via_sata_chip_map_new, 310 }, 311 { PCI_PRODUCT_VIATECH_VT8237_SATA, 312 0, 313 "VIA Technologies VT8237 SATA Controller", 314 via_sata_chip_map_7, 315 }, 316 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 317 0, 318 "VIA Technologies VT8237A SATA Controller", 319 via_sata_chip_map_7, 320 }, 321 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 322 0, 323 "VIA Technologies VT8237R SATA Controller", 324 via_sata_chip_map_0, 325 }, 326 { 0, 327 0, 328 NULL, 329 NULL 330 } 331 }; 332 333 static const struct pciide_product_desc * 334 viaide_lookup(pcireg_t id) 335 { 336 337 switch (PCI_VENDOR(id)) { 338 case PCI_VENDOR_VIATECH: 339 return (pciide_lookup_product(id, pciide_via_products)); 340 341 case PCI_VENDOR_AMD: 342 return (pciide_lookup_product(id, pciide_amd_products)); 343 344 case PCI_VENDOR_NVIDIA: 345 return (pciide_lookup_product(id, pciide_nvidia_products)); 346 } 347 return (NULL); 348 } 349 350 static int 351 viaide_match(struct device *parent, struct cfdata *match, 352 void *aux) 353 { 354 struct pci_attach_args *pa = aux; 355 356 if (viaide_lookup(pa->pa_id) != NULL) 357 return (2); 358 return (0); 359 } 360 361 static void 362 viaide_attach(struct device *parent, struct device *self, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 struct pciide_softc *sc = (struct pciide_softc *)self; 366 const struct pciide_product_desc *pp; 367 368 pp = viaide_lookup(pa->pa_id); 369 if (pp == NULL) 370 panic("viaide_attach"); 371 pciide_common_attach(sc, pa, pp); 372 } 373 374 static int 375 via_pcib_match(struct pci_attach_args *pa) 376 { 377 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 378 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 379 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 380 return (1); 381 return 0; 382 } 383 384 static void 385 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 386 { 387 struct pciide_channel *cp; 388 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 389 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 390 int channel; 391 u_int32_t ideconf; 392 bus_size_t cmdsize, ctlsize; 393 pcireg_t pcib_id, pcib_class; 394 struct pci_attach_args pcib_pa; 395 396 if (pciide_chipen(sc, pa) == 0) 397 return; 398 399 switch (vendor) { 400 case PCI_VENDOR_VIATECH: 401 /* 402 * get a PCI tag for the ISA bridge. 403 */ 404 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 405 goto unknown; 406 pcib_id = pcib_pa.pa_id; 407 pcib_class = pcib_pa.pa_class; 408 aprint_normal("%s: VIA Technologies ", 409 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 410 switch (PCI_PRODUCT(pcib_id)) { 411 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 412 aprint_normal("VT82C586 (Apollo VP) "); 413 if(PCI_REVISION(pcib_class) >= 0x02) { 414 aprint_normal("ATA33 controller\n"); 415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 416 } else { 417 aprint_normal("controller\n"); 418 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 419 } 420 break; 421 case PCI_PRODUCT_VIATECH_VT82C596A: 422 aprint_normal("VT82C596A (Apollo Pro) "); 423 if (PCI_REVISION(pcib_class) >= 0x12) { 424 aprint_normal("ATA66 controller\n"); 425 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 426 } else { 427 aprint_normal("ATA33 controller\n"); 428 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 429 } 430 break; 431 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 432 aprint_normal("VT82C686A (Apollo KX133) "); 433 if (PCI_REVISION(pcib_class) >= 0x40) { 434 aprint_normal("ATA100 controller\n"); 435 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 436 } else { 437 aprint_normal("ATA66 controller\n"); 438 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 439 } 440 break; 441 case PCI_PRODUCT_VIATECH_VT8231: 442 aprint_normal("VT8231 ATA100 controller\n"); 443 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 444 break; 445 case PCI_PRODUCT_VIATECH_VT8233: 446 aprint_normal("VT8233 ATA100 controller\n"); 447 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 448 break; 449 case PCI_PRODUCT_VIATECH_VT8233A: 450 aprint_normal("VT8233A ATA133 controller\n"); 451 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 452 break; 453 case PCI_PRODUCT_VIATECH_VT8235: 454 aprint_normal("VT8235 ATA133 controller\n"); 455 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 456 break; 457 case PCI_PRODUCT_VIATECH_VT8237: 458 aprint_normal("VT8237 ATA133 controller\n"); 459 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 460 break; 461 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 462 aprint_normal("VT8237A ATA133 controller\n"); 463 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 464 break; 465 case PCI_PRODUCT_VIATECH_CX700_IDE: 466 aprint_normal("CX700 ATA133 controller\n"); 467 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 468 break; 469 default: 470 unknown: 471 aprint_normal("unknown VIA ATA controller\n"); 472 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 473 } 474 sc->sc_apo_regbase = APO_VIA_REGBASE; 475 break; 476 case PCI_VENDOR_AMD: 477 switch (sc->sc_pp->ide_product) { 478 case PCI_PRODUCT_AMD_PBC8111_IDE: 479 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 480 break; 481 case PCI_PRODUCT_AMD_CS5536_IDE: 482 case PCI_PRODUCT_AMD_PBC766_IDE: 483 case PCI_PRODUCT_AMD_PBC768_IDE: 484 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 485 break; 486 default: 487 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 488 } 489 sc->sc_apo_regbase = APO_AMD_REGBASE; 490 break; 491 case PCI_VENDOR_NVIDIA: 492 switch (sc->sc_pp->ide_product) { 493 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 495 break; 496 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 497 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 498 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 499 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 500 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 501 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 502 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 503 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 504 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 505 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 506 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 507 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 508 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 509 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 510 break; 511 } 512 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 513 break; 514 default: 515 panic("via_chip_map: unknown vendor"); 516 } 517 518 aprint_verbose("%s: bus-master DMA support present", 519 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 520 pciide_mapreg_dma(sc, pa); 521 aprint_verbose("\n"); 522 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 523 if (sc->sc_dma_ok) { 524 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 525 sc->sc_wdcdev.irqack = pciide_irqack; 526 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 527 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 528 } 529 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 530 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 531 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 532 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 533 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 534 535 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 536 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 537 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 538 539 wdc_allocate_regs(&sc->sc_wdcdev); 540 541 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 542 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 543 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 544 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 545 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 546 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 547 DEBUG_PROBE); 548 549 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 550 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 551 channel++) { 552 cp = &sc->pciide_channels[channel]; 553 if (pciide_chansetup(sc, channel, interface) == 0) 554 continue; 555 556 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 557 aprint_normal("%s: %s channel ignored (disabled)\n", 558 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 559 cp->ata_channel.ch_flags |= ATACH_DISABLED; 560 continue; 561 } 562 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 563 pciide_pci_intr); 564 } 565 } 566 567 static void 568 via_setup_channel(struct ata_channel *chp) 569 { 570 u_int32_t udmatim_reg, datatim_reg; 571 u_int8_t idedma_ctl; 572 int mode, drive, s; 573 struct ata_drive_datas *drvp; 574 struct atac_softc *atac = chp->ch_atac; 575 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 576 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 577 #ifndef PCIIDE_AMD756_ENABLEDMA 578 int rev = PCI_REVISION( 579 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 580 #endif 581 582 idedma_ctl = 0; 583 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 584 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 585 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 586 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 587 588 /* setup DMA if needed */ 589 pciide_channel_dma_setup(cp); 590 591 for (drive = 0; drive < 2; drive++) { 592 drvp = &chp->ch_drive[drive]; 593 /* If no drive, skip */ 594 if ((drvp->drive_flags & DRIVE) == 0) 595 continue; 596 /* add timing values, setup DMA if needed */ 597 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 598 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 599 mode = drvp->PIO_mode; 600 goto pio; 601 } 602 if ((atac->atac_cap & ATAC_CAP_UDMA) && 603 (drvp->drive_flags & DRIVE_UDMA)) { 604 /* use Ultra/DMA */ 605 s = splbio(); 606 drvp->drive_flags &= ~DRIVE_DMA; 607 splx(s); 608 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 609 APO_UDMA_EN_MTH(chp->ch_channel, drive); 610 switch (PCI_VENDOR(sc->sc_pci_id)) { 611 case PCI_VENDOR_VIATECH: 612 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 613 /* 8233a */ 614 udmatim_reg |= APO_UDMA_TIME( 615 chp->ch_channel, 616 drive, 617 via_udma133_tim[drvp->UDMA_mode]); 618 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 619 /* 686b */ 620 udmatim_reg |= APO_UDMA_TIME( 621 chp->ch_channel, 622 drive, 623 via_udma100_tim[drvp->UDMA_mode]); 624 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 625 /* 596b or 686a */ 626 udmatim_reg |= APO_UDMA_CLK66( 627 chp->ch_channel); 628 udmatim_reg |= APO_UDMA_TIME( 629 chp->ch_channel, 630 drive, 631 via_udma66_tim[drvp->UDMA_mode]); 632 } else { 633 /* 596a or 586b */ 634 udmatim_reg |= APO_UDMA_TIME( 635 chp->ch_channel, 636 drive, 637 via_udma33_tim[drvp->UDMA_mode]); 638 } 639 break; 640 case PCI_VENDOR_AMD: 641 case PCI_VENDOR_NVIDIA: 642 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 643 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 644 break; 645 } 646 /* can use PIO timings, MW DMA unused */ 647 mode = drvp->PIO_mode; 648 } else { 649 /* use Multiword DMA, but only if revision is OK */ 650 s = splbio(); 651 drvp->drive_flags &= ~DRIVE_UDMA; 652 splx(s); 653 #ifndef PCIIDE_AMD756_ENABLEDMA 654 /* 655 * The workaround doesn't seem to be necessary 656 * with all drives, so it can be disabled by 657 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 658 * triggered. 659 */ 660 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 661 sc->sc_pp->ide_product == 662 PCI_PRODUCT_AMD_PBC756_IDE && 663 AMD756_CHIPREV_DISABLEDMA(rev)) { 664 aprint_normal( 665 "%s:%d:%d: multi-word DMA disabled due " 666 "to chip revision\n", 667 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 668 chp->ch_channel, drive); 669 mode = drvp->PIO_mode; 670 s = splbio(); 671 drvp->drive_flags &= ~DRIVE_DMA; 672 splx(s); 673 goto pio; 674 } 675 #endif 676 /* mode = min(pio, dma+2) */ 677 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 678 mode = drvp->PIO_mode; 679 else 680 mode = drvp->DMA_mode + 2; 681 } 682 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 683 684 pio: /* setup PIO mode */ 685 if (mode <= 2) { 686 drvp->DMA_mode = 0; 687 drvp->PIO_mode = 0; 688 mode = 0; 689 } else { 690 drvp->PIO_mode = mode; 691 drvp->DMA_mode = mode - 2; 692 } 693 datatim_reg |= 694 APO_DATATIM_PULSE(chp->ch_channel, drive, 695 apollo_pio_set[mode]) | 696 APO_DATATIM_RECOV(chp->ch_channel, drive, 697 apollo_pio_rec[mode]); 698 } 699 if (idedma_ctl != 0) { 700 /* Add software bits in status register */ 701 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 702 idedma_ctl); 703 } 704 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 705 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 706 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 707 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 708 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 709 } 710 711 static int 712 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 713 { 714 bus_size_t satasize; 715 int maptype, ret; 716 717 if (pciide_chipen(sc, pa) == 0) 718 return 0; 719 720 aprint_verbose("%s: bus-master DMA support present", 721 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 722 pciide_mapreg_dma(sc, pa); 723 aprint_verbose("\n"); 724 725 if (sc->sc_dma_ok) { 726 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 727 sc->sc_wdcdev.irqack = pciide_irqack; 728 } 729 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 730 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 731 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 732 733 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 734 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 735 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 736 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 737 738 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 739 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 740 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 741 742 wdc_allocate_regs(&sc->sc_wdcdev); 743 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 744 PCI_MAPREG_START + 0x14); 745 switch(maptype) { 746 case PCI_MAPREG_TYPE_IO: 747 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 748 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 749 NULL, &satasize); 750 break; 751 case PCI_MAPREG_MEM_TYPE_32BIT: 752 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 753 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 754 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 755 NULL, &satasize); 756 break; 757 default: 758 aprint_error("%s: couldn't map sata regs, unsupported" 759 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 760 maptype); 761 return 0; 762 } 763 if (ret != 0) { 764 aprint_error("%s: couldn't map sata regs\n", 765 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 766 return 0; 767 } 768 return 1; 769 } 770 771 static void 772 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 773 int satareg_shift) 774 { 775 struct pciide_channel *cp; 776 struct ata_channel *wdc_cp; 777 struct wdc_regs *wdr; 778 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 779 int channel; 780 bus_size_t cmdsize, ctlsize; 781 782 if (via_sata_chip_map_common(sc, pa) == 0) 783 return; 784 785 if (interface == 0) { 786 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 787 DEBUG_PROBE); 788 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 789 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 790 } 791 792 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 793 channel++) { 794 cp = &sc->pciide_channels[channel]; 795 if (pciide_chansetup(sc, channel, interface) == 0) 796 continue; 797 wdc_cp = &cp->ata_channel; 798 wdr = CHAN_TO_WDC_REGS(wdc_cp); 799 wdr->sata_iot = sc->sc_ba5_st; 800 wdr->sata_baseioh = sc->sc_ba5_sh; 801 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 802 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 803 &wdr->sata_status) != 0) { 804 aprint_error("%s: couldn't map channel %d " 805 "sata_status regs\n", 806 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 807 wdc_cp->ch_channel); 808 continue; 809 } 810 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 811 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 812 &wdr->sata_error) != 0) { 813 aprint_error("%s: couldn't map channel %d " 814 "sata_error regs\n", 815 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 816 wdc_cp->ch_channel); 817 continue; 818 } 819 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 820 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 821 &wdr->sata_control) != 0) { 822 aprint_error("%s: couldn't map channel %d " 823 "sata_control regs\n", 824 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 825 wdc_cp->ch_channel); 826 continue; 827 } 828 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 829 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 830 pciide_pci_intr); 831 } 832 } 833 834 static void 835 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 836 { 837 via_sata_chip_map(sc, pa, 0); 838 } 839 840 static void 841 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 842 { 843 via_sata_chip_map(sc, pa, 6); 844 } 845 846 static void 847 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 848 { 849 via_sata_chip_map(sc, pa, 7); 850 } 851 852 static void 853 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 854 { 855 struct pciide_channel *cp; 856 struct ata_channel *wdc_cp; 857 struct wdc_regs *wdr; 858 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 859 int channel; 860 bus_size_t cmdsize; 861 pci_intr_handle_t intrhandle; 862 const char *intrstr; 863 int i; 864 865 if (via_sata_chip_map_common(sc, pa) == 0) 866 return; 867 868 if (interface == 0) { 869 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 870 DEBUG_PROBE); 871 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 872 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 873 } 874 875 if (pci_intr_map(pa, &intrhandle) != 0) { 876 aprint_error("%s: couldn't map native-PCI interrupt\n", 877 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 878 return; 879 } 880 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 881 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 882 intrhandle, IPL_BIO, pciide_pci_intr, sc); 883 if (sc->sc_pci_ih == NULL) { 884 aprint_error( 885 "%s: couldn't establish native-PCI interrupt", 886 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 887 if (intrstr != NULL) 888 aprint_error(" at %s", intrstr); 889 aprint_error("\n"); 890 return; 891 } 892 aprint_normal("%s: using %s for native-PCI interrupt\n", 893 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 894 intrstr ? intrstr : "unknown interrupt"); 895 896 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 897 channel++) { 898 cp = &sc->pciide_channels[channel]; 899 if (pciide_chansetup(sc, channel, interface) == 0) 900 continue; 901 cp->ata_channel.ch_ndrive = 1; 902 wdc_cp = &cp->ata_channel; 903 wdr = CHAN_TO_WDC_REGS(wdc_cp); 904 905 wdr->sata_iot = sc->sc_ba5_st; 906 wdr->sata_baseioh = sc->sc_ba5_sh; 907 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 908 (wdc_cp->ch_channel << 6) + 0x0, 1, 909 &wdr->sata_status) != 0) { 910 aprint_error("%s: couldn't map channel %d " 911 "sata_status regs\n", 912 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 913 wdc_cp->ch_channel); 914 continue; 915 } 916 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 917 (wdc_cp->ch_channel << 6) + 0x4, 1, 918 &wdr->sata_error) != 0) { 919 aprint_error("%s: couldn't map channel %d " 920 "sata_error regs\n", 921 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 922 wdc_cp->ch_channel); 923 continue; 924 } 925 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 926 (wdc_cp->ch_channel << 6) + 0x8, 1, 927 &wdr->sata_control) != 0) { 928 aprint_error("%s: couldn't map channel %d " 929 "sata_control regs\n", 930 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 931 wdc_cp->ch_channel); 932 continue; 933 } 934 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 935 936 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 937 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 938 NULL, &cmdsize) != 0) { 939 aprint_error("%s: couldn't map %s channel regs\n", 940 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 941 cp->name); 942 } 943 wdr->ctl_iot = wdr->cmd_iot; 944 for (i = 0; i < WDC_NREG; i++) { 945 if (bus_space_subregion(wdr->cmd_iot, 946 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 947 &wdr->cmd_iohs[i]) != 0) { 948 aprint_error("%s: couldn't subregion %s " 949 "channel cmd regs\n", 950 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 951 cp->name); 952 return; 953 } 954 } 955 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 956 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 957 aprint_error("%s: couldn't map channel %d ctl regs\n", 958 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 959 return; 960 } 961 wdc_init_shadow_regs(wdc_cp); 962 wdcattach(wdc_cp); 963 } 964 } 965
Indexes created Mon Oct 20 20:10:13 GMT 2025