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viaide.c revision 1.43
      1 /*	$NetBSD: viaide.c,v 1.43 2007/08/31 01:37:46 xtraeme Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Manuel Bouyer.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  *
     31  */
     32 
     33 #include <sys/cdefs.h>
     34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.43 2007/08/31 01:37:46 xtraeme Exp $");
     35 
     36 #include <sys/param.h>
     37 #include <sys/systm.h>
     38 
     39 #include <dev/pci/pcivar.h>
     40 #include <dev/pci/pcidevs.h>
     41 #include <dev/pci/pciidereg.h>
     42 #include <dev/pci/pciidevar.h>
     43 #include <dev/pci/pciide_apollo_reg.h>
     44 
     45 static int	via_pcib_match(struct pci_attach_args *);
     46 static void	via_chip_map(struct pciide_softc *, struct pci_attach_args *);
     47 static int	via_sata_chip_map_common(struct pciide_softc *,
     48 		    struct pci_attach_args *);
     49 static void	via_sata_chip_map(struct pciide_softc *,
     50 		    struct pci_attach_args *, int);
     51 static void	via_sata_chip_map_0(struct pciide_softc *,
     52 		    struct pci_attach_args *);
     53 static void	via_sata_chip_map_6(struct pciide_softc *,
     54 		    struct pci_attach_args *);
     55 static void	via_sata_chip_map_7(struct pciide_softc *,
     56 		    struct pci_attach_args *);
     57 static void	via_sata_chip_map_new(struct pciide_softc *,
     58 		    struct pci_attach_args *);
     59 static void	via_setup_channel(struct ata_channel *);
     60 
     61 static int	viaide_match(struct device *, struct cfdata *, void *);
     62 static void	viaide_attach(struct device *, struct device *, void *);
     63 static const struct pciide_product_desc *
     64 		viaide_lookup(pcireg_t);
     65 
     66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc),
     67     viaide_match, viaide_attach, NULL, NULL);
     68 
     69 static const struct pciide_product_desc pciide_amd_products[] =  {
     70 	{ PCI_PRODUCT_AMD_PBC756_IDE,
     71 	  0,
     72 	  "Advanced Micro Devices AMD756 IDE Controller",
     73 	  via_chip_map
     74 	},
     75 	{ PCI_PRODUCT_AMD_PBC766_IDE,
     76 	  0,
     77 	  "Advanced Micro Devices AMD766 IDE Controller",
     78 	  via_chip_map
     79 	},
     80 	{ PCI_PRODUCT_AMD_PBC768_IDE,
     81 	  0,
     82 	  "Advanced Micro Devices AMD768 IDE Controller",
     83 	  via_chip_map
     84 	},
     85 	{ PCI_PRODUCT_AMD_PBC8111_IDE,
     86 	  0,
     87 	  "Advanced Micro Devices AMD8111 IDE Controller",
     88 	  via_chip_map
     89 	},
     90 	{ PCI_PRODUCT_AMD_CS5536_IDE,
     91 	  0,
     92 	  "Advanced Micro Devices CS5536 IDE Controller",
     93 	  via_chip_map
     94 	},
     95 	{ 0,
     96 	  0,
     97 	  NULL,
     98 	  NULL
     99 	}
    100 };
    101 
    102 static const struct pciide_product_desc pciide_nvidia_products[] = {
    103 	{ PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
    104 	  0,
    105 	  "NVIDIA nForce IDE Controller",
    106 	  via_chip_map
    107 	},
    108 	{ PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
    109 	  0,
    110 	  "NVIDIA nForce2 IDE Controller",
    111 	  via_chip_map
    112 	},
    113 	{ PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
    114 	  0,
    115 	  "NVIDIA nForce2 Ultra 400 IDE Controller",
    116 	  via_chip_map
    117 	},
    118 	{ PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
    119 	  0,
    120 	  "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
    121 	  via_sata_chip_map_6
    122 	},
    123 	{ PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
    124 	  0,
    125 	  "NVIDIA nForce3 IDE Controller",
    126 	  via_chip_map
    127 	},
    128 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
    129 	  0,
    130 	  "NVIDIA nForce3 250 IDE Controller",
    131 	  via_chip_map
    132 	},
    133 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
    134 	  0,
    135 	  "NVIDIA nForce3 250 Serial ATA Controller",
    136 	  via_sata_chip_map_6
    137 	},
    138 	{ PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
    139 	  0,
    140 	  "NVIDIA nForce3 250 Serial ATA Controller",
    141 	  via_sata_chip_map_6
    142 	},
    143 	{ PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
    144 	  0,
    145 	  "NVIDIA nForce4 IDE Controller",
    146 	  via_chip_map
    147 	},
    148 	{ PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
    149 	  0,
    150 	  "NVIDIA nForce4 Serial ATA Controller",
    151 	  via_sata_chip_map_6
    152 	},
    153 	{ PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
    154 	  0,
    155 	  "NVIDIA nForce4 Serial ATA Controller",
    156 	  via_sata_chip_map_6
    157 	},
    158 	{ PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
    159 	  0,
    160 	  "NVIDIA nForce430 IDE Controller",
    161 	  via_chip_map
    162 	},
    163 	{ PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
    164 	  0,
    165 	  "NVIDIA nForce430 Serial ATA Controller",
    166 	  via_sata_chip_map_6
    167 	},
    168 	{ PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
    169 	  0,
    170 	  "NVIDIA nForce430 Serial ATA Controller",
    171 	  via_sata_chip_map_6
    172 	},
    173 	{ PCI_PRODUCT_NVIDIA_MCP04_IDE,
    174 	  0,
    175 	  "NVIDIA MCP04 IDE Controller",
    176 	  via_chip_map
    177 	},
    178 	{ PCI_PRODUCT_NVIDIA_MCP04_SATA,
    179 	  0,
    180 	  "NVIDIA MCP04 Serial ATA Controller",
    181 	  via_sata_chip_map_6
    182 	},
    183 	{ PCI_PRODUCT_NVIDIA_MCP04_SATA2,
    184 	  0,
    185 	  "NVIDIA MCP04 Serial ATA Controller",
    186 	  via_sata_chip_map_6
    187 	},
    188 	{ PCI_PRODUCT_NVIDIA_MCP55_IDE,
    189 	  0,
    190 	  "NVIDIA MCP55 IDE Controller",
    191 	  via_chip_map
    192 	},
    193 	{ PCI_PRODUCT_NVIDIA_MCP55_SATA,
    194 	  0,
    195 	  "NVIDIA MCP55 Serial ATA Controller",
    196 	  via_sata_chip_map_6
    197 	},
    198 	{ PCI_PRODUCT_NVIDIA_MCP55_SATA2,
    199 	  0,
    200 	  "NVIDIA MCP55 Serial ATA Controller",
    201 	  via_sata_chip_map_6
    202 	},
    203 	{ PCI_PRODUCT_NVIDIA_MCP61_IDE,
    204 	  0,
    205 	  "NVIDIA MCP61 IDE Controller",
    206 	  via_chip_map
    207 	},
    208 	{ PCI_PRODUCT_NVIDIA_MCP65_IDE,
    209 	  0,
    210 	  "NVIDIA MCP65 IDE Controller",
    211 	  via_chip_map
    212 	},
    213 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA,
    214 	  0,
    215 	  "NVIDIA MCP61 Serial ATA Controller",
    216 	  via_sata_chip_map_6
    217 	},
    218 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA2,
    219 	  0,
    220 	  "NVIDIA MCP61 Serial ATA Controller",
    221 	  via_sata_chip_map_6
    222 	},
    223 	{ PCI_PRODUCT_NVIDIA_MCP61_SATA3,
    224 	  0,
    225 	  "NVIDIA MCP61 Serial ATA Controller",
    226 	  via_sata_chip_map_6
    227 	},
    228 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA,
    229 	  0,
    230 	  "NVIDIA MCP65 Serial ATA Controller",
    231 	  via_sata_chip_map_6
    232 	},
    233 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA2,
    234 	  0,
    235 	  "NVIDIA MCP65 Serial ATA Controller",
    236 	  via_sata_chip_map_6
    237 	},
    238 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA3,
    239 	  0,
    240 	  "NVIDIA MCP65 Serial ATA Controller",
    241 	  via_sata_chip_map_6
    242 	},
    243 	{ PCI_PRODUCT_NVIDIA_MCP65_SATA4,
    244 	  0,
    245 	  "NVIDIA MCP65 Serial ATA Controller",
    246 	  via_sata_chip_map_6
    247 	},
    248 	{ PCI_PRODUCT_NVIDIA_MCP67_IDE,
    249 	  0,
    250 	  "NVIDIA MCP67 IDE Controller",
    251 	  via_chip_map,
    252 	},
    253 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA,
    254 	  0,
    255 	  "NVIDIA MCP67 Serial ATA Controller",
    256 	  via_sata_chip_map_6,
    257 	},
    258 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA2,
    259 	  0,
    260 	  "NVIDIA MCP67 Serial ATA Controller",
    261 	  via_sata_chip_map_6,
    262 	},
    263 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA3,
    264 	  0,
    265 	  "NVIDIA MCP67 Serial ATA Controller",
    266 	  via_sata_chip_map_6,
    267 	},
    268 	{ PCI_PRODUCT_NVIDIA_MCP67_SATA4,
    269 	  0,
    270 	  "NVIDIA MCP67 Serial ATA Controller",
    271 	  via_sata_chip_map_6,
    272 	},
    273 	{ 0,
    274 	  0,
    275 	  NULL,
    276 	  NULL
    277 	}
    278 };
    279 
    280 static const struct pciide_product_desc pciide_via_products[] =  {
    281 	{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
    282 	  0,
    283 	  NULL,
    284 	  via_chip_map,
    285 	 },
    286 	{ PCI_PRODUCT_VIATECH_VT82C586A_IDE,
    287 	  0,
    288 	  NULL,
    289 	  via_chip_map,
    290 	},
    291 	{ PCI_PRODUCT_VIATECH_CX700_IDE,
    292 	  0,
    293 	  "VIA Technologies CX700 IDE Controller",
    294 	  via_chip_map,
    295 	},
    296 	{ PCI_PRODUCT_VIATECH_VT6421_RAID,
    297 	  0,
    298 	  "VIA Technologies VT6421 Serial RAID Controller",
    299 	  via_sata_chip_map_new,
    300 	},
    301 	{ PCI_PRODUCT_VIATECH_VT8237_SATA,
    302 	  0,
    303 	  "VIA Technologies VT8237 SATA Controller",
    304 	  via_sata_chip_map_7,
    305 	},
    306 	{ PCI_PRODUCT_VIATECH_VT8237A_SATA,
    307 	  0,
    308 	  "VIA Technologies VT8237A SATA Controller",
    309 	  via_sata_chip_map_7,
    310 	},
    311 	{ PCI_PRODUCT_VIATECH_VT8237R_SATA,
    312 	  0,
    313 	  "VIA Technologies VT8237R SATA Controller",
    314 	  via_sata_chip_map_0,
    315 	},
    316 	{ 0,
    317 	  0,
    318 	  NULL,
    319 	  NULL
    320 	}
    321 };
    322 
    323 static const struct pciide_product_desc *
    324 viaide_lookup(pcireg_t id)
    325 {
    326 
    327 	switch (PCI_VENDOR(id)) {
    328 	case PCI_VENDOR_VIATECH:
    329 		return (pciide_lookup_product(id, pciide_via_products));
    330 
    331 	case PCI_VENDOR_AMD:
    332 		return (pciide_lookup_product(id, pciide_amd_products));
    333 
    334 	case PCI_VENDOR_NVIDIA:
    335 		return (pciide_lookup_product(id, pciide_nvidia_products));
    336 	}
    337 	return (NULL);
    338 }
    339 
    340 static int
    341 viaide_match(struct device *parent, struct cfdata *match,
    342     void *aux)
    343 {
    344 	struct pci_attach_args *pa = aux;
    345 
    346 	if (viaide_lookup(pa->pa_id) != NULL)
    347 		return (2);
    348 	return (0);
    349 }
    350 
    351 static void
    352 viaide_attach(struct device *parent, struct device *self, void *aux)
    353 {
    354 	struct pci_attach_args *pa = aux;
    355 	struct pciide_softc *sc = (struct pciide_softc *)self;
    356 	const struct pciide_product_desc *pp;
    357 
    358 	pp = viaide_lookup(pa->pa_id);
    359 	if (pp == NULL)
    360 		panic("viaide_attach");
    361 	pciide_common_attach(sc, pa, pp);
    362 }
    363 
    364 static int
    365 via_pcib_match(struct pci_attach_args *pa)
    366 {
    367 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
    368 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
    369 	    PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
    370 		return (1);
    371 	return 0;
    372 }
    373 
    374 static void
    375 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    376 {
    377 	struct pciide_channel *cp;
    378 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    379 	pcireg_t vendor = PCI_VENDOR(pa->pa_id);
    380 	int channel;
    381 	u_int32_t ideconf;
    382 	bus_size_t cmdsize, ctlsize;
    383 	pcireg_t pcib_id, pcib_class;
    384 	struct pci_attach_args pcib_pa;
    385 
    386 	if (pciide_chipen(sc, pa) == 0)
    387 		return;
    388 
    389 	switch (vendor) {
    390 	case PCI_VENDOR_VIATECH:
    391 		/*
    392 		 * get a PCI tag for the ISA bridge.
    393 		 */
    394 		if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
    395 			goto unknown;
    396 		pcib_id = pcib_pa.pa_id;
    397 		pcib_class = pcib_pa.pa_class;
    398 		aprint_normal("%s: VIA Technologies ",
    399 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    400 		switch (PCI_PRODUCT(pcib_id)) {
    401 		case PCI_PRODUCT_VIATECH_VT82C586_ISA:
    402 			aprint_normal("VT82C586 (Apollo VP) ");
    403 			if(PCI_REVISION(pcib_class) >= 0x02) {
    404 				aprint_normal("ATA33 controller\n");
    405 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    406 			} else {
    407 				aprint_normal("controller\n");
    408 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
    409 			}
    410 			break;
    411 		case PCI_PRODUCT_VIATECH_VT82C596A:
    412 			aprint_normal("VT82C596A (Apollo Pro) ");
    413 			if (PCI_REVISION(pcib_class) >= 0x12) {
    414 				aprint_normal("ATA66 controller\n");
    415 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    416 			} else {
    417 				aprint_normal("ATA33 controller\n");
    418 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    419 			}
    420 			break;
    421 		case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
    422 			aprint_normal("VT82C686A (Apollo KX133) ");
    423 			if (PCI_REVISION(pcib_class) >= 0x40) {
    424 				aprint_normal("ATA100 controller\n");
    425 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    426 			} else {
    427 				aprint_normal("ATA66 controller\n");
    428 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    429 			}
    430 			break;
    431 		case PCI_PRODUCT_VIATECH_VT8231:
    432 			aprint_normal("VT8231 ATA100 controller\n");
    433 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    434 			break;
    435 		case PCI_PRODUCT_VIATECH_VT8233:
    436 			aprint_normal("VT8233 ATA100 controller\n");
    437 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    438 			break;
    439 		case PCI_PRODUCT_VIATECH_VT8233A:
    440 			aprint_normal("VT8233A ATA133 controller\n");
    441 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    442 			break;
    443 		case PCI_PRODUCT_VIATECH_VT8235:
    444 			aprint_normal("VT8235 ATA133 controller\n");
    445 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    446 			break;
    447 		case PCI_PRODUCT_VIATECH_VT8237:
    448 		case PCI_PRODUCT_VIATECH_CX700_IDE:
    449 			aprint_normal("VT8237 ATA133 controller\n");
    450 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    451 			break;
    452 		case PCI_PRODUCT_VIATECH_VT8237A_ISA:
    453 			aprint_normal("VT8237A ATA133 controller\n");
    454 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    455 			break;
    456 		default:
    457 unknown:
    458 			aprint_normal("unknown VIA ATA controller\n");
    459 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
    460 		}
    461 		sc->sc_apo_regbase = APO_VIA_REGBASE;
    462 		break;
    463 	case PCI_VENDOR_AMD:
    464 		switch (sc->sc_pp->ide_product) {
    465 		case PCI_PRODUCT_AMD_PBC8111_IDE:
    466 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    467 			break;
    468 		case PCI_PRODUCT_AMD_PBC766_IDE:
    469 		case PCI_PRODUCT_AMD_PBC768_IDE:
    470 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    471 			break;
    472 		default:
    473 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    474 		}
    475 		sc->sc_apo_regbase = APO_AMD_REGBASE;
    476 		break;
    477 	case PCI_VENDOR_NVIDIA:
    478 		switch (sc->sc_pp->ide_product) {
    479 		case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
    480 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    481 			break;
    482 		case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
    483 		case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
    484 		case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
    485 		case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
    486 		case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
    487 		case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
    488 		case PCI_PRODUCT_NVIDIA_MCP04_IDE:
    489 		case PCI_PRODUCT_NVIDIA_MCP55_IDE:
    490 		case PCI_PRODUCT_NVIDIA_MCP61_IDE:
    491 		case PCI_PRODUCT_NVIDIA_MCP65_IDE:
    492 		case PCI_PRODUCT_NVIDIA_MCP67_IDE:
    493 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    494 			break;
    495 		}
    496 		sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
    497 		break;
    498 	default:
    499 		panic("via_chip_map: unknown vendor");
    500 	}
    501 
    502 	aprint_verbose("%s: bus-master DMA support present",
    503 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    504 	pciide_mapreg_dma(sc, pa);
    505 	aprint_verbose("\n");
    506 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    507 	if (sc->sc_dma_ok) {
    508 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
    509 		sc->sc_wdcdev.irqack = pciide_irqack;
    510 		if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
    511 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    512 	}
    513 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    514 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    515 	sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
    516 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    517 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    518 
    519 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
    520 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
    521 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
    522 
    523 	wdc_allocate_regs(&sc->sc_wdcdev);
    524 
    525 	ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
    526 	    "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
    527 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
    528 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
    529 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
    530 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
    531 	    DEBUG_PROBE);
    532 
    533 	ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
    534 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    535 	     channel++) {
    536 		cp = &sc->pciide_channels[channel];
    537 		if (pciide_chansetup(sc, channel, interface) == 0)
    538 			continue;
    539 
    540 		if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
    541 			aprint_normal("%s: %s channel ignored (disabled)\n",
    542 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
    543 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
    544 			continue;
    545 		}
    546 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
    547 		    pciide_pci_intr);
    548 	}
    549 }
    550 
    551 static void
    552 via_setup_channel(struct ata_channel *chp)
    553 {
    554 	u_int32_t udmatim_reg, datatim_reg;
    555 	u_int8_t idedma_ctl;
    556 	int mode, drive, s;
    557 	struct ata_drive_datas *drvp;
    558 	struct atac_softc *atac = chp->ch_atac;
    559 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    560 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    561 #ifndef PCIIDE_AMD756_ENABLEDMA
    562 	int rev = PCI_REVISION(
    563 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
    564 #endif
    565 
    566 	idedma_ctl = 0;
    567 	datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
    568 	udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
    569 	datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
    570 	udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
    571 
    572 	/* setup DMA if needed */
    573 	pciide_channel_dma_setup(cp);
    574 
    575 	for (drive = 0; drive < 2; drive++) {
    576 		drvp = &chp->ch_drive[drive];
    577 		/* If no drive, skip */
    578 		if ((drvp->drive_flags & DRIVE) == 0)
    579 			continue;
    580 		/* add timing values, setup DMA if needed */
    581 		if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
    582 		    (drvp->drive_flags & DRIVE_UDMA) == 0)) {
    583 			mode = drvp->PIO_mode;
    584 			goto pio;
    585 		}
    586 		if ((atac->atac_cap & ATAC_CAP_UDMA) &&
    587 		    (drvp->drive_flags & DRIVE_UDMA)) {
    588 			/* use Ultra/DMA */
    589 			s = splbio();
    590 			drvp->drive_flags &= ~DRIVE_DMA;
    591 			splx(s);
    592 			udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
    593 			    APO_UDMA_EN_MTH(chp->ch_channel, drive);
    594 			switch (PCI_VENDOR(sc->sc_pci_id)) {
    595 			case PCI_VENDOR_VIATECH:
    596 				if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
    597 					/* 8233a */
    598 					udmatim_reg |= APO_UDMA_TIME(
    599 					    chp->ch_channel,
    600 					    drive,
    601 					    via_udma133_tim[drvp->UDMA_mode]);
    602 				} else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
    603 					/* 686b */
    604 					udmatim_reg |= APO_UDMA_TIME(
    605 					    chp->ch_channel,
    606 					    drive,
    607 					    via_udma100_tim[drvp->UDMA_mode]);
    608 				} else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
    609 					/* 596b or 686a */
    610 					udmatim_reg |= APO_UDMA_CLK66(
    611 					    chp->ch_channel);
    612 					udmatim_reg |= APO_UDMA_TIME(
    613 					    chp->ch_channel,
    614 					    drive,
    615 					    via_udma66_tim[drvp->UDMA_mode]);
    616 				} else {
    617 					/* 596a or 586b */
    618 					udmatim_reg |= APO_UDMA_TIME(
    619 					    chp->ch_channel,
    620 					    drive,
    621 					    via_udma33_tim[drvp->UDMA_mode]);
    622 				}
    623 				break;
    624 			case PCI_VENDOR_AMD:
    625 			case PCI_VENDOR_NVIDIA:
    626 				udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
    627 				    drive, amd7x6_udma_tim[drvp->UDMA_mode]);
    628 				 break;
    629 			}
    630 			/* can use PIO timings, MW DMA unused */
    631 			mode = drvp->PIO_mode;
    632 		} else {
    633 			/* use Multiword DMA, but only if revision is OK */
    634 			s = splbio();
    635 			drvp->drive_flags &= ~DRIVE_UDMA;
    636 			splx(s);
    637 #ifndef PCIIDE_AMD756_ENABLEDMA
    638 			/*
    639 			 * The workaround doesn't seem to be necessary
    640 			 * with all drives, so it can be disabled by
    641 			 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
    642 			 * triggered.
    643 			 */
    644 			if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
    645 			    sc->sc_pp->ide_product ==
    646 			    PCI_PRODUCT_AMD_PBC756_IDE &&
    647 			    AMD756_CHIPREV_DISABLEDMA(rev)) {
    648 				aprint_normal(
    649 				    "%s:%d:%d: multi-word DMA disabled due "
    650 				    "to chip revision\n",
    651 				    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    652 				    chp->ch_channel, drive);
    653 				mode = drvp->PIO_mode;
    654 				s = splbio();
    655 				drvp->drive_flags &= ~DRIVE_DMA;
    656 				splx(s);
    657 				goto pio;
    658 			}
    659 #endif
    660 			/* mode = min(pio, dma+2) */
    661 			if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
    662 				mode = drvp->PIO_mode;
    663 			else
    664 				mode = drvp->DMA_mode + 2;
    665 		}
    666 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    667 
    668 pio:		/* setup PIO mode */
    669 		if (mode <= 2) {
    670 			drvp->DMA_mode = 0;
    671 			drvp->PIO_mode = 0;
    672 			mode = 0;
    673 		} else {
    674 			drvp->PIO_mode = mode;
    675 			drvp->DMA_mode = mode - 2;
    676 		}
    677 		datatim_reg |=
    678 		    APO_DATATIM_PULSE(chp->ch_channel, drive,
    679 			apollo_pio_set[mode]) |
    680 		    APO_DATATIM_RECOV(chp->ch_channel, drive,
    681 			apollo_pio_rec[mode]);
    682 	}
    683 	if (idedma_ctl != 0) {
    684 		/* Add software bits in status register */
    685 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    686 		    idedma_ctl);
    687 	}
    688 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
    689 	pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
    690 	ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
    691 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
    692 	    pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
    693 }
    694 
    695 static int
    696 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa)
    697 {
    698 	bus_size_t satasize;
    699 	int maptype, ret;
    700 
    701 	if (pciide_chipen(sc, pa) == 0)
    702 		return 0;
    703 
    704 	aprint_verbose("%s: bus-master DMA support present",
    705 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    706 	pciide_mapreg_dma(sc, pa);
    707 	aprint_verbose("\n");
    708 
    709 	if (sc->sc_dma_ok) {
    710 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
    711 		sc->sc_wdcdev.irqack = pciide_irqack;
    712 	}
    713 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    714 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    715 	sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    716 
    717 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    718 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    719 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    720 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
    721 
    722 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
    723 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
    724 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
    725 
    726 	wdc_allocate_regs(&sc->sc_wdcdev);
    727 	maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
    728 	    PCI_MAPREG_START + 0x14);
    729 	switch(maptype) {
    730 	case PCI_MAPREG_TYPE_IO:
    731 		ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
    732 		    PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
    733 		    NULL, &satasize);
    734 		break;
    735 	case PCI_MAPREG_MEM_TYPE_32BIT:
    736 		ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
    737 		    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
    738 		    0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
    739 		    NULL, &satasize);
    740 		break;
    741 	default:
    742 		aprint_error("%s: couldn't map sata regs, unsupported"
    743 		    "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    744 		    maptype);
    745 		return 0;
    746 	}
    747 	if (ret != 0) {
    748 		aprint_error("%s: couldn't map sata regs\n",
    749 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    750 		return 0;
    751 	}
    752 	return 1;
    753 }
    754 
    755 static void
    756 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa,
    757     int satareg_shift)
    758 {
    759 	struct pciide_channel *cp;
    760 	struct ata_channel *wdc_cp;
    761 	struct wdc_regs *wdr;
    762 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    763 	int channel;
    764 	bus_size_t cmdsize, ctlsize;
    765 
    766 	if (via_sata_chip_map_common(sc, pa) == 0)
    767 		return;
    768 
    769 	if (interface == 0) {
    770 		ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
    771 		    DEBUG_PROBE);
    772 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    773 		    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    774 	}
    775 
    776 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    777 	     channel++) {
    778 		cp = &sc->pciide_channels[channel];
    779 		if (pciide_chansetup(sc, channel, interface) == 0)
    780 			continue;
    781 		wdc_cp = &cp->ata_channel;
    782 		wdr = CHAN_TO_WDC_REGS(wdc_cp);
    783 		wdr->sata_iot = sc->sc_ba5_st;
    784 		wdr->sata_baseioh = sc->sc_ba5_sh;
    785 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    786 		    (wdc_cp->ch_channel << satareg_shift) + 0x0, 1,
    787 		    &wdr->sata_status) != 0) {
    788 			aprint_error("%s: couldn't map channel %d "
    789 			    "sata_status regs\n",
    790 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    791 			    wdc_cp->ch_channel);
    792 			continue;
    793 		}
    794 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    795 		    (wdc_cp->ch_channel << satareg_shift) + 0x4, 1,
    796 		    &wdr->sata_error) != 0) {
    797 			aprint_error("%s: couldn't map channel %d "
    798 			    "sata_error regs\n",
    799 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    800 			    wdc_cp->ch_channel);
    801 			continue;
    802 		}
    803 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    804 		    (wdc_cp->ch_channel << satareg_shift) + 0x8, 1,
    805 		    &wdr->sata_control) != 0) {
    806 			aprint_error("%s: couldn't map channel %d "
    807 			    "sata_control regs\n",
    808 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    809 			    wdc_cp->ch_channel);
    810 			continue;
    811 		}
    812 		sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
    813 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
    814 		    pciide_pci_intr);
    815 	}
    816 }
    817 
    818 static void
    819 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa)
    820 {
    821 	via_sata_chip_map(sc, pa, 0);
    822 }
    823 
    824 static void
    825 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa)
    826 {
    827 	via_sata_chip_map(sc, pa, 6);
    828 }
    829 
    830 static void
    831 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa)
    832 {
    833 	via_sata_chip_map(sc, pa, 7);
    834 }
    835 
    836 static void
    837 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa)
    838 {
    839 	struct pciide_channel *cp;
    840 	struct ata_channel *wdc_cp;
    841 	struct wdc_regs *wdr;
    842 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    843 	int channel;
    844 	bus_size_t cmdsize;
    845 	pci_intr_handle_t intrhandle;
    846 	const char *intrstr;
    847 	int i;
    848 
    849 	if (via_sata_chip_map_common(sc, pa) == 0)
    850 		return;
    851 
    852 	if (interface == 0) {
    853 		ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
    854 		    DEBUG_PROBE);
    855 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    856 		    PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
    857 	}
    858 
    859 	if (pci_intr_map(pa, &intrhandle) != 0) {
    860 		aprint_error("%s: couldn't map native-PCI interrupt\n",
    861 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    862 		return;
    863 	}
    864 	intrstr = pci_intr_string(pa->pa_pc, intrhandle);
    865 	sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
    866 	    intrhandle, IPL_BIO, pciide_pci_intr, sc);
    867 	if (sc->sc_pci_ih == NULL) {
    868 		aprint_error(
    869 		    "%s: couldn't establish native-PCI interrupt",
    870 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    871 		if (intrstr != NULL)
    872 		    aprint_error(" at %s", intrstr);
    873 		aprint_error("\n");
    874 		return;
    875 	}
    876 	aprint_normal("%s: using %s for native-PCI interrupt\n",
    877 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    878 	    intrstr ? intrstr : "unknown interrupt");
    879 
    880 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    881 	     channel++) {
    882 		cp = &sc->pciide_channels[channel];
    883 		if (pciide_chansetup(sc, channel, interface) == 0)
    884 			continue;
    885 		cp->ata_channel.ch_ndrive = 1;
    886 		wdc_cp = &cp->ata_channel;
    887 		wdr = CHAN_TO_WDC_REGS(wdc_cp);
    888 
    889 		wdr->sata_iot = sc->sc_ba5_st;
    890 		wdr->sata_baseioh = sc->sc_ba5_sh;
    891 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    892 		    (wdc_cp->ch_channel << 6) + 0x0, 1,
    893 		    &wdr->sata_status) != 0) {
    894 			aprint_error("%s: couldn't map channel %d "
    895 			    "sata_status regs\n",
    896 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    897 			    wdc_cp->ch_channel);
    898 			continue;
    899 		}
    900 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    901 		    (wdc_cp->ch_channel << 6) + 0x4, 1,
    902 		    &wdr->sata_error) != 0) {
    903 			aprint_error("%s: couldn't map channel %d "
    904 			    "sata_error regs\n",
    905 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    906 			    wdc_cp->ch_channel);
    907 			continue;
    908 		}
    909 		if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
    910 		    (wdc_cp->ch_channel << 6) + 0x8, 1,
    911 		    &wdr->sata_control) != 0) {
    912 			aprint_error("%s: couldn't map channel %d "
    913 			    "sata_control regs\n",
    914 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    915 			    wdc_cp->ch_channel);
    916 			continue;
    917 		}
    918 		sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
    919 
    920 		if (pci_mapreg_map(pa, (0x10 + (4 * (channel))),
    921 		    PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
    922 		    NULL, &cmdsize) != 0) {
    923 			aprint_error("%s: couldn't map %s channel regs\n",
    924 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    925 			    cp->name);
    926 		}
    927 		wdr->ctl_iot = wdr->cmd_iot;
    928 		for (i = 0; i < WDC_NREG; i++) {
    929 			if (bus_space_subregion(wdr->cmd_iot,
    930 			    wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
    931 			    &wdr->cmd_iohs[i]) != 0) {
    932 				aprint_error("%s: couldn't subregion %s "
    933 				    "channel cmd regs\n",
    934 				    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
    935 				    cp->name);
    936 				return;
    937 			}
    938 		}
    939 		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
    940 		    WDC_NREG + 2, 1,  &wdr->ctl_ioh) != 0) {
    941 			aprint_error("%s: couldn't map channel %d ctl regs\n",
    942 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel);
    943 			return;
    944 		}
    945 		wdc_init_shadow_regs(wdc_cp);
    946 		wdcattach(wdc_cp);
    947 	}
    948 }
    949