viaide.c revision 1.46
1 /* $NetBSD: viaide.c,v 1.46 2007/11/14 12:30:48 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.46 2007/11/14 12:30:48 xtraeme Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static int via_sata_chip_map_common(struct pciide_softc *, 48 struct pci_attach_args *); 49 static void via_sata_chip_map(struct pciide_softc *, 50 struct pci_attach_args *, int); 51 static void via_sata_chip_map_0(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map_6(struct pciide_softc *, 54 struct pci_attach_args *); 55 static void via_sata_chip_map_7(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_new(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_setup_channel(struct ata_channel *); 60 61 static int viaide_match(struct device *, struct cfdata *, void *); 62 static void viaide_attach(struct device *, struct device *, void *); 63 static const struct pciide_product_desc * 64 viaide_lookup(pcireg_t); 65 66 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 67 viaide_match, viaide_attach, NULL, NULL); 68 69 static const struct pciide_product_desc pciide_amd_products[] = { 70 { PCI_PRODUCT_AMD_PBC756_IDE, 71 0, 72 "Advanced Micro Devices AMD756 IDE Controller", 73 via_chip_map 74 }, 75 { PCI_PRODUCT_AMD_PBC766_IDE, 76 0, 77 "Advanced Micro Devices AMD766 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC768_IDE, 81 0, 82 "Advanced Micro Devices AMD768 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC8111_IDE, 86 0, 87 "Advanced Micro Devices AMD8111 IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_AMD_CS5536_IDE, 91 0, 92 "Advanced Micro Devices CS5536 IDE Controller", 93 via_chip_map 94 }, 95 { 0, 96 0, 97 NULL, 98 NULL 99 } 100 }; 101 102 static const struct pciide_product_desc pciide_nvidia_products[] = { 103 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 104 0, 105 "NVIDIA nForce IDE Controller", 106 via_chip_map 107 }, 108 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 109 0, 110 "NVIDIA nForce2 IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 114 0, 115 "NVIDIA nForce2 Ultra 400 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 119 0, 120 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 121 via_sata_chip_map_6 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 124 0, 125 "NVIDIA nForce3 IDE Controller", 126 via_chip_map 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 129 0, 130 "NVIDIA nForce3 250 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 134 0, 135 "NVIDIA nForce3 250 Serial ATA Controller", 136 via_sata_chip_map_6 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 139 0, 140 "NVIDIA nForce3 250 Serial ATA Controller", 141 via_sata_chip_map_6 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 144 0, 145 "NVIDIA nForce4 IDE Controller", 146 via_chip_map 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 149 0, 150 "NVIDIA nForce4 Serial ATA Controller", 151 via_sata_chip_map_6 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 154 0, 155 "NVIDIA nForce4 Serial ATA Controller", 156 via_sata_chip_map_6 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 159 0, 160 "NVIDIA nForce430 IDE Controller", 161 via_chip_map 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 164 0, 165 "NVIDIA nForce430 Serial ATA Controller", 166 via_sata_chip_map_6 167 }, 168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 169 0, 170 "NVIDIA nForce430 Serial ATA Controller", 171 via_sata_chip_map_6 172 }, 173 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 174 0, 175 "NVIDIA MCP04 IDE Controller", 176 via_chip_map 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 179 0, 180 "NVIDIA MCP04 Serial ATA Controller", 181 via_sata_chip_map_6 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 184 0, 185 "NVIDIA MCP04 Serial ATA Controller", 186 via_sata_chip_map_6 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 189 0, 190 "NVIDIA MCP55 IDE Controller", 191 via_chip_map 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 194 0, 195 "NVIDIA MCP55 Serial ATA Controller", 196 via_sata_chip_map_6 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 199 0, 200 "NVIDIA MCP55 Serial ATA Controller", 201 via_sata_chip_map_6 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 204 0, 205 "NVIDIA MCP61 IDE Controller", 206 via_chip_map 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 209 0, 210 "NVIDIA MCP65 IDE Controller", 211 via_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 214 0, 215 "NVIDIA MCP73 IDE Controller", 216 via_chip_map 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 219 0, 220 "NVIDIA MCP77 IDE Controller", 221 via_chip_map 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 224 0, 225 "NVIDIA MCP61 Serial ATA Controller", 226 via_sata_chip_map_6 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 229 0, 230 "NVIDIA MCP61 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 234 0, 235 "NVIDIA MCP61 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 239 0, 240 "NVIDIA MCP65 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 244 0, 245 "NVIDIA MCP65 Serial ATA Controller", 246 via_sata_chip_map_6 247 }, 248 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 249 0, 250 "NVIDIA MCP65 Serial ATA Controller", 251 via_sata_chip_map_6 252 }, 253 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 254 0, 255 "NVIDIA MCP65 Serial ATA Controller", 256 via_sata_chip_map_6 257 }, 258 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 259 0, 260 "NVIDIA MCP67 IDE Controller", 261 via_chip_map, 262 }, 263 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 264 0, 265 "NVIDIA MCP67 Serial ATA Controller", 266 via_sata_chip_map_6, 267 }, 268 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 269 0, 270 "NVIDIA MCP67 Serial ATA Controller", 271 via_sata_chip_map_6, 272 }, 273 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 274 0, 275 "NVIDIA MCP67 Serial ATA Controller", 276 via_sata_chip_map_6, 277 }, 278 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 279 0, 280 "NVIDIA MCP67 Serial ATA Controller", 281 via_sata_chip_map_6, 282 }, 283 { 0, 284 0, 285 NULL, 286 NULL 287 } 288 }; 289 290 static const struct pciide_product_desc pciide_via_products[] = { 291 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 292 0, 293 NULL, 294 via_chip_map, 295 }, 296 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 297 0, 298 NULL, 299 via_chip_map, 300 }, 301 { PCI_PRODUCT_VIATECH_CX700_IDE, 302 0, 303 NULL, 304 via_chip_map, 305 }, 306 { PCI_PRODUCT_VIATECH_VT6421_RAID, 307 0, 308 "VIA Technologies VT6421 Serial RAID Controller", 309 via_sata_chip_map_new, 310 }, 311 { PCI_PRODUCT_VIATECH_VT8237_SATA, 312 0, 313 "VIA Technologies VT8237 SATA Controller", 314 via_sata_chip_map_7, 315 }, 316 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 317 0, 318 "VIA Technologies VT8237A SATA Controller", 319 via_sata_chip_map_7, 320 }, 321 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 322 0, 323 "VIA Technologies VT8237R SATA Controller", 324 via_sata_chip_map_0, 325 }, 326 { 0, 327 0, 328 NULL, 329 NULL 330 } 331 }; 332 333 static const struct pciide_product_desc * 334 viaide_lookup(pcireg_t id) 335 { 336 337 switch (PCI_VENDOR(id)) { 338 case PCI_VENDOR_VIATECH: 339 return (pciide_lookup_product(id, pciide_via_products)); 340 341 case PCI_VENDOR_AMD: 342 return (pciide_lookup_product(id, pciide_amd_products)); 343 344 case PCI_VENDOR_NVIDIA: 345 return (pciide_lookup_product(id, pciide_nvidia_products)); 346 } 347 return (NULL); 348 } 349 350 static int 351 viaide_match(struct device *parent, struct cfdata *match, 352 void *aux) 353 { 354 struct pci_attach_args *pa = aux; 355 356 if (viaide_lookup(pa->pa_id) != NULL) 357 return (2); 358 return (0); 359 } 360 361 static void 362 viaide_attach(struct device *parent, struct device *self, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 struct pciide_softc *sc = (struct pciide_softc *)self; 366 const struct pciide_product_desc *pp; 367 368 pp = viaide_lookup(pa->pa_id); 369 if (pp == NULL) 370 panic("viaide_attach"); 371 pciide_common_attach(sc, pa, pp); 372 } 373 374 static int 375 via_pcib_match(struct pci_attach_args *pa) 376 { 377 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 378 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 379 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 380 return (1); 381 return 0; 382 } 383 384 static void 385 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 386 { 387 struct pciide_channel *cp; 388 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 389 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 390 int channel; 391 u_int32_t ideconf; 392 bus_size_t cmdsize, ctlsize; 393 pcireg_t pcib_id, pcib_class; 394 struct pci_attach_args pcib_pa; 395 396 if (pciide_chipen(sc, pa) == 0) 397 return; 398 399 switch (vendor) { 400 case PCI_VENDOR_VIATECH: 401 /* 402 * get a PCI tag for the ISA bridge. 403 */ 404 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 405 goto unknown; 406 pcib_id = pcib_pa.pa_id; 407 pcib_class = pcib_pa.pa_class; 408 aprint_normal("%s: VIA Technologies ", 409 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 410 switch (PCI_PRODUCT(pcib_id)) { 411 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 412 aprint_normal("VT82C586 (Apollo VP) "); 413 if(PCI_REVISION(pcib_class) >= 0x02) { 414 aprint_normal("ATA33 controller\n"); 415 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 416 } else { 417 aprint_normal("controller\n"); 418 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 419 } 420 break; 421 case PCI_PRODUCT_VIATECH_VT82C596A: 422 aprint_normal("VT82C596A (Apollo Pro) "); 423 if (PCI_REVISION(pcib_class) >= 0x12) { 424 aprint_normal("ATA66 controller\n"); 425 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 426 } else { 427 aprint_normal("ATA33 controller\n"); 428 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 429 } 430 break; 431 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 432 aprint_normal("VT82C686A (Apollo KX133) "); 433 if (PCI_REVISION(pcib_class) >= 0x40) { 434 aprint_normal("ATA100 controller\n"); 435 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 436 } else { 437 aprint_normal("ATA66 controller\n"); 438 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 439 } 440 break; 441 case PCI_PRODUCT_VIATECH_VT8231: 442 aprint_normal("VT8231 ATA100 controller\n"); 443 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 444 break; 445 case PCI_PRODUCT_VIATECH_VT8233: 446 aprint_normal("VT8233 ATA100 controller\n"); 447 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 448 break; 449 case PCI_PRODUCT_VIATECH_VT8233A: 450 aprint_normal("VT8233A ATA133 controller\n"); 451 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 452 break; 453 case PCI_PRODUCT_VIATECH_VT8235: 454 aprint_normal("VT8235 ATA133 controller\n"); 455 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 456 break; 457 case PCI_PRODUCT_VIATECH_VT8237: 458 aprint_normal("VT8237 ATA133 controller\n"); 459 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 460 break; 461 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 462 aprint_normal("VT8237A ATA133 controller\n"); 463 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 464 break; 465 case PCI_PRODUCT_VIATECH_CX700_IDE: 466 aprint_normal("CX700 ATA133 controller\n"); 467 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 468 break; 469 default: 470 unknown: 471 aprint_normal("unknown VIA ATA controller\n"); 472 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 473 } 474 sc->sc_apo_regbase = APO_VIA_REGBASE; 475 break; 476 case PCI_VENDOR_AMD: 477 switch (sc->sc_pp->ide_product) { 478 case PCI_PRODUCT_AMD_PBC8111_IDE: 479 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 480 break; 481 case PCI_PRODUCT_AMD_CS5536_IDE: 482 case PCI_PRODUCT_AMD_PBC766_IDE: 483 case PCI_PRODUCT_AMD_PBC768_IDE: 484 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 485 break; 486 default: 487 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 488 } 489 sc->sc_apo_regbase = APO_AMD_REGBASE; 490 break; 491 case PCI_VENDOR_NVIDIA: 492 switch (sc->sc_pp->ide_product) { 493 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 495 break; 496 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 497 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 498 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 499 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 500 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 501 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 502 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 503 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 504 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 505 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 506 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 507 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 508 break; 509 } 510 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 511 break; 512 default: 513 panic("via_chip_map: unknown vendor"); 514 } 515 516 aprint_verbose("%s: bus-master DMA support present", 517 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 518 pciide_mapreg_dma(sc, pa); 519 aprint_verbose("\n"); 520 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 521 if (sc->sc_dma_ok) { 522 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 523 sc->sc_wdcdev.irqack = pciide_irqack; 524 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 525 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 526 } 527 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 528 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 529 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 530 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 531 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 532 533 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 534 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 535 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 536 537 wdc_allocate_regs(&sc->sc_wdcdev); 538 539 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 540 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 541 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 542 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 543 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 544 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 545 DEBUG_PROBE); 546 547 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 548 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 549 channel++) { 550 cp = &sc->pciide_channels[channel]; 551 if (pciide_chansetup(sc, channel, interface) == 0) 552 continue; 553 554 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 555 aprint_normal("%s: %s channel ignored (disabled)\n", 556 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 557 cp->ata_channel.ch_flags |= ATACH_DISABLED; 558 continue; 559 } 560 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 561 pciide_pci_intr); 562 } 563 } 564 565 static void 566 via_setup_channel(struct ata_channel *chp) 567 { 568 u_int32_t udmatim_reg, datatim_reg; 569 u_int8_t idedma_ctl; 570 int mode, drive, s; 571 struct ata_drive_datas *drvp; 572 struct atac_softc *atac = chp->ch_atac; 573 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 574 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 575 #ifndef PCIIDE_AMD756_ENABLEDMA 576 int rev = PCI_REVISION( 577 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 578 #endif 579 580 idedma_ctl = 0; 581 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 582 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 583 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 584 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 585 586 /* setup DMA if needed */ 587 pciide_channel_dma_setup(cp); 588 589 for (drive = 0; drive < 2; drive++) { 590 drvp = &chp->ch_drive[drive]; 591 /* If no drive, skip */ 592 if ((drvp->drive_flags & DRIVE) == 0) 593 continue; 594 /* add timing values, setup DMA if needed */ 595 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 596 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 597 mode = drvp->PIO_mode; 598 goto pio; 599 } 600 if ((atac->atac_cap & ATAC_CAP_UDMA) && 601 (drvp->drive_flags & DRIVE_UDMA)) { 602 /* use Ultra/DMA */ 603 s = splbio(); 604 drvp->drive_flags &= ~DRIVE_DMA; 605 splx(s); 606 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 607 APO_UDMA_EN_MTH(chp->ch_channel, drive); 608 switch (PCI_VENDOR(sc->sc_pci_id)) { 609 case PCI_VENDOR_VIATECH: 610 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 611 /* 8233a */ 612 udmatim_reg |= APO_UDMA_TIME( 613 chp->ch_channel, 614 drive, 615 via_udma133_tim[drvp->UDMA_mode]); 616 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 617 /* 686b */ 618 udmatim_reg |= APO_UDMA_TIME( 619 chp->ch_channel, 620 drive, 621 via_udma100_tim[drvp->UDMA_mode]); 622 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 623 /* 596b or 686a */ 624 udmatim_reg |= APO_UDMA_CLK66( 625 chp->ch_channel); 626 udmatim_reg |= APO_UDMA_TIME( 627 chp->ch_channel, 628 drive, 629 via_udma66_tim[drvp->UDMA_mode]); 630 } else { 631 /* 596a or 586b */ 632 udmatim_reg |= APO_UDMA_TIME( 633 chp->ch_channel, 634 drive, 635 via_udma33_tim[drvp->UDMA_mode]); 636 } 637 break; 638 case PCI_VENDOR_AMD: 639 case PCI_VENDOR_NVIDIA: 640 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 641 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 642 break; 643 } 644 /* can use PIO timings, MW DMA unused */ 645 mode = drvp->PIO_mode; 646 } else { 647 /* use Multiword DMA, but only if revision is OK */ 648 s = splbio(); 649 drvp->drive_flags &= ~DRIVE_UDMA; 650 splx(s); 651 #ifndef PCIIDE_AMD756_ENABLEDMA 652 /* 653 * The workaround doesn't seem to be necessary 654 * with all drives, so it can be disabled by 655 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 656 * triggered. 657 */ 658 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 659 sc->sc_pp->ide_product == 660 PCI_PRODUCT_AMD_PBC756_IDE && 661 AMD756_CHIPREV_DISABLEDMA(rev)) { 662 aprint_normal( 663 "%s:%d:%d: multi-word DMA disabled due " 664 "to chip revision\n", 665 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 666 chp->ch_channel, drive); 667 mode = drvp->PIO_mode; 668 s = splbio(); 669 drvp->drive_flags &= ~DRIVE_DMA; 670 splx(s); 671 goto pio; 672 } 673 #endif 674 /* mode = min(pio, dma+2) */ 675 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 676 mode = drvp->PIO_mode; 677 else 678 mode = drvp->DMA_mode + 2; 679 } 680 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 681 682 pio: /* setup PIO mode */ 683 if (mode <= 2) { 684 drvp->DMA_mode = 0; 685 drvp->PIO_mode = 0; 686 mode = 0; 687 } else { 688 drvp->PIO_mode = mode; 689 drvp->DMA_mode = mode - 2; 690 } 691 datatim_reg |= 692 APO_DATATIM_PULSE(chp->ch_channel, drive, 693 apollo_pio_set[mode]) | 694 APO_DATATIM_RECOV(chp->ch_channel, drive, 695 apollo_pio_rec[mode]); 696 } 697 if (idedma_ctl != 0) { 698 /* Add software bits in status register */ 699 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 700 idedma_ctl); 701 } 702 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 703 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 704 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 705 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 706 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 707 } 708 709 static int 710 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 711 { 712 bus_size_t satasize; 713 int maptype, ret; 714 715 if (pciide_chipen(sc, pa) == 0) 716 return 0; 717 718 aprint_verbose("%s: bus-master DMA support present", 719 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 720 pciide_mapreg_dma(sc, pa); 721 aprint_verbose("\n"); 722 723 if (sc->sc_dma_ok) { 724 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 725 sc->sc_wdcdev.irqack = pciide_irqack; 726 } 727 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 728 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 729 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 730 731 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 732 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 733 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 734 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 735 736 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 737 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 738 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 739 740 wdc_allocate_regs(&sc->sc_wdcdev); 741 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 742 PCI_MAPREG_START + 0x14); 743 switch(maptype) { 744 case PCI_MAPREG_TYPE_IO: 745 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 746 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 747 NULL, &satasize); 748 break; 749 case PCI_MAPREG_MEM_TYPE_32BIT: 750 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 751 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 752 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 753 NULL, &satasize); 754 break; 755 default: 756 aprint_error("%s: couldn't map sata regs, unsupported" 757 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 758 maptype); 759 return 0; 760 } 761 if (ret != 0) { 762 aprint_error("%s: couldn't map sata regs\n", 763 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 764 return 0; 765 } 766 return 1; 767 } 768 769 static void 770 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 771 int satareg_shift) 772 { 773 struct pciide_channel *cp; 774 struct ata_channel *wdc_cp; 775 struct wdc_regs *wdr; 776 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 777 int channel; 778 bus_size_t cmdsize, ctlsize; 779 780 if (via_sata_chip_map_common(sc, pa) == 0) 781 return; 782 783 if (interface == 0) { 784 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 785 DEBUG_PROBE); 786 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 787 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 788 } 789 790 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 791 channel++) { 792 cp = &sc->pciide_channels[channel]; 793 if (pciide_chansetup(sc, channel, interface) == 0) 794 continue; 795 wdc_cp = &cp->ata_channel; 796 wdr = CHAN_TO_WDC_REGS(wdc_cp); 797 wdr->sata_iot = sc->sc_ba5_st; 798 wdr->sata_baseioh = sc->sc_ba5_sh; 799 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 800 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 801 &wdr->sata_status) != 0) { 802 aprint_error("%s: couldn't map channel %d " 803 "sata_status regs\n", 804 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 805 wdc_cp->ch_channel); 806 continue; 807 } 808 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 809 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 810 &wdr->sata_error) != 0) { 811 aprint_error("%s: couldn't map channel %d " 812 "sata_error regs\n", 813 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 814 wdc_cp->ch_channel); 815 continue; 816 } 817 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 818 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 819 &wdr->sata_control) != 0) { 820 aprint_error("%s: couldn't map channel %d " 821 "sata_control regs\n", 822 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 823 wdc_cp->ch_channel); 824 continue; 825 } 826 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 827 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 828 pciide_pci_intr); 829 } 830 } 831 832 static void 833 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 834 { 835 via_sata_chip_map(sc, pa, 0); 836 } 837 838 static void 839 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 840 { 841 via_sata_chip_map(sc, pa, 6); 842 } 843 844 static void 845 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 846 { 847 via_sata_chip_map(sc, pa, 7); 848 } 849 850 static void 851 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 852 { 853 struct pciide_channel *cp; 854 struct ata_channel *wdc_cp; 855 struct wdc_regs *wdr; 856 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 857 int channel; 858 bus_size_t cmdsize; 859 pci_intr_handle_t intrhandle; 860 const char *intrstr; 861 int i; 862 863 if (via_sata_chip_map_common(sc, pa) == 0) 864 return; 865 866 if (interface == 0) { 867 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 868 DEBUG_PROBE); 869 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 870 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 871 } 872 873 if (pci_intr_map(pa, &intrhandle) != 0) { 874 aprint_error("%s: couldn't map native-PCI interrupt\n", 875 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 876 return; 877 } 878 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 879 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 880 intrhandle, IPL_BIO, pciide_pci_intr, sc); 881 if (sc->sc_pci_ih == NULL) { 882 aprint_error( 883 "%s: couldn't establish native-PCI interrupt", 884 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 885 if (intrstr != NULL) 886 aprint_error(" at %s", intrstr); 887 aprint_error("\n"); 888 return; 889 } 890 aprint_normal("%s: using %s for native-PCI interrupt\n", 891 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 892 intrstr ? intrstr : "unknown interrupt"); 893 894 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 895 channel++) { 896 cp = &sc->pciide_channels[channel]; 897 if (pciide_chansetup(sc, channel, interface) == 0) 898 continue; 899 cp->ata_channel.ch_ndrive = 1; 900 wdc_cp = &cp->ata_channel; 901 wdr = CHAN_TO_WDC_REGS(wdc_cp); 902 903 wdr->sata_iot = sc->sc_ba5_st; 904 wdr->sata_baseioh = sc->sc_ba5_sh; 905 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 906 (wdc_cp->ch_channel << 6) + 0x0, 1, 907 &wdr->sata_status) != 0) { 908 aprint_error("%s: couldn't map channel %d " 909 "sata_status regs\n", 910 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 911 wdc_cp->ch_channel); 912 continue; 913 } 914 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 915 (wdc_cp->ch_channel << 6) + 0x4, 1, 916 &wdr->sata_error) != 0) { 917 aprint_error("%s: couldn't map channel %d " 918 "sata_error regs\n", 919 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 920 wdc_cp->ch_channel); 921 continue; 922 } 923 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 924 (wdc_cp->ch_channel << 6) + 0x8, 1, 925 &wdr->sata_control) != 0) { 926 aprint_error("%s: couldn't map channel %d " 927 "sata_control regs\n", 928 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 929 wdc_cp->ch_channel); 930 continue; 931 } 932 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 933 934 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 935 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 936 NULL, &cmdsize) != 0) { 937 aprint_error("%s: couldn't map %s channel regs\n", 938 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 939 cp->name); 940 } 941 wdr->ctl_iot = wdr->cmd_iot; 942 for (i = 0; i < WDC_NREG; i++) { 943 if (bus_space_subregion(wdr->cmd_iot, 944 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 945 &wdr->cmd_iohs[i]) != 0) { 946 aprint_error("%s: couldn't subregion %s " 947 "channel cmd regs\n", 948 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 949 cp->name); 950 return; 951 } 952 } 953 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 954 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 955 aprint_error("%s: couldn't map channel %d ctl regs\n", 956 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 957 return; 958 } 959 wdc_init_shadow_regs(wdc_cp); 960 wdcattach(wdc_cp); 961 } 962 } 963
Indexes created Mon Oct 20 08:09:54 GMT 2025