viaide.c revision 1.47.6.1
1 /* $NetBSD: viaide.c,v 1.47.6.1 2008/01/02 21:54:59 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.47.6.1 2008/01/02 21:54:59 bouyer Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 48 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *)); 49 static void vt8231_mapregs_native(struct pci_attach_args *, 50 struct pciide_channel *, bus_size_t *, bus_size_t *, 51 int (*)(void *)); 52 static int via_sata_chip_map_common(struct pciide_softc *, 53 struct pci_attach_args *); 54 static void via_sata_chip_map(struct pciide_softc *, 55 struct pci_attach_args *, int); 56 static void via_sata_chip_map_0(struct pciide_softc *, 57 struct pci_attach_args *); 58 static void via_sata_chip_map_6(struct pciide_softc *, 59 struct pci_attach_args *); 60 static void via_sata_chip_map_7(struct pciide_softc *, 61 struct pci_attach_args *); 62 static void via_sata_chip_map_new(struct pciide_softc *, 63 struct pci_attach_args *); 64 static void via_setup_channel(struct ata_channel *); 65 66 static int viaide_match(struct device *, struct cfdata *, void *); 67 static void viaide_attach(struct device *, struct device *, void *); 68 static const struct pciide_product_desc * 69 viaide_lookup(pcireg_t); 70 71 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 72 viaide_match, viaide_attach, NULL, NULL); 73 74 static const struct pciide_product_desc pciide_amd_products[] = { 75 { PCI_PRODUCT_AMD_PBC756_IDE, 76 0, 77 "Advanced Micro Devices AMD756 IDE Controller", 78 via_chip_map 79 }, 80 { PCI_PRODUCT_AMD_PBC766_IDE, 81 0, 82 "Advanced Micro Devices AMD766 IDE Controller", 83 via_chip_map 84 }, 85 { PCI_PRODUCT_AMD_PBC768_IDE, 86 0, 87 "Advanced Micro Devices AMD768 IDE Controller", 88 via_chip_map 89 }, 90 { PCI_PRODUCT_AMD_PBC8111_IDE, 91 0, 92 "Advanced Micro Devices AMD8111 IDE Controller", 93 via_chip_map 94 }, 95 { PCI_PRODUCT_AMD_CS5536_IDE, 96 0, 97 "Advanced Micro Devices CS5536 IDE Controller", 98 via_chip_map 99 }, 100 { 0, 101 0, 102 NULL, 103 NULL 104 } 105 }; 106 107 static const struct pciide_product_desc pciide_nvidia_products[] = { 108 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 109 0, 110 "NVIDIA nForce IDE Controller", 111 via_chip_map 112 }, 113 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 114 0, 115 "NVIDIA nForce2 IDE Controller", 116 via_chip_map 117 }, 118 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 119 0, 120 "NVIDIA nForce2 Ultra 400 IDE Controller", 121 via_chip_map 122 }, 123 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 124 0, 125 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 126 via_sata_chip_map_6 127 }, 128 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 129 0, 130 "NVIDIA nForce3 IDE Controller", 131 via_chip_map 132 }, 133 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 134 0, 135 "NVIDIA nForce3 250 IDE Controller", 136 via_chip_map 137 }, 138 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 139 0, 140 "NVIDIA nForce3 250 Serial ATA Controller", 141 via_sata_chip_map_6 142 }, 143 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 144 0, 145 "NVIDIA nForce3 250 Serial ATA Controller", 146 via_sata_chip_map_6 147 }, 148 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 149 0, 150 "NVIDIA nForce4 IDE Controller", 151 via_chip_map 152 }, 153 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 154 0, 155 "NVIDIA nForce4 Serial ATA Controller", 156 via_sata_chip_map_6 157 }, 158 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 159 0, 160 "NVIDIA nForce4 Serial ATA Controller", 161 via_sata_chip_map_6 162 }, 163 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 164 0, 165 "NVIDIA nForce430 IDE Controller", 166 via_chip_map 167 }, 168 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 169 0, 170 "NVIDIA nForce430 Serial ATA Controller", 171 via_sata_chip_map_6 172 }, 173 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 174 0, 175 "NVIDIA nForce430 Serial ATA Controller", 176 via_sata_chip_map_6 177 }, 178 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 179 0, 180 "NVIDIA MCP04 IDE Controller", 181 via_chip_map 182 }, 183 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 184 0, 185 "NVIDIA MCP04 Serial ATA Controller", 186 via_sata_chip_map_6 187 }, 188 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 189 0, 190 "NVIDIA MCP04 Serial ATA Controller", 191 via_sata_chip_map_6 192 }, 193 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 194 0, 195 "NVIDIA MCP55 IDE Controller", 196 via_chip_map 197 }, 198 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 199 0, 200 "NVIDIA MCP55 Serial ATA Controller", 201 via_sata_chip_map_6 202 }, 203 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 204 0, 205 "NVIDIA MCP55 Serial ATA Controller", 206 via_sata_chip_map_6 207 }, 208 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 209 0, 210 "NVIDIA MCP61 IDE Controller", 211 via_chip_map 212 }, 213 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 214 0, 215 "NVIDIA MCP65 IDE Controller", 216 via_chip_map 217 }, 218 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 219 0, 220 "NVIDIA MCP73 IDE Controller", 221 via_chip_map 222 }, 223 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 224 0, 225 "NVIDIA MCP77 IDE Controller", 226 via_chip_map 227 }, 228 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 229 0, 230 "NVIDIA MCP61 Serial ATA Controller", 231 via_sata_chip_map_6 232 }, 233 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 234 0, 235 "NVIDIA MCP61 Serial ATA Controller", 236 via_sata_chip_map_6 237 }, 238 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 239 0, 240 "NVIDIA MCP61 Serial ATA Controller", 241 via_sata_chip_map_6 242 }, 243 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 244 0, 245 "NVIDIA MCP65 Serial ATA Controller", 246 via_sata_chip_map_6 247 }, 248 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 249 0, 250 "NVIDIA MCP65 Serial ATA Controller", 251 via_sata_chip_map_6 252 }, 253 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 254 0, 255 "NVIDIA MCP65 Serial ATA Controller", 256 via_sata_chip_map_6 257 }, 258 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 259 0, 260 "NVIDIA MCP65 Serial ATA Controller", 261 via_sata_chip_map_6 262 }, 263 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 264 0, 265 "NVIDIA MCP67 IDE Controller", 266 via_chip_map, 267 }, 268 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 269 0, 270 "NVIDIA MCP67 Serial ATA Controller", 271 via_sata_chip_map_6, 272 }, 273 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 274 0, 275 "NVIDIA MCP67 Serial ATA Controller", 276 via_sata_chip_map_6, 277 }, 278 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 279 0, 280 "NVIDIA MCP67 Serial ATA Controller", 281 via_sata_chip_map_6, 282 }, 283 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 284 0, 285 "NVIDIA MCP67 Serial ATA Controller", 286 via_sata_chip_map_6, 287 }, 288 { 0, 289 0, 290 NULL, 291 NULL 292 } 293 }; 294 295 static const struct pciide_product_desc pciide_via_products[] = { 296 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 297 0, 298 NULL, 299 via_chip_map, 300 }, 301 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 302 0, 303 NULL, 304 via_chip_map, 305 }, 306 { PCI_PRODUCT_VIATECH_CX700_IDE, 307 0, 308 NULL, 309 via_chip_map, 310 }, 311 { PCI_PRODUCT_VIATECH_VT6421_RAID, 312 0, 313 "VIA Technologies VT6421 Serial RAID Controller", 314 via_sata_chip_map_new, 315 }, 316 { PCI_PRODUCT_VIATECH_VT8237_SATA, 317 0, 318 "VIA Technologies VT8237 SATA Controller", 319 via_sata_chip_map_7, 320 }, 321 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 322 0, 323 "VIA Technologies VT8237A SATA Controller", 324 via_sata_chip_map_7, 325 }, 326 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 327 0, 328 "VIA Technologies VT8237R SATA Controller", 329 via_sata_chip_map_0, 330 }, 331 { 0, 332 0, 333 NULL, 334 NULL 335 } 336 }; 337 338 static const struct pciide_product_desc * 339 viaide_lookup(pcireg_t id) 340 { 341 342 switch (PCI_VENDOR(id)) { 343 case PCI_VENDOR_VIATECH: 344 return (pciide_lookup_product(id, pciide_via_products)); 345 346 case PCI_VENDOR_AMD: 347 return (pciide_lookup_product(id, pciide_amd_products)); 348 349 case PCI_VENDOR_NVIDIA: 350 return (pciide_lookup_product(id, pciide_nvidia_products)); 351 } 352 return (NULL); 353 } 354 355 static int 356 viaide_match(struct device *parent, struct cfdata *match, 357 void *aux) 358 { 359 struct pci_attach_args *pa = aux; 360 361 if (viaide_lookup(pa->pa_id) != NULL) 362 return (2); 363 return (0); 364 } 365 366 static void 367 viaide_attach(struct device *parent, struct device *self, void *aux) 368 { 369 struct pci_attach_args *pa = aux; 370 struct pciide_softc *sc = (struct pciide_softc *)self; 371 const struct pciide_product_desc *pp; 372 373 pp = viaide_lookup(pa->pa_id); 374 if (pp == NULL) 375 panic("viaide_attach"); 376 pciide_common_attach(sc, pa, pp); 377 } 378 379 static int 380 via_pcib_match(struct pci_attach_args *pa) 381 { 382 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 383 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 384 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 385 return (1); 386 return 0; 387 } 388 389 static void 390 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 391 { 392 struct pciide_channel *cp; 393 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 394 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 395 int channel; 396 u_int32_t ideconf; 397 bus_size_t cmdsize, ctlsize; 398 pcireg_t pcib_id, pcib_class; 399 struct pci_attach_args pcib_pa; 400 401 if (pciide_chipen(sc, pa) == 0) 402 return; 403 404 switch (vendor) { 405 case PCI_VENDOR_VIATECH: 406 /* 407 * get a PCI tag for the ISA bridge. 408 */ 409 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 410 goto unknown; 411 pcib_id = pcib_pa.pa_id; 412 pcib_class = pcib_pa.pa_class; 413 aprint_normal("%s: VIA Technologies ", 414 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 415 switch (PCI_PRODUCT(pcib_id)) { 416 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 417 aprint_normal("VT82C586 (Apollo VP) "); 418 if(PCI_REVISION(pcib_class) >= 0x02) { 419 aprint_normal("ATA33 controller\n"); 420 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 421 } else { 422 aprint_normal("controller\n"); 423 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 424 } 425 break; 426 case PCI_PRODUCT_VIATECH_VT82C596A: 427 aprint_normal("VT82C596A (Apollo Pro) "); 428 if (PCI_REVISION(pcib_class) >= 0x12) { 429 aprint_normal("ATA66 controller\n"); 430 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 431 } else { 432 aprint_normal("ATA33 controller\n"); 433 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 434 } 435 break; 436 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 437 aprint_normal("VT82C686A (Apollo KX133) "); 438 if (PCI_REVISION(pcib_class) >= 0x40) { 439 aprint_normal("ATA100 controller\n"); 440 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 441 } else { 442 aprint_normal("ATA66 controller\n"); 443 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 444 } 445 break; 446 case PCI_PRODUCT_VIATECH_VT8231: 447 aprint_normal("VT8231 ATA100 controller\n"); 448 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 449 break; 450 case PCI_PRODUCT_VIATECH_VT8233: 451 aprint_normal("VT8233 ATA100 controller\n"); 452 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 453 break; 454 case PCI_PRODUCT_VIATECH_VT8233A: 455 aprint_normal("VT8233A ATA133 controller\n"); 456 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 457 break; 458 case PCI_PRODUCT_VIATECH_VT8235: 459 aprint_normal("VT8235 ATA133 controller\n"); 460 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 461 break; 462 case PCI_PRODUCT_VIATECH_VT8237: 463 aprint_normal("VT8237 ATA133 controller\n"); 464 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 465 break; 466 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 467 aprint_normal("VT8237A ATA133 controller\n"); 468 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 469 break; 470 case PCI_PRODUCT_VIATECH_CX700_IDE: 471 aprint_normal("CX700 ATA133 controller\n"); 472 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 473 break; 474 default: 475 unknown: 476 aprint_normal("unknown VIA ATA controller\n"); 477 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 478 } 479 sc->sc_apo_regbase = APO_VIA_REGBASE; 480 break; 481 case PCI_VENDOR_AMD: 482 switch (sc->sc_pp->ide_product) { 483 case PCI_PRODUCT_AMD_PBC8111_IDE: 484 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 485 break; 486 case PCI_PRODUCT_AMD_CS5536_IDE: 487 case PCI_PRODUCT_AMD_PBC766_IDE: 488 case PCI_PRODUCT_AMD_PBC768_IDE: 489 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 490 break; 491 default: 492 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 493 } 494 sc->sc_apo_regbase = APO_AMD_REGBASE; 495 break; 496 case PCI_VENDOR_NVIDIA: 497 switch (sc->sc_pp->ide_product) { 498 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 499 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 500 break; 501 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 502 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 503 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 504 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 505 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 506 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 507 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 508 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 509 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 510 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 511 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 512 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 513 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 514 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 515 break; 516 } 517 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 518 break; 519 default: 520 panic("via_chip_map: unknown vendor"); 521 } 522 523 aprint_verbose("%s: bus-master DMA support present", 524 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 525 pciide_mapreg_dma(sc, pa); 526 aprint_verbose("\n"); 527 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 528 if (sc->sc_dma_ok) { 529 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 530 sc->sc_wdcdev.irqack = pciide_irqack; 531 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 532 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 533 } 534 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 535 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 536 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 537 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 538 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 539 540 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 541 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 542 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 543 544 wdc_allocate_regs(&sc->sc_wdcdev); 545 546 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 547 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 548 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 549 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 550 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 551 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 552 DEBUG_PROBE); 553 554 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 555 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 556 channel++) { 557 cp = &sc->pciide_channels[channel]; 558 if (pciide_chansetup(sc, channel, interface) == 0) 559 continue; 560 561 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 562 aprint_normal("%s: %s channel ignored (disabled)\n", 563 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 564 cp->ata_channel.ch_flags |= ATACH_DISABLED; 565 continue; 566 } 567 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 568 pciide_pci_intr); 569 } 570 } 571 572 static void 573 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 574 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 575 int (*pci_intr)(void *)) 576 { 577 struct ata_channel *wdc_cp; 578 struct pciide_softc *sc; 579 prop_bool_t compat_nat_enable; 580 581 wdc_cp = &cp->ata_channel; 582 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 583 compat_nat_enable = prop_dictionary_get( 584 device_properties((struct device *)sc), "use-compat-native-irq"); 585 586 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 587 /* native mode with irq 14/15 requested? */ 588 if (compat_nat_enable != NULL && 589 prop_bool_true(compat_nat_enable)) 590 vt8231_mapregs_native(pa, cp, cmdsizep, ctlsizep, 591 pci_intr); 592 else 593 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 594 pci_intr); 595 } else { 596 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 597 ctlsizep); 598 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 599 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 600 } 601 wdcattach(wdc_cp); 602 } 603 604 /* 605 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 606 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 607 * programmed to use a single native PCI irq alone. So we install an interrupt 608 * handler for each channel, as in compatibility mode. 609 */ 610 static void 611 vt8231_mapregs_native(struct pci_attach_args *pa, struct pciide_channel *cp, 612 bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *)) 613 { 614 struct ata_channel *wdc_cp; 615 struct pciide_softc *sc; 616 617 wdc_cp = &cp->ata_channel; 618 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 619 620 /* XXX prevent pciide_mapregs_native from installing a handler */ 621 if (sc->sc_pci_ih == NULL) 622 sc->sc_pci_ih = (void *)~0; 623 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL); 624 625 /* interrupts are fixed to 14/15, as in compatibility mode */ 626 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 627 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 628 cp->ih = pciide_machdep_compat_intr_establish( 629 &sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 630 pci_intr, sc); 631 if (cp->ih == NULL) { 632 #endif 633 aprint_error("%s: no compatibility interrupt for " 634 "use by %s channel\n", 635 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 636 wdc_cp->ch_flags |= ATACH_DISABLED; 637 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 638 } 639 sc->sc_pci_ih = cp->ih; /* XXX */ 640 #endif 641 } 642 } 643 644 static void 645 via_setup_channel(struct ata_channel *chp) 646 { 647 u_int32_t udmatim_reg, datatim_reg; 648 u_int8_t idedma_ctl; 649 int mode, drive, s; 650 struct ata_drive_datas *drvp; 651 struct atac_softc *atac = chp->ch_atac; 652 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 653 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 654 #ifndef PCIIDE_AMD756_ENABLEDMA 655 int rev = PCI_REVISION( 656 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 657 #endif 658 659 idedma_ctl = 0; 660 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 661 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 662 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 663 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 664 665 /* setup DMA if needed */ 666 pciide_channel_dma_setup(cp); 667 668 for (drive = 0; drive < 2; drive++) { 669 drvp = &chp->ch_drive[drive]; 670 /* If no drive, skip */ 671 if ((drvp->drive_flags & DRIVE) == 0) 672 continue; 673 /* add timing values, setup DMA if needed */ 674 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 675 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 676 mode = drvp->PIO_mode; 677 goto pio; 678 } 679 if ((atac->atac_cap & ATAC_CAP_UDMA) && 680 (drvp->drive_flags & DRIVE_UDMA)) { 681 /* use Ultra/DMA */ 682 s = splbio(); 683 drvp->drive_flags &= ~DRIVE_DMA; 684 splx(s); 685 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 686 APO_UDMA_EN_MTH(chp->ch_channel, drive); 687 switch (PCI_VENDOR(sc->sc_pci_id)) { 688 case PCI_VENDOR_VIATECH: 689 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 690 /* 8233a */ 691 udmatim_reg |= APO_UDMA_TIME( 692 chp->ch_channel, 693 drive, 694 via_udma133_tim[drvp->UDMA_mode]); 695 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 696 /* 686b */ 697 udmatim_reg |= APO_UDMA_TIME( 698 chp->ch_channel, 699 drive, 700 via_udma100_tim[drvp->UDMA_mode]); 701 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 702 /* 596b or 686a */ 703 udmatim_reg |= APO_UDMA_CLK66( 704 chp->ch_channel); 705 udmatim_reg |= APO_UDMA_TIME( 706 chp->ch_channel, 707 drive, 708 via_udma66_tim[drvp->UDMA_mode]); 709 } else { 710 /* 596a or 586b */ 711 udmatim_reg |= APO_UDMA_TIME( 712 chp->ch_channel, 713 drive, 714 via_udma33_tim[drvp->UDMA_mode]); 715 } 716 break; 717 case PCI_VENDOR_AMD: 718 case PCI_VENDOR_NVIDIA: 719 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 720 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 721 break; 722 } 723 /* can use PIO timings, MW DMA unused */ 724 mode = drvp->PIO_mode; 725 } else { 726 /* use Multiword DMA, but only if revision is OK */ 727 s = splbio(); 728 drvp->drive_flags &= ~DRIVE_UDMA; 729 splx(s); 730 #ifndef PCIIDE_AMD756_ENABLEDMA 731 /* 732 * The workaround doesn't seem to be necessary 733 * with all drives, so it can be disabled by 734 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 735 * triggered. 736 */ 737 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 738 sc->sc_pp->ide_product == 739 PCI_PRODUCT_AMD_PBC756_IDE && 740 AMD756_CHIPREV_DISABLEDMA(rev)) { 741 aprint_normal( 742 "%s:%d:%d: multi-word DMA disabled due " 743 "to chip revision\n", 744 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 745 chp->ch_channel, drive); 746 mode = drvp->PIO_mode; 747 s = splbio(); 748 drvp->drive_flags &= ~DRIVE_DMA; 749 splx(s); 750 goto pio; 751 } 752 #endif 753 /* mode = min(pio, dma+2) */ 754 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 755 mode = drvp->PIO_mode; 756 else 757 mode = drvp->DMA_mode + 2; 758 } 759 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 760 761 pio: /* setup PIO mode */ 762 if (mode <= 2) { 763 drvp->DMA_mode = 0; 764 drvp->PIO_mode = 0; 765 mode = 0; 766 } else { 767 drvp->PIO_mode = mode; 768 drvp->DMA_mode = mode - 2; 769 } 770 datatim_reg |= 771 APO_DATATIM_PULSE(chp->ch_channel, drive, 772 apollo_pio_set[mode]) | 773 APO_DATATIM_RECOV(chp->ch_channel, drive, 774 apollo_pio_rec[mode]); 775 } 776 if (idedma_ctl != 0) { 777 /* Add software bits in status register */ 778 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 779 idedma_ctl); 780 } 781 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 782 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 783 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 784 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 785 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 786 } 787 788 static int 789 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 790 { 791 bus_size_t satasize; 792 int maptype, ret; 793 794 if (pciide_chipen(sc, pa) == 0) 795 return 0; 796 797 aprint_verbose("%s: bus-master DMA support present", 798 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 799 pciide_mapreg_dma(sc, pa); 800 aprint_verbose("\n"); 801 802 if (sc->sc_dma_ok) { 803 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 804 sc->sc_wdcdev.irqack = pciide_irqack; 805 } 806 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 807 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 808 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 809 810 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 811 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 812 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 813 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 814 815 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 816 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 817 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 818 819 wdc_allocate_regs(&sc->sc_wdcdev); 820 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 821 PCI_MAPREG_START + 0x14); 822 switch(maptype) { 823 case PCI_MAPREG_TYPE_IO: 824 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 825 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 826 NULL, &satasize); 827 break; 828 case PCI_MAPREG_MEM_TYPE_32BIT: 829 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 830 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 831 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 832 NULL, &satasize); 833 break; 834 default: 835 aprint_error("%s: couldn't map sata regs, unsupported" 836 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 837 maptype); 838 return 0; 839 } 840 if (ret != 0) { 841 aprint_error("%s: couldn't map sata regs\n", 842 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 843 return 0; 844 } 845 return 1; 846 } 847 848 static void 849 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 850 int satareg_shift) 851 { 852 struct pciide_channel *cp; 853 struct ata_channel *wdc_cp; 854 struct wdc_regs *wdr; 855 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 856 int channel; 857 bus_size_t cmdsize, ctlsize; 858 859 if (via_sata_chip_map_common(sc, pa) == 0) 860 return; 861 862 if (interface == 0) { 863 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 864 DEBUG_PROBE); 865 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 866 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 867 } 868 869 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 870 channel++) { 871 cp = &sc->pciide_channels[channel]; 872 if (pciide_chansetup(sc, channel, interface) == 0) 873 continue; 874 wdc_cp = &cp->ata_channel; 875 wdr = CHAN_TO_WDC_REGS(wdc_cp); 876 wdr->sata_iot = sc->sc_ba5_st; 877 wdr->sata_baseioh = sc->sc_ba5_sh; 878 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 879 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 880 &wdr->sata_status) != 0) { 881 aprint_error("%s: couldn't map channel %d " 882 "sata_status regs\n", 883 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 884 wdc_cp->ch_channel); 885 continue; 886 } 887 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 888 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 889 &wdr->sata_error) != 0) { 890 aprint_error("%s: couldn't map channel %d " 891 "sata_error regs\n", 892 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 893 wdc_cp->ch_channel); 894 continue; 895 } 896 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 897 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 898 &wdr->sata_control) != 0) { 899 aprint_error("%s: couldn't map channel %d " 900 "sata_control regs\n", 901 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 902 wdc_cp->ch_channel); 903 continue; 904 } 905 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 906 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 907 pciide_pci_intr); 908 } 909 } 910 911 static void 912 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 913 { 914 via_sata_chip_map(sc, pa, 0); 915 } 916 917 static void 918 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 919 { 920 via_sata_chip_map(sc, pa, 6); 921 } 922 923 static void 924 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 925 { 926 via_sata_chip_map(sc, pa, 7); 927 } 928 929 static void 930 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 931 { 932 struct pciide_channel *cp; 933 struct ata_channel *wdc_cp; 934 struct wdc_regs *wdr; 935 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 936 int channel; 937 bus_size_t cmdsize; 938 pci_intr_handle_t intrhandle; 939 const char *intrstr; 940 int i; 941 942 if (via_sata_chip_map_common(sc, pa) == 0) 943 return; 944 945 if (interface == 0) { 946 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 947 DEBUG_PROBE); 948 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 949 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 950 } 951 952 if (pci_intr_map(pa, &intrhandle) != 0) { 953 aprint_error("%s: couldn't map native-PCI interrupt\n", 954 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 955 return; 956 } 957 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 958 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 959 intrhandle, IPL_BIO, pciide_pci_intr, sc); 960 if (sc->sc_pci_ih == NULL) { 961 aprint_error( 962 "%s: couldn't establish native-PCI interrupt", 963 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 964 if (intrstr != NULL) 965 aprint_error(" at %s", intrstr); 966 aprint_error("\n"); 967 return; 968 } 969 aprint_normal("%s: using %s for native-PCI interrupt\n", 970 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 971 intrstr ? intrstr : "unknown interrupt"); 972 973 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 974 channel++) { 975 cp = &sc->pciide_channels[channel]; 976 if (pciide_chansetup(sc, channel, interface) == 0) 977 continue; 978 cp->ata_channel.ch_ndrive = 1; 979 wdc_cp = &cp->ata_channel; 980 wdr = CHAN_TO_WDC_REGS(wdc_cp); 981 982 wdr->sata_iot = sc->sc_ba5_st; 983 wdr->sata_baseioh = sc->sc_ba5_sh; 984 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 985 (wdc_cp->ch_channel << 6) + 0x0, 1, 986 &wdr->sata_status) != 0) { 987 aprint_error("%s: couldn't map channel %d " 988 "sata_status regs\n", 989 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 990 wdc_cp->ch_channel); 991 continue; 992 } 993 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 994 (wdc_cp->ch_channel << 6) + 0x4, 1, 995 &wdr->sata_error) != 0) { 996 aprint_error("%s: couldn't map channel %d " 997 "sata_error regs\n", 998 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 999 wdc_cp->ch_channel); 1000 continue; 1001 } 1002 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1003 (wdc_cp->ch_channel << 6) + 0x8, 1, 1004 &wdr->sata_control) != 0) { 1005 aprint_error("%s: couldn't map channel %d " 1006 "sata_control regs\n", 1007 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1008 wdc_cp->ch_channel); 1009 continue; 1010 } 1011 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1012 1013 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 1014 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1015 NULL, &cmdsize) != 0) { 1016 aprint_error("%s: couldn't map %s channel regs\n", 1017 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1018 cp->name); 1019 } 1020 wdr->ctl_iot = wdr->cmd_iot; 1021 for (i = 0; i < WDC_NREG; i++) { 1022 if (bus_space_subregion(wdr->cmd_iot, 1023 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1024 &wdr->cmd_iohs[i]) != 0) { 1025 aprint_error("%s: couldn't subregion %s " 1026 "channel cmd regs\n", 1027 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1028 cp->name); 1029 return; 1030 } 1031 } 1032 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1033 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1034 aprint_error("%s: couldn't map channel %d ctl regs\n", 1035 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 1036 return; 1037 } 1038 wdc_init_shadow_regs(wdc_cp); 1039 wdcattach(wdc_cp); 1040 } 1041 } 1042
Indexes created Fri Oct 17 23:09:53 GMT 2025