viaide.c revision 1.51.6.3
1 /* $NetBSD: viaide.c,v 1.51.6.3 2008/06/29 09:33:09 mjf Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.51.6.3 2008/06/29 09:33:09 mjf Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 48 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *)); 49 static void via_mapregs_compat_native(struct pci_attach_args *, 50 struct pciide_channel *, bus_size_t *, bus_size_t *); 51 static int via_sata_chip_map_common(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map(struct pciide_softc *, 54 struct pci_attach_args *, int); 55 static void via_sata_chip_map_0(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_6(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_sata_chip_map_7(struct pciide_softc *, 60 struct pci_attach_args *); 61 static void via_sata_chip_map_new(struct pciide_softc *, 62 struct pci_attach_args *); 63 static void via_setup_channel(struct ata_channel *); 64 65 static int viaide_match(device_t, cfdata_t, void *); 66 static void viaide_attach(device_t, device_t, void *); 67 static const struct pciide_product_desc * 68 viaide_lookup(pcireg_t); 69 static bool viaide_suspend(device_t PMF_FN_PROTO); 70 static bool viaide_resume(device_t PMF_FN_PROTO); 71 72 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 73 viaide_match, viaide_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_amd_products[] = { 76 { PCI_PRODUCT_AMD_PBC756_IDE, 77 0, 78 "Advanced Micro Devices AMD756 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC766_IDE, 82 0, 83 "Advanced Micro Devices AMD766 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC768_IDE, 87 0, 88 "Advanced Micro Devices AMD768 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_PBC8111_IDE, 92 0, 93 "Advanced Micro Devices AMD8111 IDE Controller", 94 via_chip_map 95 }, 96 { PCI_PRODUCT_AMD_CS5536_IDE, 97 0, 98 "Advanced Micro Devices CS5536 IDE Controller", 99 via_chip_map 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static const struct pciide_product_desc pciide_nvidia_products[] = { 109 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 110 0, 111 "NVIDIA nForce IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 115 0, 116 "NVIDIA nForce2 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 120 0, 121 "NVIDIA nForce2 Ultra 400 IDE Controller", 122 via_chip_map 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 125 0, 126 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 127 via_sata_chip_map_6 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 130 0, 131 "NVIDIA nForce3 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 135 0, 136 "NVIDIA nForce3 250 IDE Controller", 137 via_chip_map 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 145 0, 146 "NVIDIA nForce3 250 Serial ATA Controller", 147 via_sata_chip_map_6 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 150 0, 151 "NVIDIA nForce4 IDE Controller", 152 via_chip_map 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 160 0, 161 "NVIDIA nForce4 Serial ATA Controller", 162 via_sata_chip_map_6 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 165 0, 166 "NVIDIA nForce430 IDE Controller", 167 via_chip_map 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 175 0, 176 "NVIDIA nForce430 Serial ATA Controller", 177 via_sata_chip_map_6 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 180 0, 181 "NVIDIA MCP04 IDE Controller", 182 via_chip_map 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 190 0, 191 "NVIDIA MCP04 Serial ATA Controller", 192 via_sata_chip_map_6 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 195 0, 196 "NVIDIA MCP55 IDE Controller", 197 via_chip_map 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 205 0, 206 "NVIDIA MCP55 Serial ATA Controller", 207 via_sata_chip_map_6 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 210 0, 211 "NVIDIA MCP61 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 215 0, 216 "NVIDIA MCP65 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 220 0, 221 "NVIDIA MCP73 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 225 0, 226 "NVIDIA MCP77 IDE Controller", 227 via_chip_map 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 240 0, 241 "NVIDIA MCP61 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 260 0, 261 "NVIDIA MCP65 Serial ATA Controller", 262 via_sata_chip_map_6 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 265 0, 266 "NVIDIA MCP67 IDE Controller", 267 via_chip_map, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 285 0, 286 "NVIDIA MCP67 Serial ATA Controller", 287 via_sata_chip_map_6, 288 }, 289 { 0, 290 0, 291 NULL, 292 NULL 293 } 294 }; 295 296 static const struct pciide_product_desc pciide_via_products[] = { 297 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 303 0, 304 NULL, 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VT6421_RAID, 313 0, 314 "VIA Technologies VT6421 Serial RAID Controller", 315 via_sata_chip_map_new, 316 }, 317 { PCI_PRODUCT_VIATECH_VT8237_SATA, 318 0, 319 "VIA Technologies VT8237 SATA Controller", 320 via_sata_chip_map_7, 321 }, 322 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 323 0, 324 "VIA Technologies VT8237A SATA Controller", 325 via_sata_chip_map_7, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 328 0, 329 "VIA Technologies VT8237R SATA Controller", 330 via_sata_chip_map_0, 331 }, 332 { 0, 333 0, 334 NULL, 335 NULL 336 } 337 }; 338 339 static const struct pciide_product_desc * 340 viaide_lookup(pcireg_t id) 341 { 342 343 switch (PCI_VENDOR(id)) { 344 case PCI_VENDOR_VIATECH: 345 return (pciide_lookup_product(id, pciide_via_products)); 346 347 case PCI_VENDOR_AMD: 348 return (pciide_lookup_product(id, pciide_amd_products)); 349 350 case PCI_VENDOR_NVIDIA: 351 return (pciide_lookup_product(id, pciide_nvidia_products)); 352 } 353 return (NULL); 354 } 355 356 static int 357 viaide_match(device_t parent, cfdata_t match, void *aux) 358 { 359 struct pci_attach_args *pa = aux; 360 361 if (viaide_lookup(pa->pa_id) != NULL) 362 return (2); 363 return (0); 364 } 365 366 static void 367 viaide_attach(device_t parent, device_t self, void *aux) 368 { 369 struct pci_attach_args *pa = aux; 370 struct pciide_softc *sc = device_private(self); 371 const struct pciide_product_desc *pp; 372 373 sc->sc_wdcdev.sc_atac.atac_dev = self; 374 375 pp = viaide_lookup(pa->pa_id); 376 if (pp == NULL) 377 panic("viaide_attach"); 378 pciide_common_attach(sc, pa, pp); 379 380 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 381 aprint_error_dev(self, "couldn't establish power handler\n"); 382 } 383 384 static int 385 via_pcib_match(struct pci_attach_args *pa) 386 { 387 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 388 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 389 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 390 return (1); 391 return 0; 392 } 393 394 static bool 395 viaide_suspend(device_t dv PMF_FN_ARGS) 396 { 397 struct pciide_softc *sc = device_private(dv); 398 399 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 400 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 401 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 402 /* This two are VIA-only, but should be ignored by other devices. */ 403 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 404 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 405 406 return true; 407 } 408 409 static bool 410 viaide_resume(device_t dv PMF_FN_ARGS) 411 { 412 struct pciide_softc *sc = device_private(dv); 413 414 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 415 sc->sc_pm_reg[0]); 416 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 417 sc->sc_pm_reg[1]); 418 /* This two are VIA-only, but should be ignored by other devices. */ 419 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 420 sc->sc_pm_reg[2]); 421 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 422 sc->sc_pm_reg[3]); 423 424 return true; 425 } 426 427 static void 428 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 429 { 430 struct pciide_channel *cp; 431 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 432 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 433 int channel; 434 u_int32_t ideconf; 435 bus_size_t cmdsize, ctlsize; 436 pcireg_t pcib_id, pcib_class; 437 struct pci_attach_args pcib_pa; 438 439 if (pciide_chipen(sc, pa) == 0) 440 return; 441 442 switch (vendor) { 443 case PCI_VENDOR_VIATECH: 444 /* 445 * get a PCI tag for the ISA bridge. 446 */ 447 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 448 goto unknown; 449 pcib_id = pcib_pa.pa_id; 450 pcib_class = pcib_pa.pa_class; 451 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 452 "VIA Technologies "); 453 switch (PCI_PRODUCT(pcib_id)) { 454 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 455 aprint_normal("VT82C586 (Apollo VP) "); 456 if(PCI_REVISION(pcib_class) >= 0x02) { 457 aprint_normal("ATA33 controller\n"); 458 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 459 } else { 460 aprint_normal("controller\n"); 461 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 462 } 463 break; 464 case PCI_PRODUCT_VIATECH_VT82C596A: 465 aprint_normal("VT82C596A (Apollo Pro) "); 466 if (PCI_REVISION(pcib_class) >= 0x12) { 467 aprint_normal("ATA66 controller\n"); 468 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 469 } else { 470 aprint_normal("ATA33 controller\n"); 471 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 472 } 473 break; 474 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 475 aprint_normal("VT82C686A (Apollo KX133) "); 476 if (PCI_REVISION(pcib_class) >= 0x40) { 477 aprint_normal("ATA100 controller\n"); 478 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 479 } else { 480 aprint_normal("ATA66 controller\n"); 481 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 482 } 483 break; 484 case PCI_PRODUCT_VIATECH_VT8231: 485 aprint_normal("VT8231 ATA100 controller\n"); 486 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 487 break; 488 case PCI_PRODUCT_VIATECH_VT8233: 489 aprint_normal("VT8233 ATA100 controller\n"); 490 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 491 break; 492 case PCI_PRODUCT_VIATECH_VT8233A: 493 aprint_normal("VT8233A ATA133 controller\n"); 494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 495 break; 496 case PCI_PRODUCT_VIATECH_VT8235: 497 aprint_normal("VT8235 ATA133 controller\n"); 498 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 499 break; 500 case PCI_PRODUCT_VIATECH_VT8237: 501 aprint_normal("VT8237 ATA133 controller\n"); 502 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 503 break; 504 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 505 aprint_normal("VT8237A ATA133 controller\n"); 506 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 507 break; 508 case PCI_PRODUCT_VIATECH_CX700_IDE: 509 aprint_normal("CX700 ATA133 controller\n"); 510 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 511 break; 512 default: 513 unknown: 514 aprint_normal("unknown VIA ATA controller\n"); 515 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 516 } 517 sc->sc_apo_regbase = APO_VIA_REGBASE; 518 break; 519 case PCI_VENDOR_AMD: 520 switch (sc->sc_pp->ide_product) { 521 case PCI_PRODUCT_AMD_PBC8111_IDE: 522 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 523 break; 524 case PCI_PRODUCT_AMD_CS5536_IDE: 525 case PCI_PRODUCT_AMD_PBC766_IDE: 526 case PCI_PRODUCT_AMD_PBC768_IDE: 527 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 528 break; 529 default: 530 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 531 } 532 sc->sc_apo_regbase = APO_AMD_REGBASE; 533 break; 534 case PCI_VENDOR_NVIDIA: 535 switch (sc->sc_pp->ide_product) { 536 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 537 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 538 break; 539 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 540 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 541 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 542 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 543 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 544 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 545 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 546 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 547 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 548 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 549 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 550 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 551 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 552 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 553 break; 554 } 555 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 556 break; 557 default: 558 panic("via_chip_map: unknown vendor"); 559 } 560 561 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 562 "bus-master DMA support present"); 563 pciide_mapreg_dma(sc, pa); 564 aprint_verbose("\n"); 565 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 566 if (sc->sc_dma_ok) { 567 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 568 sc->sc_wdcdev.irqack = pciide_irqack; 569 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 570 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 571 } 572 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 573 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 574 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 575 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 576 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 577 578 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 579 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 580 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 581 582 wdc_allocate_regs(&sc->sc_wdcdev); 583 584 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 585 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 586 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 587 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 588 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 589 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 590 DEBUG_PROBE); 591 592 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 593 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 594 channel++) { 595 cp = &sc->pciide_channels[channel]; 596 if (pciide_chansetup(sc, channel, interface) == 0) 597 continue; 598 599 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 600 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 601 "%s channel ignored (disabled)\n", cp->name); 602 cp->ata_channel.ch_flags |= ATACH_DISABLED; 603 continue; 604 } 605 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 606 pciide_pci_intr); 607 } 608 } 609 610 static void 611 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 612 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 613 int (*pci_intr)(void *)) 614 { 615 struct ata_channel *wdc_cp; 616 struct pciide_softc *sc; 617 prop_bool_t compat_nat_enable; 618 619 wdc_cp = &cp->ata_channel; 620 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 621 compat_nat_enable = prop_dictionary_get( 622 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 623 "use-compat-native-irq"); 624 625 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 626 /* native mode with irq 14/15 requested? */ 627 if (compat_nat_enable != NULL && 628 prop_bool_true(compat_nat_enable)) 629 via_mapregs_compat_native(pa, cp, cmdsizep, ctlsizep); 630 else 631 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 632 pci_intr); 633 } else { 634 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 635 ctlsizep); 636 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 637 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 638 } 639 wdcattach(wdc_cp); 640 } 641 642 /* 643 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 644 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 645 * programmed to use a single native PCI irq alone. So we install an interrupt 646 * handler for each channel, as in compatibility mode. 647 */ 648 static void 649 via_mapregs_compat_native(struct pci_attach_args *pa, 650 struct pciide_channel *cp, bus_size_t *cmdsizep, bus_size_t *ctlsizep) 651 { 652 struct ata_channel *wdc_cp; 653 struct pciide_softc *sc; 654 655 wdc_cp = &cp->ata_channel; 656 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 657 658 /* XXX prevent pciide_mapregs_native from installing a handler */ 659 if (sc->sc_pci_ih == NULL) 660 sc->sc_pci_ih = (void *)~0; 661 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL); 662 663 /* interrupts are fixed to 14/15, as in compatibility mode */ 664 cp->compat = 1; 665 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 666 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 667 cp->ih = pciide_machdep_compat_intr_establish( 668 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 669 pciide_compat_intr, cp); 670 if (cp->ih == NULL) { 671 #endif 672 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 673 "no compatibility interrupt for " 674 "use by %s channel\n", cp->name); 675 wdc_cp->ch_flags |= ATACH_DISABLED; 676 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 677 } 678 sc->sc_pci_ih = cp->ih; /* XXX */ 679 #endif 680 } 681 } 682 683 static void 684 via_setup_channel(struct ata_channel *chp) 685 { 686 u_int32_t udmatim_reg, datatim_reg; 687 u_int8_t idedma_ctl; 688 int mode, drive, s; 689 struct ata_drive_datas *drvp; 690 struct atac_softc *atac = chp->ch_atac; 691 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 692 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 693 #ifndef PCIIDE_AMD756_ENABLEDMA 694 int rev = PCI_REVISION( 695 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 696 #endif 697 698 idedma_ctl = 0; 699 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 700 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 701 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 702 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 703 704 /* setup DMA if needed */ 705 pciide_channel_dma_setup(cp); 706 707 for (drive = 0; drive < 2; drive++) { 708 drvp = &chp->ch_drive[drive]; 709 /* If no drive, skip */ 710 if ((drvp->drive_flags & DRIVE) == 0) 711 continue; 712 /* add timing values, setup DMA if needed */ 713 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 714 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 715 mode = drvp->PIO_mode; 716 goto pio; 717 } 718 if ((atac->atac_cap & ATAC_CAP_UDMA) && 719 (drvp->drive_flags & DRIVE_UDMA)) { 720 /* use Ultra/DMA */ 721 s = splbio(); 722 drvp->drive_flags &= ~DRIVE_DMA; 723 splx(s); 724 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 725 APO_UDMA_EN_MTH(chp->ch_channel, drive); 726 switch (PCI_VENDOR(sc->sc_pci_id)) { 727 case PCI_VENDOR_VIATECH: 728 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 729 /* 8233a */ 730 udmatim_reg |= APO_UDMA_TIME( 731 chp->ch_channel, 732 drive, 733 via_udma133_tim[drvp->UDMA_mode]); 734 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 735 /* 686b */ 736 udmatim_reg |= APO_UDMA_TIME( 737 chp->ch_channel, 738 drive, 739 via_udma100_tim[drvp->UDMA_mode]); 740 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 741 /* 596b or 686a */ 742 udmatim_reg |= APO_UDMA_CLK66( 743 chp->ch_channel); 744 udmatim_reg |= APO_UDMA_TIME( 745 chp->ch_channel, 746 drive, 747 via_udma66_tim[drvp->UDMA_mode]); 748 } else { 749 /* 596a or 586b */ 750 udmatim_reg |= APO_UDMA_TIME( 751 chp->ch_channel, 752 drive, 753 via_udma33_tim[drvp->UDMA_mode]); 754 } 755 break; 756 case PCI_VENDOR_AMD: 757 case PCI_VENDOR_NVIDIA: 758 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 759 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 760 break; 761 } 762 /* can use PIO timings, MW DMA unused */ 763 mode = drvp->PIO_mode; 764 } else { 765 /* use Multiword DMA, but only if revision is OK */ 766 s = splbio(); 767 drvp->drive_flags &= ~DRIVE_UDMA; 768 splx(s); 769 #ifndef PCIIDE_AMD756_ENABLEDMA 770 /* 771 * The workaround doesn't seem to be necessary 772 * with all drives, so it can be disabled by 773 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 774 * triggered. 775 */ 776 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 777 sc->sc_pp->ide_product == 778 PCI_PRODUCT_AMD_PBC756_IDE && 779 AMD756_CHIPREV_DISABLEDMA(rev)) { 780 aprint_normal( 781 "%s:%d:%d: multi-word DMA disabled due " 782 "to chip revision\n", 783 device_xname( 784 sc->sc_wdcdev.sc_atac.atac_dev), 785 chp->ch_channel, drive); 786 mode = drvp->PIO_mode; 787 s = splbio(); 788 drvp->drive_flags &= ~DRIVE_DMA; 789 splx(s); 790 goto pio; 791 } 792 #endif 793 /* mode = min(pio, dma+2) */ 794 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 795 mode = drvp->PIO_mode; 796 else 797 mode = drvp->DMA_mode + 2; 798 } 799 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 800 801 pio: /* setup PIO mode */ 802 if (mode <= 2) { 803 drvp->DMA_mode = 0; 804 drvp->PIO_mode = 0; 805 mode = 0; 806 } else { 807 drvp->PIO_mode = mode; 808 drvp->DMA_mode = mode - 2; 809 } 810 datatim_reg |= 811 APO_DATATIM_PULSE(chp->ch_channel, drive, 812 apollo_pio_set[mode]) | 813 APO_DATATIM_RECOV(chp->ch_channel, drive, 814 apollo_pio_rec[mode]); 815 } 816 if (idedma_ctl != 0) { 817 /* Add software bits in status register */ 818 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 819 idedma_ctl); 820 } 821 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 822 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 823 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 824 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 825 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 826 } 827 828 static int 829 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 830 { 831 bus_size_t satasize; 832 int maptype, ret; 833 834 if (pciide_chipen(sc, pa) == 0) 835 return 0; 836 837 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 838 "bus-master DMA support present"); 839 pciide_mapreg_dma(sc, pa); 840 aprint_verbose("\n"); 841 842 if (sc->sc_dma_ok) { 843 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 844 sc->sc_wdcdev.irqack = pciide_irqack; 845 } 846 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 847 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 848 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 849 850 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 851 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 852 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 853 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 854 855 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 856 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 857 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 858 859 wdc_allocate_regs(&sc->sc_wdcdev); 860 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 861 PCI_MAPREG_START + 0x14); 862 switch(maptype) { 863 case PCI_MAPREG_TYPE_IO: 864 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 865 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 866 NULL, &satasize); 867 break; 868 case PCI_MAPREG_MEM_TYPE_32BIT: 869 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 870 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 871 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 872 NULL, &satasize); 873 break; 874 default: 875 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 876 "couldn't map sata regs, unsupported maptype (0x%x)\n", 877 maptype); 878 return 0; 879 } 880 if (ret != 0) { 881 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 882 "couldn't map sata regs\n"); 883 return 0; 884 } 885 return 1; 886 } 887 888 static void 889 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 890 int satareg_shift) 891 { 892 struct pciide_channel *cp; 893 struct ata_channel *wdc_cp; 894 struct wdc_regs *wdr; 895 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 896 int channel; 897 bus_size_t cmdsize, ctlsize; 898 899 if (via_sata_chip_map_common(sc, pa) == 0) 900 return; 901 902 if (interface == 0) { 903 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 904 DEBUG_PROBE); 905 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 906 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 907 } 908 909 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 910 channel++) { 911 cp = &sc->pciide_channels[channel]; 912 if (pciide_chansetup(sc, channel, interface) == 0) 913 continue; 914 wdc_cp = &cp->ata_channel; 915 wdr = CHAN_TO_WDC_REGS(wdc_cp); 916 wdr->sata_iot = sc->sc_ba5_st; 917 wdr->sata_baseioh = sc->sc_ba5_sh; 918 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 919 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 920 &wdr->sata_status) != 0) { 921 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 922 "couldn't map channel %d sata_status regs\n", 923 wdc_cp->ch_channel); 924 continue; 925 } 926 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 927 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 928 &wdr->sata_error) != 0) { 929 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 930 "couldn't map channel %d sata_error regs\n", 931 wdc_cp->ch_channel); 932 continue; 933 } 934 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 935 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 936 &wdr->sata_control) != 0) { 937 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 938 "couldn't map channel %d sata_control regs\n", 939 wdc_cp->ch_channel); 940 continue; 941 } 942 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 943 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 944 pciide_pci_intr); 945 } 946 } 947 948 static void 949 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 950 { 951 via_sata_chip_map(sc, pa, 0); 952 } 953 954 static void 955 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 956 { 957 via_sata_chip_map(sc, pa, 6); 958 } 959 960 static void 961 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 962 { 963 via_sata_chip_map(sc, pa, 7); 964 } 965 966 static void 967 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 968 { 969 struct pciide_channel *cp; 970 struct ata_channel *wdc_cp; 971 struct wdc_regs *wdr; 972 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 973 int channel; 974 bus_size_t cmdsize; 975 pci_intr_handle_t intrhandle; 976 const char *intrstr; 977 int i; 978 979 if (via_sata_chip_map_common(sc, pa) == 0) 980 return; 981 982 if (interface == 0) { 983 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 984 DEBUG_PROBE); 985 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 986 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 987 } 988 989 if (pci_intr_map(pa, &intrhandle) != 0) { 990 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 991 "couldn't map native-PCI interrupt\n"); 992 return; 993 } 994 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 995 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 996 intrhandle, IPL_BIO, pciide_pci_intr, sc); 997 if (sc->sc_pci_ih == NULL) { 998 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 999 "couldn't establish native-PCI interrupt"); 1000 if (intrstr != NULL) 1001 aprint_error(" at %s", intrstr); 1002 aprint_error("\n"); 1003 return; 1004 } 1005 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1006 "using %s for native-PCI interrupt\n", 1007 intrstr ? intrstr : "unknown interrupt"); 1008 1009 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1010 channel++) { 1011 cp = &sc->pciide_channels[channel]; 1012 if (pciide_chansetup(sc, channel, interface) == 0) 1013 continue; 1014 cp->ata_channel.ch_ndrive = 1; 1015 wdc_cp = &cp->ata_channel; 1016 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1017 1018 wdr->sata_iot = sc->sc_ba5_st; 1019 wdr->sata_baseioh = sc->sc_ba5_sh; 1020 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1021 (wdc_cp->ch_channel << 6) + 0x0, 1, 1022 &wdr->sata_status) != 0) { 1023 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1024 "couldn't map channel %d sata_status regs\n", 1025 wdc_cp->ch_channel); 1026 continue; 1027 } 1028 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1029 (wdc_cp->ch_channel << 6) + 0x4, 1, 1030 &wdr->sata_error) != 0) { 1031 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1032 "couldn't map channel %d sata_error regs\n", 1033 wdc_cp->ch_channel); 1034 continue; 1035 } 1036 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1037 (wdc_cp->ch_channel << 6) + 0x8, 1, 1038 &wdr->sata_control) != 0) { 1039 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1040 "couldn't map channel %d sata_control regs\n", 1041 wdc_cp->ch_channel); 1042 continue; 1043 } 1044 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1045 1046 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 1047 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1048 NULL, &cmdsize) != 0) { 1049 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1050 "couldn't map %s channel regs\n", cp->name); 1051 } 1052 wdr->ctl_iot = wdr->cmd_iot; 1053 for (i = 0; i < WDC_NREG; i++) { 1054 if (bus_space_subregion(wdr->cmd_iot, 1055 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1056 &wdr->cmd_iohs[i]) != 0) { 1057 aprint_error_dev( 1058 sc->sc_wdcdev.sc_atac.atac_dev, 1059 "couldn't subregion %s " 1060 "channel cmd regs\n", cp->name); 1061 return; 1062 } 1063 } 1064 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1065 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1066 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1067 "couldn't map channel %d ctl regs\n", channel); 1068 return; 1069 } 1070 wdc_init_shadow_regs(wdc_cp); 1071 wdcattach(wdc_cp); 1072 } 1073 } 1074
Indexes created Sat Oct 18 23:09:54 GMT 2025