viaide.c revision 1.52
1 /* $NetBSD: viaide.c,v 1.52 2008/02/29 06:13:39 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.52 2008/02/29 06:13:39 dyoung Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 48 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *)); 49 static void vt8231_mapregs_native(struct pci_attach_args *, 50 struct pciide_channel *, bus_size_t *, bus_size_t *, 51 int (*)(void *)); 52 static int via_sata_chip_map_common(struct pciide_softc *, 53 struct pci_attach_args *); 54 static void via_sata_chip_map(struct pciide_softc *, 55 struct pci_attach_args *, int); 56 static void via_sata_chip_map_0(struct pciide_softc *, 57 struct pci_attach_args *); 58 static void via_sata_chip_map_6(struct pciide_softc *, 59 struct pci_attach_args *); 60 static void via_sata_chip_map_7(struct pciide_softc *, 61 struct pci_attach_args *); 62 static void via_sata_chip_map_new(struct pciide_softc *, 63 struct pci_attach_args *); 64 static void via_setup_channel(struct ata_channel *); 65 66 static int viaide_match(struct device *, struct cfdata *, void *); 67 static void viaide_attach(struct device *, struct device *, void *); 68 static const struct pciide_product_desc * 69 viaide_lookup(pcireg_t); 70 static bool viaide_suspend(device_t PMF_FN_PROTO); 71 static bool viaide_resume(device_t PMF_FN_PROTO); 72 73 CFATTACH_DECL(viaide, sizeof(struct pciide_softc), 74 viaide_match, viaide_attach, NULL, NULL); 75 76 static const struct pciide_product_desc pciide_amd_products[] = { 77 { PCI_PRODUCT_AMD_PBC756_IDE, 78 0, 79 "Advanced Micro Devices AMD756 IDE Controller", 80 via_chip_map 81 }, 82 { PCI_PRODUCT_AMD_PBC766_IDE, 83 0, 84 "Advanced Micro Devices AMD766 IDE Controller", 85 via_chip_map 86 }, 87 { PCI_PRODUCT_AMD_PBC768_IDE, 88 0, 89 "Advanced Micro Devices AMD768 IDE Controller", 90 via_chip_map 91 }, 92 { PCI_PRODUCT_AMD_PBC8111_IDE, 93 0, 94 "Advanced Micro Devices AMD8111 IDE Controller", 95 via_chip_map 96 }, 97 { PCI_PRODUCT_AMD_CS5536_IDE, 98 0, 99 "Advanced Micro Devices CS5536 IDE Controller", 100 via_chip_map 101 }, 102 { 0, 103 0, 104 NULL, 105 NULL 106 } 107 }; 108 109 static const struct pciide_product_desc pciide_nvidia_products[] = { 110 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 111 0, 112 "NVIDIA nForce IDE Controller", 113 via_chip_map 114 }, 115 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 116 0, 117 "NVIDIA nForce2 IDE Controller", 118 via_chip_map 119 }, 120 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 121 0, 122 "NVIDIA nForce2 Ultra 400 IDE Controller", 123 via_chip_map 124 }, 125 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 126 0, 127 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 128 via_sata_chip_map_6 129 }, 130 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 131 0, 132 "NVIDIA nForce3 IDE Controller", 133 via_chip_map 134 }, 135 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 136 0, 137 "NVIDIA nForce3 250 IDE Controller", 138 via_chip_map 139 }, 140 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 141 0, 142 "NVIDIA nForce3 250 Serial ATA Controller", 143 via_sata_chip_map_6 144 }, 145 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 146 0, 147 "NVIDIA nForce3 250 Serial ATA Controller", 148 via_sata_chip_map_6 149 }, 150 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 151 0, 152 "NVIDIA nForce4 IDE Controller", 153 via_chip_map 154 }, 155 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 156 0, 157 "NVIDIA nForce4 Serial ATA Controller", 158 via_sata_chip_map_6 159 }, 160 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 161 0, 162 "NVIDIA nForce4 Serial ATA Controller", 163 via_sata_chip_map_6 164 }, 165 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 166 0, 167 "NVIDIA nForce430 IDE Controller", 168 via_chip_map 169 }, 170 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 171 0, 172 "NVIDIA nForce430 Serial ATA Controller", 173 via_sata_chip_map_6 174 }, 175 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 176 0, 177 "NVIDIA nForce430 Serial ATA Controller", 178 via_sata_chip_map_6 179 }, 180 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 181 0, 182 "NVIDIA MCP04 IDE Controller", 183 via_chip_map 184 }, 185 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 186 0, 187 "NVIDIA MCP04 Serial ATA Controller", 188 via_sata_chip_map_6 189 }, 190 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 191 0, 192 "NVIDIA MCP04 Serial ATA Controller", 193 via_sata_chip_map_6 194 }, 195 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 196 0, 197 "NVIDIA MCP55 IDE Controller", 198 via_chip_map 199 }, 200 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 201 0, 202 "NVIDIA MCP55 Serial ATA Controller", 203 via_sata_chip_map_6 204 }, 205 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 206 0, 207 "NVIDIA MCP55 Serial ATA Controller", 208 via_sata_chip_map_6 209 }, 210 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 211 0, 212 "NVIDIA MCP61 IDE Controller", 213 via_chip_map 214 }, 215 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 216 0, 217 "NVIDIA MCP65 IDE Controller", 218 via_chip_map 219 }, 220 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 221 0, 222 "NVIDIA MCP73 IDE Controller", 223 via_chip_map 224 }, 225 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 226 0, 227 "NVIDIA MCP77 IDE Controller", 228 via_chip_map 229 }, 230 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 231 0, 232 "NVIDIA MCP61 Serial ATA Controller", 233 via_sata_chip_map_6 234 }, 235 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 236 0, 237 "NVIDIA MCP61 Serial ATA Controller", 238 via_sata_chip_map_6 239 }, 240 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 241 0, 242 "NVIDIA MCP61 Serial ATA Controller", 243 via_sata_chip_map_6 244 }, 245 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 246 0, 247 "NVIDIA MCP65 Serial ATA Controller", 248 via_sata_chip_map_6 249 }, 250 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 251 0, 252 "NVIDIA MCP65 Serial ATA Controller", 253 via_sata_chip_map_6 254 }, 255 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 256 0, 257 "NVIDIA MCP65 Serial ATA Controller", 258 via_sata_chip_map_6 259 }, 260 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 261 0, 262 "NVIDIA MCP65 Serial ATA Controller", 263 via_sata_chip_map_6 264 }, 265 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 266 0, 267 "NVIDIA MCP67 IDE Controller", 268 via_chip_map, 269 }, 270 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 271 0, 272 "NVIDIA MCP67 Serial ATA Controller", 273 via_sata_chip_map_6, 274 }, 275 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 276 0, 277 "NVIDIA MCP67 Serial ATA Controller", 278 via_sata_chip_map_6, 279 }, 280 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 281 0, 282 "NVIDIA MCP67 Serial ATA Controller", 283 via_sata_chip_map_6, 284 }, 285 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 286 0, 287 "NVIDIA MCP67 Serial ATA Controller", 288 via_sata_chip_map_6, 289 }, 290 { 0, 291 0, 292 NULL, 293 NULL 294 } 295 }; 296 297 static const struct pciide_product_desc pciide_via_products[] = { 298 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 299 0, 300 NULL, 301 via_chip_map, 302 }, 303 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 304 0, 305 NULL, 306 via_chip_map, 307 }, 308 { PCI_PRODUCT_VIATECH_CX700_IDE, 309 0, 310 NULL, 311 via_chip_map, 312 }, 313 { PCI_PRODUCT_VIATECH_VT6421_RAID, 314 0, 315 "VIA Technologies VT6421 Serial RAID Controller", 316 via_sata_chip_map_new, 317 }, 318 { PCI_PRODUCT_VIATECH_VT8237_SATA, 319 0, 320 "VIA Technologies VT8237 SATA Controller", 321 via_sata_chip_map_7, 322 }, 323 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 324 0, 325 "VIA Technologies VT8237A SATA Controller", 326 via_sata_chip_map_7, 327 }, 328 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 329 0, 330 "VIA Technologies VT8237R SATA Controller", 331 via_sata_chip_map_0, 332 }, 333 { 0, 334 0, 335 NULL, 336 NULL 337 } 338 }; 339 340 static const struct pciide_product_desc * 341 viaide_lookup(pcireg_t id) 342 { 343 344 switch (PCI_VENDOR(id)) { 345 case PCI_VENDOR_VIATECH: 346 return (pciide_lookup_product(id, pciide_via_products)); 347 348 case PCI_VENDOR_AMD: 349 return (pciide_lookup_product(id, pciide_amd_products)); 350 351 case PCI_VENDOR_NVIDIA: 352 return (pciide_lookup_product(id, pciide_nvidia_products)); 353 } 354 return (NULL); 355 } 356 357 static int 358 viaide_match(struct device *parent, struct cfdata *match, 359 void *aux) 360 { 361 struct pci_attach_args *pa = aux; 362 363 if (viaide_lookup(pa->pa_id) != NULL) 364 return (2); 365 return (0); 366 } 367 368 static void 369 viaide_attach(struct device *parent, struct device *self, void *aux) 370 { 371 struct pci_attach_args *pa = aux; 372 struct pciide_softc *sc = (struct pciide_softc *)self; 373 const struct pciide_product_desc *pp; 374 375 pp = viaide_lookup(pa->pa_id); 376 if (pp == NULL) 377 panic("viaide_attach"); 378 pciide_common_attach(sc, pa, pp); 379 380 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 381 aprint_error_dev(self, "couldn't establish power handler\n"); 382 } 383 384 static int 385 via_pcib_match(struct pci_attach_args *pa) 386 { 387 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 388 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 389 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 390 return (1); 391 return 0; 392 } 393 394 static bool 395 viaide_suspend(device_t dv PMF_FN_ARGS) 396 { 397 struct pciide_softc *sc = device_private(dv); 398 399 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 400 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 401 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 402 /* This two are VIA-only, but should be ignored by other devices. */ 403 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 404 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 405 406 return true; 407 } 408 409 static bool 410 viaide_resume(device_t dv PMF_FN_ARGS) 411 { 412 struct pciide_softc *sc = device_private(dv); 413 414 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 415 sc->sc_pm_reg[0]); 416 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 417 sc->sc_pm_reg[1]); 418 /* This two are VIA-only, but should be ignored by other devices. */ 419 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 420 sc->sc_pm_reg[2]); 421 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 422 sc->sc_pm_reg[3]); 423 424 return true; 425 } 426 427 static void 428 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 429 { 430 struct pciide_channel *cp; 431 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 432 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 433 int channel; 434 u_int32_t ideconf; 435 bus_size_t cmdsize, ctlsize; 436 pcireg_t pcib_id, pcib_class; 437 struct pci_attach_args pcib_pa; 438 439 if (pciide_chipen(sc, pa) == 0) 440 return; 441 442 switch (vendor) { 443 case PCI_VENDOR_VIATECH: 444 /* 445 * get a PCI tag for the ISA bridge. 446 */ 447 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 448 goto unknown; 449 pcib_id = pcib_pa.pa_id; 450 pcib_class = pcib_pa.pa_class; 451 aprint_normal("%s: VIA Technologies ", 452 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 453 switch (PCI_PRODUCT(pcib_id)) { 454 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 455 aprint_normal("VT82C586 (Apollo VP) "); 456 if(PCI_REVISION(pcib_class) >= 0x02) { 457 aprint_normal("ATA33 controller\n"); 458 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 459 } else { 460 aprint_normal("controller\n"); 461 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 462 } 463 break; 464 case PCI_PRODUCT_VIATECH_VT82C596A: 465 aprint_normal("VT82C596A (Apollo Pro) "); 466 if (PCI_REVISION(pcib_class) >= 0x12) { 467 aprint_normal("ATA66 controller\n"); 468 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 469 } else { 470 aprint_normal("ATA33 controller\n"); 471 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 472 } 473 break; 474 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 475 aprint_normal("VT82C686A (Apollo KX133) "); 476 if (PCI_REVISION(pcib_class) >= 0x40) { 477 aprint_normal("ATA100 controller\n"); 478 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 479 } else { 480 aprint_normal("ATA66 controller\n"); 481 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 482 } 483 break; 484 case PCI_PRODUCT_VIATECH_VT8231: 485 aprint_normal("VT8231 ATA100 controller\n"); 486 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 487 break; 488 case PCI_PRODUCT_VIATECH_VT8233: 489 aprint_normal("VT8233 ATA100 controller\n"); 490 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 491 break; 492 case PCI_PRODUCT_VIATECH_VT8233A: 493 aprint_normal("VT8233A ATA133 controller\n"); 494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 495 break; 496 case PCI_PRODUCT_VIATECH_VT8235: 497 aprint_normal("VT8235 ATA133 controller\n"); 498 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 499 break; 500 case PCI_PRODUCT_VIATECH_VT8237: 501 aprint_normal("VT8237 ATA133 controller\n"); 502 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 503 break; 504 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 505 aprint_normal("VT8237A ATA133 controller\n"); 506 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 507 break; 508 case PCI_PRODUCT_VIATECH_CX700_IDE: 509 aprint_normal("CX700 ATA133 controller\n"); 510 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 511 break; 512 default: 513 unknown: 514 aprint_normal("unknown VIA ATA controller\n"); 515 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 516 } 517 sc->sc_apo_regbase = APO_VIA_REGBASE; 518 break; 519 case PCI_VENDOR_AMD: 520 switch (sc->sc_pp->ide_product) { 521 case PCI_PRODUCT_AMD_PBC8111_IDE: 522 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 523 break; 524 case PCI_PRODUCT_AMD_CS5536_IDE: 525 case PCI_PRODUCT_AMD_PBC766_IDE: 526 case PCI_PRODUCT_AMD_PBC768_IDE: 527 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 528 break; 529 default: 530 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 531 } 532 sc->sc_apo_regbase = APO_AMD_REGBASE; 533 break; 534 case PCI_VENDOR_NVIDIA: 535 switch (sc->sc_pp->ide_product) { 536 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 537 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 538 break; 539 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 540 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 541 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 542 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 543 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 544 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 545 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 546 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 547 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 548 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 549 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 550 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 551 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 552 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 553 break; 554 } 555 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 556 break; 557 default: 558 panic("via_chip_map: unknown vendor"); 559 } 560 561 aprint_verbose("%s: bus-master DMA support present", 562 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 563 pciide_mapreg_dma(sc, pa); 564 aprint_verbose("\n"); 565 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 566 if (sc->sc_dma_ok) { 567 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 568 sc->sc_wdcdev.irqack = pciide_irqack; 569 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 570 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 571 } 572 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 573 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 574 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 575 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 576 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 577 578 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 579 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 580 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 581 582 wdc_allocate_regs(&sc->sc_wdcdev); 583 584 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 585 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 586 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 587 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 588 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 589 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 590 DEBUG_PROBE); 591 592 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 593 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 594 channel++) { 595 cp = &sc->pciide_channels[channel]; 596 if (pciide_chansetup(sc, channel, interface) == 0) 597 continue; 598 599 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 600 aprint_normal("%s: %s channel ignored (disabled)\n", 601 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 602 cp->ata_channel.ch_flags |= ATACH_DISABLED; 603 continue; 604 } 605 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 606 pciide_pci_intr); 607 } 608 } 609 610 static void 611 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 612 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 613 int (*pci_intr)(void *)) 614 { 615 struct ata_channel *wdc_cp; 616 struct pciide_softc *sc; 617 prop_bool_t compat_nat_enable; 618 619 wdc_cp = &cp->ata_channel; 620 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 621 compat_nat_enable = prop_dictionary_get( 622 device_properties((struct device *)sc), "use-compat-native-irq"); 623 624 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 625 /* native mode with irq 14/15 requested? */ 626 if (compat_nat_enable != NULL && 627 prop_bool_true(compat_nat_enable)) 628 vt8231_mapregs_native(pa, cp, cmdsizep, ctlsizep, 629 pci_intr); 630 else 631 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 632 pci_intr); 633 } else { 634 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 635 ctlsizep); 636 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 637 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 638 } 639 wdcattach(wdc_cp); 640 } 641 642 /* 643 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 644 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 645 * programmed to use a single native PCI irq alone. So we install an interrupt 646 * handler for each channel, as in compatibility mode. 647 */ 648 static void 649 vt8231_mapregs_native(struct pci_attach_args *pa, struct pciide_channel *cp, 650 bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *)) 651 { 652 struct ata_channel *wdc_cp; 653 struct pciide_softc *sc; 654 655 wdc_cp = &cp->ata_channel; 656 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 657 658 /* XXX prevent pciide_mapregs_native from installing a handler */ 659 if (sc->sc_pci_ih == NULL) 660 sc->sc_pci_ih = (void *)~0; 661 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL); 662 663 /* interrupts are fixed to 14/15, as in compatibility mode */ 664 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 665 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 666 cp->ih = pciide_machdep_compat_intr_establish( 667 &sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 668 pci_intr, sc); 669 if (cp->ih == NULL) { 670 #endif 671 aprint_error("%s: no compatibility interrupt for " 672 "use by %s channel\n", 673 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 674 wdc_cp->ch_flags |= ATACH_DISABLED; 675 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 676 } 677 sc->sc_pci_ih = cp->ih; /* XXX */ 678 #endif 679 } 680 } 681 682 static void 683 via_setup_channel(struct ata_channel *chp) 684 { 685 u_int32_t udmatim_reg, datatim_reg; 686 u_int8_t idedma_ctl; 687 int mode, drive, s; 688 struct ata_drive_datas *drvp; 689 struct atac_softc *atac = chp->ch_atac; 690 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 691 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 692 #ifndef PCIIDE_AMD756_ENABLEDMA 693 int rev = PCI_REVISION( 694 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 695 #endif 696 697 idedma_ctl = 0; 698 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 699 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 700 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 701 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 702 703 /* setup DMA if needed */ 704 pciide_channel_dma_setup(cp); 705 706 for (drive = 0; drive < 2; drive++) { 707 drvp = &chp->ch_drive[drive]; 708 /* If no drive, skip */ 709 if ((drvp->drive_flags & DRIVE) == 0) 710 continue; 711 /* add timing values, setup DMA if needed */ 712 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 713 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 714 mode = drvp->PIO_mode; 715 goto pio; 716 } 717 if ((atac->atac_cap & ATAC_CAP_UDMA) && 718 (drvp->drive_flags & DRIVE_UDMA)) { 719 /* use Ultra/DMA */ 720 s = splbio(); 721 drvp->drive_flags &= ~DRIVE_DMA; 722 splx(s); 723 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 724 APO_UDMA_EN_MTH(chp->ch_channel, drive); 725 switch (PCI_VENDOR(sc->sc_pci_id)) { 726 case PCI_VENDOR_VIATECH: 727 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 728 /* 8233a */ 729 udmatim_reg |= APO_UDMA_TIME( 730 chp->ch_channel, 731 drive, 732 via_udma133_tim[drvp->UDMA_mode]); 733 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 734 /* 686b */ 735 udmatim_reg |= APO_UDMA_TIME( 736 chp->ch_channel, 737 drive, 738 via_udma100_tim[drvp->UDMA_mode]); 739 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 740 /* 596b or 686a */ 741 udmatim_reg |= APO_UDMA_CLK66( 742 chp->ch_channel); 743 udmatim_reg |= APO_UDMA_TIME( 744 chp->ch_channel, 745 drive, 746 via_udma66_tim[drvp->UDMA_mode]); 747 } else { 748 /* 596a or 586b */ 749 udmatim_reg |= APO_UDMA_TIME( 750 chp->ch_channel, 751 drive, 752 via_udma33_tim[drvp->UDMA_mode]); 753 } 754 break; 755 case PCI_VENDOR_AMD: 756 case PCI_VENDOR_NVIDIA: 757 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 758 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 759 break; 760 } 761 /* can use PIO timings, MW DMA unused */ 762 mode = drvp->PIO_mode; 763 } else { 764 /* use Multiword DMA, but only if revision is OK */ 765 s = splbio(); 766 drvp->drive_flags &= ~DRIVE_UDMA; 767 splx(s); 768 #ifndef PCIIDE_AMD756_ENABLEDMA 769 /* 770 * The workaround doesn't seem to be necessary 771 * with all drives, so it can be disabled by 772 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 773 * triggered. 774 */ 775 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 776 sc->sc_pp->ide_product == 777 PCI_PRODUCT_AMD_PBC756_IDE && 778 AMD756_CHIPREV_DISABLEDMA(rev)) { 779 aprint_normal( 780 "%s:%d:%d: multi-word DMA disabled due " 781 "to chip revision\n", 782 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 783 chp->ch_channel, drive); 784 mode = drvp->PIO_mode; 785 s = splbio(); 786 drvp->drive_flags &= ~DRIVE_DMA; 787 splx(s); 788 goto pio; 789 } 790 #endif 791 /* mode = min(pio, dma+2) */ 792 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 793 mode = drvp->PIO_mode; 794 else 795 mode = drvp->DMA_mode + 2; 796 } 797 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 798 799 pio: /* setup PIO mode */ 800 if (mode <= 2) { 801 drvp->DMA_mode = 0; 802 drvp->PIO_mode = 0; 803 mode = 0; 804 } else { 805 drvp->PIO_mode = mode; 806 drvp->DMA_mode = mode - 2; 807 } 808 datatim_reg |= 809 APO_DATATIM_PULSE(chp->ch_channel, drive, 810 apollo_pio_set[mode]) | 811 APO_DATATIM_RECOV(chp->ch_channel, drive, 812 apollo_pio_rec[mode]); 813 } 814 if (idedma_ctl != 0) { 815 /* Add software bits in status register */ 816 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 817 idedma_ctl); 818 } 819 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 820 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 821 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 822 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 823 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 824 } 825 826 static int 827 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 828 { 829 bus_size_t satasize; 830 int maptype, ret; 831 832 if (pciide_chipen(sc, pa) == 0) 833 return 0; 834 835 aprint_verbose("%s: bus-master DMA support present", 836 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 837 pciide_mapreg_dma(sc, pa); 838 aprint_verbose("\n"); 839 840 if (sc->sc_dma_ok) { 841 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 842 sc->sc_wdcdev.irqack = pciide_irqack; 843 } 844 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 845 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 846 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 847 848 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 849 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 850 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 851 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 852 853 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 854 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 855 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 856 857 wdc_allocate_regs(&sc->sc_wdcdev); 858 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 859 PCI_MAPREG_START + 0x14); 860 switch(maptype) { 861 case PCI_MAPREG_TYPE_IO: 862 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 863 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 864 NULL, &satasize); 865 break; 866 case PCI_MAPREG_MEM_TYPE_32BIT: 867 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 868 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 869 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 870 NULL, &satasize); 871 break; 872 default: 873 aprint_error("%s: couldn't map sata regs, unsupported" 874 "maptype (0x%x)\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 875 maptype); 876 return 0; 877 } 878 if (ret != 0) { 879 aprint_error("%s: couldn't map sata regs\n", 880 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 881 return 0; 882 } 883 return 1; 884 } 885 886 static void 887 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 888 int satareg_shift) 889 { 890 struct pciide_channel *cp; 891 struct ata_channel *wdc_cp; 892 struct wdc_regs *wdr; 893 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 894 int channel; 895 bus_size_t cmdsize, ctlsize; 896 897 if (via_sata_chip_map_common(sc, pa) == 0) 898 return; 899 900 if (interface == 0) { 901 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 902 DEBUG_PROBE); 903 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 904 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 905 } 906 907 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 908 channel++) { 909 cp = &sc->pciide_channels[channel]; 910 if (pciide_chansetup(sc, channel, interface) == 0) 911 continue; 912 wdc_cp = &cp->ata_channel; 913 wdr = CHAN_TO_WDC_REGS(wdc_cp); 914 wdr->sata_iot = sc->sc_ba5_st; 915 wdr->sata_baseioh = sc->sc_ba5_sh; 916 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 917 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 918 &wdr->sata_status) != 0) { 919 aprint_error("%s: couldn't map channel %d " 920 "sata_status regs\n", 921 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 922 wdc_cp->ch_channel); 923 continue; 924 } 925 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 926 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 927 &wdr->sata_error) != 0) { 928 aprint_error("%s: couldn't map channel %d " 929 "sata_error regs\n", 930 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 931 wdc_cp->ch_channel); 932 continue; 933 } 934 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 935 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 936 &wdr->sata_control) != 0) { 937 aprint_error("%s: couldn't map channel %d " 938 "sata_control regs\n", 939 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 940 wdc_cp->ch_channel); 941 continue; 942 } 943 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 944 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 945 pciide_pci_intr); 946 } 947 } 948 949 static void 950 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 951 { 952 via_sata_chip_map(sc, pa, 0); 953 } 954 955 static void 956 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 957 { 958 via_sata_chip_map(sc, pa, 6); 959 } 960 961 static void 962 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 963 { 964 via_sata_chip_map(sc, pa, 7); 965 } 966 967 static void 968 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 969 { 970 struct pciide_channel *cp; 971 struct ata_channel *wdc_cp; 972 struct wdc_regs *wdr; 973 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 974 int channel; 975 bus_size_t cmdsize; 976 pci_intr_handle_t intrhandle; 977 const char *intrstr; 978 int i; 979 980 if (via_sata_chip_map_common(sc, pa) == 0) 981 return; 982 983 if (interface == 0) { 984 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 985 DEBUG_PROBE); 986 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 987 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 988 } 989 990 if (pci_intr_map(pa, &intrhandle) != 0) { 991 aprint_error("%s: couldn't map native-PCI interrupt\n", 992 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 993 return; 994 } 995 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 996 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 997 intrhandle, IPL_BIO, pciide_pci_intr, sc); 998 if (sc->sc_pci_ih == NULL) { 999 aprint_error( 1000 "%s: couldn't establish native-PCI interrupt", 1001 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 1002 if (intrstr != NULL) 1003 aprint_error(" at %s", intrstr); 1004 aprint_error("\n"); 1005 return; 1006 } 1007 aprint_normal("%s: using %s for native-PCI interrupt\n", 1008 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1009 intrstr ? intrstr : "unknown interrupt"); 1010 1011 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1012 channel++) { 1013 cp = &sc->pciide_channels[channel]; 1014 if (pciide_chansetup(sc, channel, interface) == 0) 1015 continue; 1016 cp->ata_channel.ch_ndrive = 1; 1017 wdc_cp = &cp->ata_channel; 1018 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1019 1020 wdr->sata_iot = sc->sc_ba5_st; 1021 wdr->sata_baseioh = sc->sc_ba5_sh; 1022 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1023 (wdc_cp->ch_channel << 6) + 0x0, 1, 1024 &wdr->sata_status) != 0) { 1025 aprint_error("%s: couldn't map channel %d " 1026 "sata_status regs\n", 1027 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1028 wdc_cp->ch_channel); 1029 continue; 1030 } 1031 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1032 (wdc_cp->ch_channel << 6) + 0x4, 1, 1033 &wdr->sata_error) != 0) { 1034 aprint_error("%s: couldn't map channel %d " 1035 "sata_error regs\n", 1036 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1037 wdc_cp->ch_channel); 1038 continue; 1039 } 1040 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1041 (wdc_cp->ch_channel << 6) + 0x8, 1, 1042 &wdr->sata_control) != 0) { 1043 aprint_error("%s: couldn't map channel %d " 1044 "sata_control regs\n", 1045 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1046 wdc_cp->ch_channel); 1047 continue; 1048 } 1049 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1050 1051 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 1052 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1053 NULL, &cmdsize) != 0) { 1054 aprint_error("%s: couldn't map %s channel regs\n", 1055 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1056 cp->name); 1057 } 1058 wdr->ctl_iot = wdr->cmd_iot; 1059 for (i = 0; i < WDC_NREG; i++) { 1060 if (bus_space_subregion(wdr->cmd_iot, 1061 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1062 &wdr->cmd_iohs[i]) != 0) { 1063 aprint_error("%s: couldn't subregion %s " 1064 "channel cmd regs\n", 1065 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 1066 cp->name); 1067 return; 1068 } 1069 } 1070 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1071 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1072 aprint_error("%s: couldn't map channel %d ctl regs\n", 1073 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 1074 return; 1075 } 1076 wdc_init_shadow_regs(wdc_cp); 1077 wdcattach(wdc_cp); 1078 } 1079 } 1080
Indexes created Mon Oct 20 01:09:56 GMT 2025