viaide.c revision 1.53.2.1
1 /* $NetBSD: viaide.c,v 1.53.2.1 2008/05/18 12:34:23 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.53.2.1 2008/05/18 12:34:23 yamt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 48 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *)); 49 static void vt8231_mapregs_native(struct pci_attach_args *, 50 struct pciide_channel *, bus_size_t *, bus_size_t *, 51 int (*)(void *)); 52 static int via_sata_chip_map_common(struct pciide_softc *, 53 struct pci_attach_args *); 54 static void via_sata_chip_map(struct pciide_softc *, 55 struct pci_attach_args *, int); 56 static void via_sata_chip_map_0(struct pciide_softc *, 57 struct pci_attach_args *); 58 static void via_sata_chip_map_6(struct pciide_softc *, 59 struct pci_attach_args *); 60 static void via_sata_chip_map_7(struct pciide_softc *, 61 struct pci_attach_args *); 62 static void via_sata_chip_map_new(struct pciide_softc *, 63 struct pci_attach_args *); 64 static void via_setup_channel(struct ata_channel *); 65 66 static int viaide_match(device_t, cfdata_t, void *); 67 static void viaide_attach(device_t, device_t, void *); 68 static const struct pciide_product_desc * 69 viaide_lookup(pcireg_t); 70 static bool viaide_suspend(device_t PMF_FN_PROTO); 71 static bool viaide_resume(device_t PMF_FN_PROTO); 72 73 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 74 viaide_match, viaide_attach, NULL, NULL); 75 76 static const struct pciide_product_desc pciide_amd_products[] = { 77 { PCI_PRODUCT_AMD_PBC756_IDE, 78 0, 79 "Advanced Micro Devices AMD756 IDE Controller", 80 via_chip_map 81 }, 82 { PCI_PRODUCT_AMD_PBC766_IDE, 83 0, 84 "Advanced Micro Devices AMD766 IDE Controller", 85 via_chip_map 86 }, 87 { PCI_PRODUCT_AMD_PBC768_IDE, 88 0, 89 "Advanced Micro Devices AMD768 IDE Controller", 90 via_chip_map 91 }, 92 { PCI_PRODUCT_AMD_PBC8111_IDE, 93 0, 94 "Advanced Micro Devices AMD8111 IDE Controller", 95 via_chip_map 96 }, 97 { PCI_PRODUCT_AMD_CS5536_IDE, 98 0, 99 "Advanced Micro Devices CS5536 IDE Controller", 100 via_chip_map 101 }, 102 { 0, 103 0, 104 NULL, 105 NULL 106 } 107 }; 108 109 static const struct pciide_product_desc pciide_nvidia_products[] = { 110 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 111 0, 112 "NVIDIA nForce IDE Controller", 113 via_chip_map 114 }, 115 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 116 0, 117 "NVIDIA nForce2 IDE Controller", 118 via_chip_map 119 }, 120 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 121 0, 122 "NVIDIA nForce2 Ultra 400 IDE Controller", 123 via_chip_map 124 }, 125 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 126 0, 127 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 128 via_sata_chip_map_6 129 }, 130 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 131 0, 132 "NVIDIA nForce3 IDE Controller", 133 via_chip_map 134 }, 135 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 136 0, 137 "NVIDIA nForce3 250 IDE Controller", 138 via_chip_map 139 }, 140 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 141 0, 142 "NVIDIA nForce3 250 Serial ATA Controller", 143 via_sata_chip_map_6 144 }, 145 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 146 0, 147 "NVIDIA nForce3 250 Serial ATA Controller", 148 via_sata_chip_map_6 149 }, 150 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 151 0, 152 "NVIDIA nForce4 IDE Controller", 153 via_chip_map 154 }, 155 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 156 0, 157 "NVIDIA nForce4 Serial ATA Controller", 158 via_sata_chip_map_6 159 }, 160 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 161 0, 162 "NVIDIA nForce4 Serial ATA Controller", 163 via_sata_chip_map_6 164 }, 165 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 166 0, 167 "NVIDIA nForce430 IDE Controller", 168 via_chip_map 169 }, 170 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 171 0, 172 "NVIDIA nForce430 Serial ATA Controller", 173 via_sata_chip_map_6 174 }, 175 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 176 0, 177 "NVIDIA nForce430 Serial ATA Controller", 178 via_sata_chip_map_6 179 }, 180 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 181 0, 182 "NVIDIA MCP04 IDE Controller", 183 via_chip_map 184 }, 185 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 186 0, 187 "NVIDIA MCP04 Serial ATA Controller", 188 via_sata_chip_map_6 189 }, 190 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 191 0, 192 "NVIDIA MCP04 Serial ATA Controller", 193 via_sata_chip_map_6 194 }, 195 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 196 0, 197 "NVIDIA MCP55 IDE Controller", 198 via_chip_map 199 }, 200 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 201 0, 202 "NVIDIA MCP55 Serial ATA Controller", 203 via_sata_chip_map_6 204 }, 205 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 206 0, 207 "NVIDIA MCP55 Serial ATA Controller", 208 via_sata_chip_map_6 209 }, 210 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 211 0, 212 "NVIDIA MCP61 IDE Controller", 213 via_chip_map 214 }, 215 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 216 0, 217 "NVIDIA MCP65 IDE Controller", 218 via_chip_map 219 }, 220 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 221 0, 222 "NVIDIA MCP73 IDE Controller", 223 via_chip_map 224 }, 225 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 226 0, 227 "NVIDIA MCP77 IDE Controller", 228 via_chip_map 229 }, 230 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 231 0, 232 "NVIDIA MCP61 Serial ATA Controller", 233 via_sata_chip_map_6 234 }, 235 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 236 0, 237 "NVIDIA MCP61 Serial ATA Controller", 238 via_sata_chip_map_6 239 }, 240 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 241 0, 242 "NVIDIA MCP61 Serial ATA Controller", 243 via_sata_chip_map_6 244 }, 245 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 246 0, 247 "NVIDIA MCP65 Serial ATA Controller", 248 via_sata_chip_map_6 249 }, 250 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 251 0, 252 "NVIDIA MCP65 Serial ATA Controller", 253 via_sata_chip_map_6 254 }, 255 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 256 0, 257 "NVIDIA MCP65 Serial ATA Controller", 258 via_sata_chip_map_6 259 }, 260 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 261 0, 262 "NVIDIA MCP65 Serial ATA Controller", 263 via_sata_chip_map_6 264 }, 265 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 266 0, 267 "NVIDIA MCP67 IDE Controller", 268 via_chip_map, 269 }, 270 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 271 0, 272 "NVIDIA MCP67 Serial ATA Controller", 273 via_sata_chip_map_6, 274 }, 275 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 276 0, 277 "NVIDIA MCP67 Serial ATA Controller", 278 via_sata_chip_map_6, 279 }, 280 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 281 0, 282 "NVIDIA MCP67 Serial ATA Controller", 283 via_sata_chip_map_6, 284 }, 285 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 286 0, 287 "NVIDIA MCP67 Serial ATA Controller", 288 via_sata_chip_map_6, 289 }, 290 { 0, 291 0, 292 NULL, 293 NULL 294 } 295 }; 296 297 static const struct pciide_product_desc pciide_via_products[] = { 298 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 299 0, 300 NULL, 301 via_chip_map, 302 }, 303 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 304 0, 305 NULL, 306 via_chip_map, 307 }, 308 { PCI_PRODUCT_VIATECH_CX700_IDE, 309 0, 310 NULL, 311 via_chip_map, 312 }, 313 { PCI_PRODUCT_VIATECH_VT6421_RAID, 314 0, 315 "VIA Technologies VT6421 Serial RAID Controller", 316 via_sata_chip_map_new, 317 }, 318 { PCI_PRODUCT_VIATECH_VT8237_SATA, 319 0, 320 "VIA Technologies VT8237 SATA Controller", 321 via_sata_chip_map_7, 322 }, 323 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 324 0, 325 "VIA Technologies VT8237A SATA Controller", 326 via_sata_chip_map_7, 327 }, 328 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 329 0, 330 "VIA Technologies VT8237R SATA Controller", 331 via_sata_chip_map_0, 332 }, 333 { 0, 334 0, 335 NULL, 336 NULL 337 } 338 }; 339 340 static const struct pciide_product_desc * 341 viaide_lookup(pcireg_t id) 342 { 343 344 switch (PCI_VENDOR(id)) { 345 case PCI_VENDOR_VIATECH: 346 return (pciide_lookup_product(id, pciide_via_products)); 347 348 case PCI_VENDOR_AMD: 349 return (pciide_lookup_product(id, pciide_amd_products)); 350 351 case PCI_VENDOR_NVIDIA: 352 return (pciide_lookup_product(id, pciide_nvidia_products)); 353 } 354 return (NULL); 355 } 356 357 static int 358 viaide_match(device_t parent, cfdata_t match, void *aux) 359 { 360 struct pci_attach_args *pa = aux; 361 362 if (viaide_lookup(pa->pa_id) != NULL) 363 return (2); 364 return (0); 365 } 366 367 static void 368 viaide_attach(device_t parent, device_t self, void *aux) 369 { 370 struct pci_attach_args *pa = aux; 371 struct pciide_softc *sc = device_private(self); 372 const struct pciide_product_desc *pp; 373 374 sc->sc_wdcdev.sc_atac.atac_dev = self; 375 376 pp = viaide_lookup(pa->pa_id); 377 if (pp == NULL) 378 panic("viaide_attach"); 379 pciide_common_attach(sc, pa, pp); 380 381 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 382 aprint_error_dev(self, "couldn't establish power handler\n"); 383 } 384 385 static int 386 via_pcib_match(struct pci_attach_args *pa) 387 { 388 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 389 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 390 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 391 return (1); 392 return 0; 393 } 394 395 static bool 396 viaide_suspend(device_t dv PMF_FN_ARGS) 397 { 398 struct pciide_softc *sc = device_private(dv); 399 400 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 401 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 402 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 403 /* This two are VIA-only, but should be ignored by other devices. */ 404 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 405 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 406 407 return true; 408 } 409 410 static bool 411 viaide_resume(device_t dv PMF_FN_ARGS) 412 { 413 struct pciide_softc *sc = device_private(dv); 414 415 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 416 sc->sc_pm_reg[0]); 417 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 418 sc->sc_pm_reg[1]); 419 /* This two are VIA-only, but should be ignored by other devices. */ 420 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 421 sc->sc_pm_reg[2]); 422 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 423 sc->sc_pm_reg[3]); 424 425 return true; 426 } 427 428 static void 429 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 430 { 431 struct pciide_channel *cp; 432 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 433 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 434 int channel; 435 u_int32_t ideconf; 436 bus_size_t cmdsize, ctlsize; 437 pcireg_t pcib_id, pcib_class; 438 struct pci_attach_args pcib_pa; 439 440 if (pciide_chipen(sc, pa) == 0) 441 return; 442 443 switch (vendor) { 444 case PCI_VENDOR_VIATECH: 445 /* 446 * get a PCI tag for the ISA bridge. 447 */ 448 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 449 goto unknown; 450 pcib_id = pcib_pa.pa_id; 451 pcib_class = pcib_pa.pa_class; 452 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 453 "VIA Technologies "); 454 switch (PCI_PRODUCT(pcib_id)) { 455 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 456 aprint_normal("VT82C586 (Apollo VP) "); 457 if(PCI_REVISION(pcib_class) >= 0x02) { 458 aprint_normal("ATA33 controller\n"); 459 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 460 } else { 461 aprint_normal("controller\n"); 462 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 463 } 464 break; 465 case PCI_PRODUCT_VIATECH_VT82C596A: 466 aprint_normal("VT82C596A (Apollo Pro) "); 467 if (PCI_REVISION(pcib_class) >= 0x12) { 468 aprint_normal("ATA66 controller\n"); 469 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 470 } else { 471 aprint_normal("ATA33 controller\n"); 472 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 473 } 474 break; 475 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 476 aprint_normal("VT82C686A (Apollo KX133) "); 477 if (PCI_REVISION(pcib_class) >= 0x40) { 478 aprint_normal("ATA100 controller\n"); 479 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 480 } else { 481 aprint_normal("ATA66 controller\n"); 482 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 483 } 484 break; 485 case PCI_PRODUCT_VIATECH_VT8231: 486 aprint_normal("VT8231 ATA100 controller\n"); 487 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 488 break; 489 case PCI_PRODUCT_VIATECH_VT8233: 490 aprint_normal("VT8233 ATA100 controller\n"); 491 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 492 break; 493 case PCI_PRODUCT_VIATECH_VT8233A: 494 aprint_normal("VT8233A ATA133 controller\n"); 495 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 496 break; 497 case PCI_PRODUCT_VIATECH_VT8235: 498 aprint_normal("VT8235 ATA133 controller\n"); 499 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 500 break; 501 case PCI_PRODUCT_VIATECH_VT8237: 502 aprint_normal("VT8237 ATA133 controller\n"); 503 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 504 break; 505 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 506 aprint_normal("VT8237A ATA133 controller\n"); 507 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 508 break; 509 case PCI_PRODUCT_VIATECH_CX700_IDE: 510 aprint_normal("CX700 ATA133 controller\n"); 511 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 512 break; 513 default: 514 unknown: 515 aprint_normal("unknown VIA ATA controller\n"); 516 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 517 } 518 sc->sc_apo_regbase = APO_VIA_REGBASE; 519 break; 520 case PCI_VENDOR_AMD: 521 switch (sc->sc_pp->ide_product) { 522 case PCI_PRODUCT_AMD_PBC8111_IDE: 523 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 524 break; 525 case PCI_PRODUCT_AMD_CS5536_IDE: 526 case PCI_PRODUCT_AMD_PBC766_IDE: 527 case PCI_PRODUCT_AMD_PBC768_IDE: 528 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 529 break; 530 default: 531 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 532 } 533 sc->sc_apo_regbase = APO_AMD_REGBASE; 534 break; 535 case PCI_VENDOR_NVIDIA: 536 switch (sc->sc_pp->ide_product) { 537 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 538 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 539 break; 540 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 541 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 542 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 543 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 544 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 545 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 546 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 547 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 548 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 549 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 550 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 551 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 552 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 553 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 554 break; 555 } 556 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 557 break; 558 default: 559 panic("via_chip_map: unknown vendor"); 560 } 561 562 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 563 "bus-master DMA support present"); 564 pciide_mapreg_dma(sc, pa); 565 aprint_verbose("\n"); 566 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 567 if (sc->sc_dma_ok) { 568 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 569 sc->sc_wdcdev.irqack = pciide_irqack; 570 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 571 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 572 } 573 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 574 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 575 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 576 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 577 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 578 579 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 580 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 581 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 582 583 wdc_allocate_regs(&sc->sc_wdcdev); 584 585 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 586 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 587 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 588 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 589 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 590 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 591 DEBUG_PROBE); 592 593 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 594 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 595 channel++) { 596 cp = &sc->pciide_channels[channel]; 597 if (pciide_chansetup(sc, channel, interface) == 0) 598 continue; 599 600 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 601 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 602 "%s channel ignored (disabled)\n", cp->name); 603 cp->ata_channel.ch_flags |= ATACH_DISABLED; 604 continue; 605 } 606 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 607 pciide_pci_intr); 608 } 609 } 610 611 static void 612 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 613 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 614 int (*pci_intr)(void *)) 615 { 616 struct ata_channel *wdc_cp; 617 struct pciide_softc *sc; 618 prop_bool_t compat_nat_enable; 619 620 wdc_cp = &cp->ata_channel; 621 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 622 compat_nat_enable = prop_dictionary_get( 623 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 624 "use-compat-native-irq"); 625 626 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 627 /* native mode with irq 14/15 requested? */ 628 if (compat_nat_enable != NULL && 629 prop_bool_true(compat_nat_enable)) 630 vt8231_mapregs_native(pa, cp, cmdsizep, ctlsizep, 631 pci_intr); 632 else 633 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 634 pci_intr); 635 } else { 636 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 637 ctlsizep); 638 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 639 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 640 } 641 wdcattach(wdc_cp); 642 } 643 644 /* 645 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 646 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 647 * programmed to use a single native PCI irq alone. So we install an interrupt 648 * handler for each channel, as in compatibility mode. 649 */ 650 static void 651 vt8231_mapregs_native(struct pci_attach_args *pa, struct pciide_channel *cp, 652 bus_size_t *cmdsizep, bus_size_t *ctlsizep, int (*pci_intr)(void *)) 653 { 654 struct ata_channel *wdc_cp; 655 struct pciide_softc *sc; 656 657 wdc_cp = &cp->ata_channel; 658 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 659 660 /* XXX prevent pciide_mapregs_native from installing a handler */ 661 if (sc->sc_pci_ih == NULL) 662 sc->sc_pci_ih = (void *)~0; 663 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL); 664 665 /* interrupts are fixed to 14/15, as in compatibility mode */ 666 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 667 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 668 cp->ih = pciide_machdep_compat_intr_establish( 669 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 670 pci_intr, sc); 671 if (cp->ih == NULL) { 672 #endif 673 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 674 "no compatibility interrupt for " 675 "use by %s channel\n", cp->name); 676 wdc_cp->ch_flags |= ATACH_DISABLED; 677 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 678 } 679 sc->sc_pci_ih = cp->ih; /* XXX */ 680 #endif 681 } 682 } 683 684 static void 685 via_setup_channel(struct ata_channel *chp) 686 { 687 u_int32_t udmatim_reg, datatim_reg; 688 u_int8_t idedma_ctl; 689 int mode, drive, s; 690 struct ata_drive_datas *drvp; 691 struct atac_softc *atac = chp->ch_atac; 692 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 693 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 694 #ifndef PCIIDE_AMD756_ENABLEDMA 695 int rev = PCI_REVISION( 696 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 697 #endif 698 699 idedma_ctl = 0; 700 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 701 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 702 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 703 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 704 705 /* setup DMA if needed */ 706 pciide_channel_dma_setup(cp); 707 708 for (drive = 0; drive < 2; drive++) { 709 drvp = &chp->ch_drive[drive]; 710 /* If no drive, skip */ 711 if ((drvp->drive_flags & DRIVE) == 0) 712 continue; 713 /* add timing values, setup DMA if needed */ 714 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 715 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 716 mode = drvp->PIO_mode; 717 goto pio; 718 } 719 if ((atac->atac_cap & ATAC_CAP_UDMA) && 720 (drvp->drive_flags & DRIVE_UDMA)) { 721 /* use Ultra/DMA */ 722 s = splbio(); 723 drvp->drive_flags &= ~DRIVE_DMA; 724 splx(s); 725 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 726 APO_UDMA_EN_MTH(chp->ch_channel, drive); 727 switch (PCI_VENDOR(sc->sc_pci_id)) { 728 case PCI_VENDOR_VIATECH: 729 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 730 /* 8233a */ 731 udmatim_reg |= APO_UDMA_TIME( 732 chp->ch_channel, 733 drive, 734 via_udma133_tim[drvp->UDMA_mode]); 735 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 736 /* 686b */ 737 udmatim_reg |= APO_UDMA_TIME( 738 chp->ch_channel, 739 drive, 740 via_udma100_tim[drvp->UDMA_mode]); 741 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 742 /* 596b or 686a */ 743 udmatim_reg |= APO_UDMA_CLK66( 744 chp->ch_channel); 745 udmatim_reg |= APO_UDMA_TIME( 746 chp->ch_channel, 747 drive, 748 via_udma66_tim[drvp->UDMA_mode]); 749 } else { 750 /* 596a or 586b */ 751 udmatim_reg |= APO_UDMA_TIME( 752 chp->ch_channel, 753 drive, 754 via_udma33_tim[drvp->UDMA_mode]); 755 } 756 break; 757 case PCI_VENDOR_AMD: 758 case PCI_VENDOR_NVIDIA: 759 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 760 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 761 break; 762 } 763 /* can use PIO timings, MW DMA unused */ 764 mode = drvp->PIO_mode; 765 } else { 766 /* use Multiword DMA, but only if revision is OK */ 767 s = splbio(); 768 drvp->drive_flags &= ~DRIVE_UDMA; 769 splx(s); 770 #ifndef PCIIDE_AMD756_ENABLEDMA 771 /* 772 * The workaround doesn't seem to be necessary 773 * with all drives, so it can be disabled by 774 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 775 * triggered. 776 */ 777 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 778 sc->sc_pp->ide_product == 779 PCI_PRODUCT_AMD_PBC756_IDE && 780 AMD756_CHIPREV_DISABLEDMA(rev)) { 781 aprint_normal( 782 "%s:%d:%d: multi-word DMA disabled due " 783 "to chip revision\n", 784 device_xname( 785 sc->sc_wdcdev.sc_atac.atac_dev), 786 chp->ch_channel, drive); 787 mode = drvp->PIO_mode; 788 s = splbio(); 789 drvp->drive_flags &= ~DRIVE_DMA; 790 splx(s); 791 goto pio; 792 } 793 #endif 794 /* mode = min(pio, dma+2) */ 795 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 796 mode = drvp->PIO_mode; 797 else 798 mode = drvp->DMA_mode + 2; 799 } 800 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 801 802 pio: /* setup PIO mode */ 803 if (mode <= 2) { 804 drvp->DMA_mode = 0; 805 drvp->PIO_mode = 0; 806 mode = 0; 807 } else { 808 drvp->PIO_mode = mode; 809 drvp->DMA_mode = mode - 2; 810 } 811 datatim_reg |= 812 APO_DATATIM_PULSE(chp->ch_channel, drive, 813 apollo_pio_set[mode]) | 814 APO_DATATIM_RECOV(chp->ch_channel, drive, 815 apollo_pio_rec[mode]); 816 } 817 if (idedma_ctl != 0) { 818 /* Add software bits in status register */ 819 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 820 idedma_ctl); 821 } 822 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 823 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 824 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 825 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 826 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 827 } 828 829 static int 830 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 831 { 832 bus_size_t satasize; 833 int maptype, ret; 834 835 if (pciide_chipen(sc, pa) == 0) 836 return 0; 837 838 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 839 "bus-master DMA support present"); 840 pciide_mapreg_dma(sc, pa); 841 aprint_verbose("\n"); 842 843 if (sc->sc_dma_ok) { 844 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 845 sc->sc_wdcdev.irqack = pciide_irqack; 846 } 847 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 848 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 849 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 850 851 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 852 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 853 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 854 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 855 856 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 857 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 858 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 859 860 wdc_allocate_regs(&sc->sc_wdcdev); 861 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 862 PCI_MAPREG_START + 0x14); 863 switch(maptype) { 864 case PCI_MAPREG_TYPE_IO: 865 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 866 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 867 NULL, &satasize); 868 break; 869 case PCI_MAPREG_MEM_TYPE_32BIT: 870 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 871 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 872 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 873 NULL, &satasize); 874 break; 875 default: 876 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 877 "couldn't map sata regs, unsupported maptype (0x%x)\n", 878 maptype); 879 return 0; 880 } 881 if (ret != 0) { 882 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 883 "couldn't map sata regs\n"); 884 return 0; 885 } 886 return 1; 887 } 888 889 static void 890 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 891 int satareg_shift) 892 { 893 struct pciide_channel *cp; 894 struct ata_channel *wdc_cp; 895 struct wdc_regs *wdr; 896 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 897 int channel; 898 bus_size_t cmdsize, ctlsize; 899 900 if (via_sata_chip_map_common(sc, pa) == 0) 901 return; 902 903 if (interface == 0) { 904 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 905 DEBUG_PROBE); 906 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 907 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 908 } 909 910 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 911 channel++) { 912 cp = &sc->pciide_channels[channel]; 913 if (pciide_chansetup(sc, channel, interface) == 0) 914 continue; 915 wdc_cp = &cp->ata_channel; 916 wdr = CHAN_TO_WDC_REGS(wdc_cp); 917 wdr->sata_iot = sc->sc_ba5_st; 918 wdr->sata_baseioh = sc->sc_ba5_sh; 919 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 920 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 921 &wdr->sata_status) != 0) { 922 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 923 "couldn't map channel %d sata_status regs\n", 924 wdc_cp->ch_channel); 925 continue; 926 } 927 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 928 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 929 &wdr->sata_error) != 0) { 930 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 931 "couldn't map channel %d sata_error regs\n", 932 wdc_cp->ch_channel); 933 continue; 934 } 935 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 936 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 937 &wdr->sata_control) != 0) { 938 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 939 "couldn't map channel %d sata_control regs\n", 940 wdc_cp->ch_channel); 941 continue; 942 } 943 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 944 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 945 pciide_pci_intr); 946 } 947 } 948 949 static void 950 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 951 { 952 via_sata_chip_map(sc, pa, 0); 953 } 954 955 static void 956 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 957 { 958 via_sata_chip_map(sc, pa, 6); 959 } 960 961 static void 962 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 963 { 964 via_sata_chip_map(sc, pa, 7); 965 } 966 967 static void 968 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 969 { 970 struct pciide_channel *cp; 971 struct ata_channel *wdc_cp; 972 struct wdc_regs *wdr; 973 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 974 int channel; 975 bus_size_t cmdsize; 976 pci_intr_handle_t intrhandle; 977 const char *intrstr; 978 int i; 979 980 if (via_sata_chip_map_common(sc, pa) == 0) 981 return; 982 983 if (interface == 0) { 984 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 985 DEBUG_PROBE); 986 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 987 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 988 } 989 990 if (pci_intr_map(pa, &intrhandle) != 0) { 991 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 992 "couldn't map native-PCI interrupt\n"); 993 return; 994 } 995 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 996 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 997 intrhandle, IPL_BIO, pciide_pci_intr, sc); 998 if (sc->sc_pci_ih == NULL) { 999 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1000 "couldn't establish native-PCI interrupt"); 1001 if (intrstr != NULL) 1002 aprint_error(" at %s", intrstr); 1003 aprint_error("\n"); 1004 return; 1005 } 1006 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1007 "using %s for native-PCI interrupt\n", 1008 intrstr ? intrstr : "unknown interrupt"); 1009 1010 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1011 channel++) { 1012 cp = &sc->pciide_channels[channel]; 1013 if (pciide_chansetup(sc, channel, interface) == 0) 1014 continue; 1015 cp->ata_channel.ch_ndrive = 1; 1016 wdc_cp = &cp->ata_channel; 1017 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1018 1019 wdr->sata_iot = sc->sc_ba5_st; 1020 wdr->sata_baseioh = sc->sc_ba5_sh; 1021 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1022 (wdc_cp->ch_channel << 6) + 0x0, 1, 1023 &wdr->sata_status) != 0) { 1024 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1025 "couldn't map channel %d sata_status regs\n", 1026 wdc_cp->ch_channel); 1027 continue; 1028 } 1029 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1030 (wdc_cp->ch_channel << 6) + 0x4, 1, 1031 &wdr->sata_error) != 0) { 1032 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1033 "couldn't map channel %d sata_error regs\n", 1034 wdc_cp->ch_channel); 1035 continue; 1036 } 1037 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1038 (wdc_cp->ch_channel << 6) + 0x8, 1, 1039 &wdr->sata_control) != 0) { 1040 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1041 "couldn't map channel %d sata_control regs\n", 1042 wdc_cp->ch_channel); 1043 continue; 1044 } 1045 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1046 1047 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 1048 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1049 NULL, &cmdsize) != 0) { 1050 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1051 "couldn't map %s channel regs\n", cp->name); 1052 } 1053 wdr->ctl_iot = wdr->cmd_iot; 1054 for (i = 0; i < WDC_NREG; i++) { 1055 if (bus_space_subregion(wdr->cmd_iot, 1056 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1057 &wdr->cmd_iohs[i]) != 0) { 1058 aprint_error_dev( 1059 sc->sc_wdcdev.sc_atac.atac_dev, 1060 "couldn't subregion %s " 1061 "channel cmd regs\n", cp->name); 1062 return; 1063 } 1064 } 1065 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1066 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1067 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1068 "couldn't map channel %d ctl regs\n", channel); 1069 return; 1070 } 1071 wdc_init_shadow_regs(wdc_cp); 1072 wdcattach(wdc_cp); 1073 } 1074 } 1075
Indexes created Fri Oct 17 03:10:13 GMT 2025