viaide.c revision 1.56.2.1
1 /* $NetBSD: viaide.c,v 1.56.2.1 2008/10/19 22:16:40 haad Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.56.2.1 2008/10/19 22:16:40 haad Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 48 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *)); 49 static void via_mapregs_compat_native(struct pci_attach_args *, 50 struct pciide_channel *, bus_size_t *, bus_size_t *); 51 static int via_sata_chip_map_common(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map(struct pciide_softc *, 54 struct pci_attach_args *, int); 55 static void via_sata_chip_map_0(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_6(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_sata_chip_map_7(struct pciide_softc *, 60 struct pci_attach_args *); 61 static void via_sata_chip_map_new(struct pciide_softc *, 62 struct pci_attach_args *); 63 static void via_setup_channel(struct ata_channel *); 64 65 static int viaide_match(device_t, cfdata_t, void *); 66 static void viaide_attach(device_t, device_t, void *); 67 static const struct pciide_product_desc * 68 viaide_lookup(pcireg_t); 69 static bool viaide_suspend(device_t PMF_FN_PROTO); 70 static bool viaide_resume(device_t PMF_FN_PROTO); 71 72 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 73 viaide_match, viaide_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_amd_products[] = { 76 { PCI_PRODUCT_AMD_PBC756_IDE, 77 0, 78 "Advanced Micro Devices AMD756 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC766_IDE, 82 0, 83 "Advanced Micro Devices AMD766 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC768_IDE, 87 0, 88 "Advanced Micro Devices AMD768 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_PBC8111_IDE, 92 0, 93 "Advanced Micro Devices AMD8111 IDE Controller", 94 via_chip_map 95 }, 96 { PCI_PRODUCT_AMD_CS5536_IDE, 97 0, 98 "Advanced Micro Devices CS5536 IDE Controller", 99 via_chip_map 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static const struct pciide_product_desc pciide_nvidia_products[] = { 109 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 110 0, 111 "NVIDIA nForce IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 115 0, 116 "NVIDIA nForce2 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 120 0, 121 "NVIDIA nForce2 Ultra 400 IDE Controller", 122 via_chip_map 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 125 0, 126 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 127 via_sata_chip_map_6 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 130 0, 131 "NVIDIA nForce3 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 135 0, 136 "NVIDIA nForce3 250 IDE Controller", 137 via_chip_map 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 145 0, 146 "NVIDIA nForce3 250 Serial ATA Controller", 147 via_sata_chip_map_6 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 150 0, 151 "NVIDIA nForce4 IDE Controller", 152 via_chip_map 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 160 0, 161 "NVIDIA nForce4 Serial ATA Controller", 162 via_sata_chip_map_6 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 165 0, 166 "NVIDIA nForce430 IDE Controller", 167 via_chip_map 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 175 0, 176 "NVIDIA nForce430 Serial ATA Controller", 177 via_sata_chip_map_6 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 180 0, 181 "NVIDIA MCP04 IDE Controller", 182 via_chip_map 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 190 0, 191 "NVIDIA MCP04 Serial ATA Controller", 192 via_sata_chip_map_6 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 195 0, 196 "NVIDIA MCP55 IDE Controller", 197 via_chip_map 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 205 0, 206 "NVIDIA MCP55 Serial ATA Controller", 207 via_sata_chip_map_6 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 210 0, 211 "NVIDIA MCP61 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 215 0, 216 "NVIDIA MCP65 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 220 0, 221 "NVIDIA MCP73 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 225 0, 226 "NVIDIA MCP77 IDE Controller", 227 via_chip_map 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 240 0, 241 "NVIDIA MCP61 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 260 0, 261 "NVIDIA MCP65 Serial ATA Controller", 262 via_sata_chip_map_6 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 265 0, 266 "NVIDIA MCP67 IDE Controller", 267 via_chip_map, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 285 0, 286 "NVIDIA MCP67 Serial ATA Controller", 287 via_sata_chip_map_6, 288 }, 289 { 0, 290 0, 291 NULL, 292 NULL 293 } 294 }; 295 296 static const struct pciide_product_desc pciide_via_products[] = { 297 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 303 0, 304 NULL, 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 313 0, 314 NULL, 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VT6421_RAID, 318 0, 319 "VIA Technologies VT6421 Serial RAID Controller", 320 via_sata_chip_map_new, 321 }, 322 { PCI_PRODUCT_VIATECH_VT8237_SATA, 323 0, 324 "VIA Technologies VT8237 SATA Controller", 325 via_sata_chip_map_7, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 328 0, 329 "VIA Technologies VT8237A SATA Controller", 330 via_sata_chip_map_7, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 333 0, 334 "VIA Technologies VT8237R SATA Controller", 335 via_sata_chip_map_0, 336 }, 337 { 0, 338 0, 339 NULL, 340 NULL 341 } 342 }; 343 344 static const struct pciide_product_desc * 345 viaide_lookup(pcireg_t id) 346 { 347 348 switch (PCI_VENDOR(id)) { 349 case PCI_VENDOR_VIATECH: 350 return (pciide_lookup_product(id, pciide_via_products)); 351 352 case PCI_VENDOR_AMD: 353 return (pciide_lookup_product(id, pciide_amd_products)); 354 355 case PCI_VENDOR_NVIDIA: 356 return (pciide_lookup_product(id, pciide_nvidia_products)); 357 } 358 return (NULL); 359 } 360 361 static int 362 viaide_match(device_t parent, cfdata_t match, void *aux) 363 { 364 struct pci_attach_args *pa = aux; 365 366 if (viaide_lookup(pa->pa_id) != NULL) 367 return (2); 368 return (0); 369 } 370 371 static void 372 viaide_attach(device_t parent, device_t self, void *aux) 373 { 374 struct pci_attach_args *pa = aux; 375 struct pciide_softc *sc = device_private(self); 376 const struct pciide_product_desc *pp; 377 378 sc->sc_wdcdev.sc_atac.atac_dev = self; 379 380 pp = viaide_lookup(pa->pa_id); 381 if (pp == NULL) 382 panic("viaide_attach"); 383 pciide_common_attach(sc, pa, pp); 384 385 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 386 aprint_error_dev(self, "couldn't establish power handler\n"); 387 } 388 389 static int 390 via_pcib_match(struct pci_attach_args *pa) 391 { 392 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 393 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 394 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 395 return (1); 396 return 0; 397 } 398 399 static bool 400 viaide_suspend(device_t dv PMF_FN_ARGS) 401 { 402 struct pciide_softc *sc = device_private(dv); 403 404 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 405 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 406 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 407 /* This two are VIA-only, but should be ignored by other devices. */ 408 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 409 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 410 411 return true; 412 } 413 414 static bool 415 viaide_resume(device_t dv PMF_FN_ARGS) 416 { 417 struct pciide_softc *sc = device_private(dv); 418 419 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 420 sc->sc_pm_reg[0]); 421 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 422 sc->sc_pm_reg[1]); 423 /* This two are VIA-only, but should be ignored by other devices. */ 424 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 425 sc->sc_pm_reg[2]); 426 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 427 sc->sc_pm_reg[3]); 428 429 return true; 430 } 431 432 static void 433 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 434 { 435 struct pciide_channel *cp; 436 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 437 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 438 int channel; 439 u_int32_t ideconf; 440 bus_size_t cmdsize, ctlsize; 441 pcireg_t pcib_id, pcib_class; 442 struct pci_attach_args pcib_pa; 443 444 if (pciide_chipen(sc, pa) == 0) 445 return; 446 447 switch (vendor) { 448 case PCI_VENDOR_VIATECH: 449 /* 450 * get a PCI tag for the ISA bridge. 451 */ 452 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 453 goto unknown; 454 pcib_id = pcib_pa.pa_id; 455 pcib_class = pcib_pa.pa_class; 456 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 457 "VIA Technologies "); 458 switch (PCI_PRODUCT(pcib_id)) { 459 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 460 aprint_normal("VT82C586 (Apollo VP) "); 461 if(PCI_REVISION(pcib_class) >= 0x02) { 462 aprint_normal("ATA33 controller\n"); 463 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 464 } else { 465 aprint_normal("controller\n"); 466 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 467 } 468 break; 469 case PCI_PRODUCT_VIATECH_VT82C596A: 470 aprint_normal("VT82C596A (Apollo Pro) "); 471 if (PCI_REVISION(pcib_class) >= 0x12) { 472 aprint_normal("ATA66 controller\n"); 473 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 474 } else { 475 aprint_normal("ATA33 controller\n"); 476 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 477 } 478 break; 479 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 480 aprint_normal("VT82C686A (Apollo KX133) "); 481 if (PCI_REVISION(pcib_class) >= 0x40) { 482 aprint_normal("ATA100 controller\n"); 483 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 484 } else { 485 aprint_normal("ATA66 controller\n"); 486 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 487 } 488 break; 489 case PCI_PRODUCT_VIATECH_VT8231: 490 aprint_normal("VT8231 ATA100 controller\n"); 491 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 492 break; 493 case PCI_PRODUCT_VIATECH_VT8233: 494 aprint_normal("VT8233 ATA100 controller\n"); 495 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 496 break; 497 case PCI_PRODUCT_VIATECH_VT8233A: 498 aprint_normal("VT8233A ATA133 controller\n"); 499 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 500 break; 501 case PCI_PRODUCT_VIATECH_VT8235: 502 aprint_normal("VT8235 ATA133 controller\n"); 503 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 504 break; 505 case PCI_PRODUCT_VIATECH_VT8237: 506 aprint_normal("VT8237 ATA133 controller\n"); 507 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 508 break; 509 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 510 aprint_normal("VT8237A ATA133 controller\n"); 511 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 512 break; 513 case PCI_PRODUCT_VIATECH_CX700_IDE: 514 aprint_normal("CX700 ATA133 controller\n"); 515 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 516 break; 517 case PCI_PRODUCT_VIATECH_CX700M2_IDE: 518 aprint_normal("CX700M2/VX700 ATA133 controller\n"); 519 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 520 break; 521 default: 522 unknown: 523 aprint_normal("unknown VIA ATA controller\n"); 524 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 525 } 526 sc->sc_apo_regbase = APO_VIA_REGBASE; 527 break; 528 case PCI_VENDOR_AMD: 529 switch (sc->sc_pp->ide_product) { 530 case PCI_PRODUCT_AMD_PBC8111_IDE: 531 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 532 break; 533 case PCI_PRODUCT_AMD_CS5536_IDE: 534 case PCI_PRODUCT_AMD_PBC766_IDE: 535 case PCI_PRODUCT_AMD_PBC768_IDE: 536 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 537 break; 538 default: 539 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 540 } 541 sc->sc_apo_regbase = APO_AMD_REGBASE; 542 break; 543 case PCI_VENDOR_NVIDIA: 544 switch (sc->sc_pp->ide_product) { 545 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 546 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 547 break; 548 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 549 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 550 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 551 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 552 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 553 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 554 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 555 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 556 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 557 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 558 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 559 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 560 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 561 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 562 break; 563 } 564 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 565 break; 566 default: 567 panic("via_chip_map: unknown vendor"); 568 } 569 570 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 571 "bus-master DMA support present"); 572 pciide_mapreg_dma(sc, pa); 573 aprint_verbose("\n"); 574 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 575 if (sc->sc_dma_ok) { 576 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 577 sc->sc_wdcdev.irqack = pciide_irqack; 578 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 579 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 580 } 581 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 582 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 583 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 584 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 585 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 586 587 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 588 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 589 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 590 591 wdc_allocate_regs(&sc->sc_wdcdev); 592 593 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 594 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 595 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 596 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 597 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 598 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 599 DEBUG_PROBE); 600 601 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 602 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 603 channel++) { 604 cp = &sc->pciide_channels[channel]; 605 if (pciide_chansetup(sc, channel, interface) == 0) 606 continue; 607 608 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 609 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 610 "%s channel ignored (disabled)\n", cp->name); 611 cp->ata_channel.ch_flags |= ATACH_DISABLED; 612 continue; 613 } 614 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 615 pciide_pci_intr); 616 } 617 } 618 619 static void 620 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 621 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 622 int (*pci_intr)(void *)) 623 { 624 struct ata_channel *wdc_cp; 625 struct pciide_softc *sc; 626 prop_bool_t compat_nat_enable; 627 628 wdc_cp = &cp->ata_channel; 629 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 630 compat_nat_enable = prop_dictionary_get( 631 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 632 "use-compat-native-irq"); 633 634 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 635 /* native mode with irq 14/15 requested? */ 636 if (compat_nat_enable != NULL && 637 prop_bool_true(compat_nat_enable)) 638 via_mapregs_compat_native(pa, cp, cmdsizep, ctlsizep); 639 else 640 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 641 pci_intr); 642 } else { 643 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 644 ctlsizep); 645 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 646 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 647 } 648 wdcattach(wdc_cp); 649 } 650 651 /* 652 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 653 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 654 * programmed to use a single native PCI irq alone. So we install an interrupt 655 * handler for each channel, as in compatibility mode. 656 */ 657 static void 658 via_mapregs_compat_native(struct pci_attach_args *pa, 659 struct pciide_channel *cp, bus_size_t *cmdsizep, bus_size_t *ctlsizep) 660 { 661 struct ata_channel *wdc_cp; 662 struct pciide_softc *sc; 663 664 wdc_cp = &cp->ata_channel; 665 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 666 667 /* XXX prevent pciide_mapregs_native from installing a handler */ 668 if (sc->sc_pci_ih == NULL) 669 sc->sc_pci_ih = (void *)~0; 670 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL); 671 672 /* interrupts are fixed to 14/15, as in compatibility mode */ 673 cp->compat = 1; 674 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 675 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 676 cp->ih = pciide_machdep_compat_intr_establish( 677 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 678 pciide_compat_intr, cp); 679 if (cp->ih == NULL) { 680 #endif 681 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 682 "no compatibility interrupt for " 683 "use by %s channel\n", cp->name); 684 wdc_cp->ch_flags |= ATACH_DISABLED; 685 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 686 } 687 sc->sc_pci_ih = cp->ih; /* XXX */ 688 #endif 689 } 690 } 691 692 static void 693 via_setup_channel(struct ata_channel *chp) 694 { 695 u_int32_t udmatim_reg, datatim_reg; 696 u_int8_t idedma_ctl; 697 int mode, drive, s; 698 struct ata_drive_datas *drvp; 699 struct atac_softc *atac = chp->ch_atac; 700 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 701 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 702 #ifndef PCIIDE_AMD756_ENABLEDMA 703 int rev = PCI_REVISION( 704 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 705 #endif 706 707 idedma_ctl = 0; 708 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 709 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 710 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 711 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 712 713 /* setup DMA if needed */ 714 pciide_channel_dma_setup(cp); 715 716 for (drive = 0; drive < 2; drive++) { 717 drvp = &chp->ch_drive[drive]; 718 /* If no drive, skip */ 719 if ((drvp->drive_flags & DRIVE) == 0) 720 continue; 721 /* add timing values, setup DMA if needed */ 722 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 723 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 724 mode = drvp->PIO_mode; 725 goto pio; 726 } 727 if ((atac->atac_cap & ATAC_CAP_UDMA) && 728 (drvp->drive_flags & DRIVE_UDMA)) { 729 /* use Ultra/DMA */ 730 s = splbio(); 731 drvp->drive_flags &= ~DRIVE_DMA; 732 splx(s); 733 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 734 APO_UDMA_EN_MTH(chp->ch_channel, drive); 735 switch (PCI_VENDOR(sc->sc_pci_id)) { 736 case PCI_VENDOR_VIATECH: 737 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 738 /* 8233a */ 739 udmatim_reg |= APO_UDMA_TIME( 740 chp->ch_channel, 741 drive, 742 via_udma133_tim[drvp->UDMA_mode]); 743 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 744 /* 686b */ 745 udmatim_reg |= APO_UDMA_TIME( 746 chp->ch_channel, 747 drive, 748 via_udma100_tim[drvp->UDMA_mode]); 749 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 750 /* 596b or 686a */ 751 udmatim_reg |= APO_UDMA_CLK66( 752 chp->ch_channel); 753 udmatim_reg |= APO_UDMA_TIME( 754 chp->ch_channel, 755 drive, 756 via_udma66_tim[drvp->UDMA_mode]); 757 } else { 758 /* 596a or 586b */ 759 udmatim_reg |= APO_UDMA_TIME( 760 chp->ch_channel, 761 drive, 762 via_udma33_tim[drvp->UDMA_mode]); 763 } 764 break; 765 case PCI_VENDOR_AMD: 766 case PCI_VENDOR_NVIDIA: 767 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 768 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 769 break; 770 } 771 /* can use PIO timings, MW DMA unused */ 772 mode = drvp->PIO_mode; 773 } else { 774 /* use Multiword DMA, but only if revision is OK */ 775 s = splbio(); 776 drvp->drive_flags &= ~DRIVE_UDMA; 777 splx(s); 778 #ifndef PCIIDE_AMD756_ENABLEDMA 779 /* 780 * The workaround doesn't seem to be necessary 781 * with all drives, so it can be disabled by 782 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 783 * triggered. 784 */ 785 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 786 sc->sc_pp->ide_product == 787 PCI_PRODUCT_AMD_PBC756_IDE && 788 AMD756_CHIPREV_DISABLEDMA(rev)) { 789 aprint_normal( 790 "%s:%d:%d: multi-word DMA disabled due " 791 "to chip revision\n", 792 device_xname( 793 sc->sc_wdcdev.sc_atac.atac_dev), 794 chp->ch_channel, drive); 795 mode = drvp->PIO_mode; 796 s = splbio(); 797 drvp->drive_flags &= ~DRIVE_DMA; 798 splx(s); 799 goto pio; 800 } 801 #endif 802 /* mode = min(pio, dma+2) */ 803 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 804 mode = drvp->PIO_mode; 805 else 806 mode = drvp->DMA_mode + 2; 807 } 808 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 809 810 pio: /* setup PIO mode */ 811 if (mode <= 2) { 812 drvp->DMA_mode = 0; 813 drvp->PIO_mode = 0; 814 mode = 0; 815 } else { 816 drvp->PIO_mode = mode; 817 drvp->DMA_mode = mode - 2; 818 } 819 datatim_reg |= 820 APO_DATATIM_PULSE(chp->ch_channel, drive, 821 apollo_pio_set[mode]) | 822 APO_DATATIM_RECOV(chp->ch_channel, drive, 823 apollo_pio_rec[mode]); 824 } 825 if (idedma_ctl != 0) { 826 /* Add software bits in status register */ 827 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 828 idedma_ctl); 829 } 830 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 831 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 832 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 833 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 834 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 835 } 836 837 static int 838 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 839 { 840 bus_size_t satasize; 841 int maptype, ret; 842 843 if (pciide_chipen(sc, pa) == 0) 844 return 0; 845 846 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 847 "bus-master DMA support present"); 848 pciide_mapreg_dma(sc, pa); 849 aprint_verbose("\n"); 850 851 if (sc->sc_dma_ok) { 852 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 853 sc->sc_wdcdev.irqack = pciide_irqack; 854 } 855 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 856 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 857 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 858 859 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 860 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 861 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 862 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 863 864 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 865 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 866 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 867 868 wdc_allocate_regs(&sc->sc_wdcdev); 869 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 870 PCI_MAPREG_START + 0x14); 871 switch(maptype) { 872 case PCI_MAPREG_TYPE_IO: 873 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 874 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 875 NULL, &satasize); 876 break; 877 case PCI_MAPREG_MEM_TYPE_32BIT: 878 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 879 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 880 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 881 NULL, &satasize); 882 break; 883 default: 884 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 885 "couldn't map sata regs, unsupported maptype (0x%x)\n", 886 maptype); 887 return 0; 888 } 889 if (ret != 0) { 890 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 891 "couldn't map sata regs\n"); 892 return 0; 893 } 894 return 1; 895 } 896 897 static void 898 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 899 int satareg_shift) 900 { 901 struct pciide_channel *cp; 902 struct ata_channel *wdc_cp; 903 struct wdc_regs *wdr; 904 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 905 int channel; 906 bus_size_t cmdsize, ctlsize; 907 908 if (via_sata_chip_map_common(sc, pa) == 0) 909 return; 910 911 if (interface == 0) { 912 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 913 DEBUG_PROBE); 914 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 915 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 916 } 917 918 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 919 channel++) { 920 cp = &sc->pciide_channels[channel]; 921 if (pciide_chansetup(sc, channel, interface) == 0) 922 continue; 923 wdc_cp = &cp->ata_channel; 924 wdr = CHAN_TO_WDC_REGS(wdc_cp); 925 wdr->sata_iot = sc->sc_ba5_st; 926 wdr->sata_baseioh = sc->sc_ba5_sh; 927 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 928 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 929 &wdr->sata_status) != 0) { 930 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 931 "couldn't map channel %d sata_status regs\n", 932 wdc_cp->ch_channel); 933 continue; 934 } 935 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 936 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 937 &wdr->sata_error) != 0) { 938 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 939 "couldn't map channel %d sata_error regs\n", 940 wdc_cp->ch_channel); 941 continue; 942 } 943 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 944 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 945 &wdr->sata_control) != 0) { 946 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 947 "couldn't map channel %d sata_control regs\n", 948 wdc_cp->ch_channel); 949 continue; 950 } 951 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 952 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 953 pciide_pci_intr); 954 } 955 } 956 957 static void 958 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 959 { 960 via_sata_chip_map(sc, pa, 0); 961 } 962 963 static void 964 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 965 { 966 via_sata_chip_map(sc, pa, 6); 967 } 968 969 static void 970 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 971 { 972 via_sata_chip_map(sc, pa, 7); 973 } 974 975 static void 976 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 977 { 978 struct pciide_channel *cp; 979 struct ata_channel *wdc_cp; 980 struct wdc_regs *wdr; 981 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 982 int channel; 983 bus_size_t cmdsize; 984 pci_intr_handle_t intrhandle; 985 const char *intrstr; 986 int i; 987 988 if (via_sata_chip_map_common(sc, pa) == 0) 989 return; 990 991 if (interface == 0) { 992 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 993 DEBUG_PROBE); 994 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 995 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 996 } 997 998 if (pci_intr_map(pa, &intrhandle) != 0) { 999 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1000 "couldn't map native-PCI interrupt\n"); 1001 return; 1002 } 1003 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1004 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1005 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1006 if (sc->sc_pci_ih == NULL) { 1007 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1008 "couldn't establish native-PCI interrupt"); 1009 if (intrstr != NULL) 1010 aprint_error(" at %s", intrstr); 1011 aprint_error("\n"); 1012 return; 1013 } 1014 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1015 "using %s for native-PCI interrupt\n", 1016 intrstr ? intrstr : "unknown interrupt"); 1017 1018 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1019 channel++) { 1020 cp = &sc->pciide_channels[channel]; 1021 if (pciide_chansetup(sc, channel, interface) == 0) 1022 continue; 1023 cp->ata_channel.ch_ndrive = 1; 1024 wdc_cp = &cp->ata_channel; 1025 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1026 1027 wdr->sata_iot = sc->sc_ba5_st; 1028 wdr->sata_baseioh = sc->sc_ba5_sh; 1029 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1030 (wdc_cp->ch_channel << 6) + 0x0, 1, 1031 &wdr->sata_status) != 0) { 1032 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1033 "couldn't map channel %d sata_status regs\n", 1034 wdc_cp->ch_channel); 1035 continue; 1036 } 1037 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1038 (wdc_cp->ch_channel << 6) + 0x4, 1, 1039 &wdr->sata_error) != 0) { 1040 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1041 "couldn't map channel %d sata_error regs\n", 1042 wdc_cp->ch_channel); 1043 continue; 1044 } 1045 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1046 (wdc_cp->ch_channel << 6) + 0x8, 1, 1047 &wdr->sata_control) != 0) { 1048 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1049 "couldn't map channel %d sata_control regs\n", 1050 wdc_cp->ch_channel); 1051 continue; 1052 } 1053 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1054 1055 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 1056 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1057 NULL, &cmdsize) != 0) { 1058 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1059 "couldn't map %s channel regs\n", cp->name); 1060 } 1061 wdr->ctl_iot = wdr->cmd_iot; 1062 for (i = 0; i < WDC_NREG; i++) { 1063 if (bus_space_subregion(wdr->cmd_iot, 1064 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1065 &wdr->cmd_iohs[i]) != 0) { 1066 aprint_error_dev( 1067 sc->sc_wdcdev.sc_atac.atac_dev, 1068 "couldn't subregion %s " 1069 "channel cmd regs\n", cp->name); 1070 return; 1071 } 1072 } 1073 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1074 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1075 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1076 "couldn't map channel %d ctl regs\n", channel); 1077 return; 1078 } 1079 wdc_init_shadow_regs(wdc_cp); 1080 wdcattach(wdc_cp); 1081 } 1082 } 1083
Indexes created Wed Oct 22 13:09:56 GMT 2025