viaide.c revision 1.57.10.1
1 /* $NetBSD: viaide.c,v 1.57.10.1 2010/04/21 00:27:49 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.57.10.1 2010/04/21 00:27:49 matt Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 48 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *)); 49 static void via_mapregs_compat_native(struct pci_attach_args *, 50 struct pciide_channel *, bus_size_t *, bus_size_t *); 51 static int via_sata_chip_map_common(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map(struct pciide_softc *, 54 struct pci_attach_args *, int); 55 static void via_sata_chip_map_0(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_6(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_sata_chip_map_7(struct pciide_softc *, 60 struct pci_attach_args *); 61 static void via_sata_chip_map_new(struct pciide_softc *, 62 struct pci_attach_args *); 63 static void via_setup_channel(struct ata_channel *); 64 65 static int viaide_match(device_t, cfdata_t, void *); 66 static void viaide_attach(device_t, device_t, void *); 67 static const struct pciide_product_desc * 68 viaide_lookup(pcireg_t); 69 static bool viaide_suspend(device_t PMF_FN_PROTO); 70 static bool viaide_resume(device_t PMF_FN_PROTO); 71 72 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 73 viaide_match, viaide_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_amd_products[] = { 76 { PCI_PRODUCT_AMD_PBC756_IDE, 77 0, 78 "Advanced Micro Devices AMD756 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC766_IDE, 82 0, 83 "Advanced Micro Devices AMD766 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC768_IDE, 87 0, 88 "Advanced Micro Devices AMD768 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_PBC8111_IDE, 92 0, 93 "Advanced Micro Devices AMD8111 IDE Controller", 94 via_chip_map 95 }, 96 { PCI_PRODUCT_AMD_CS5536_IDE, 97 0, 98 "Advanced Micro Devices CS5536 IDE Controller", 99 via_chip_map 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static const struct pciide_product_desc pciide_nvidia_products[] = { 109 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 110 0, 111 "NVIDIA nForce IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 115 0, 116 "NVIDIA nForce2 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 120 0, 121 "NVIDIA nForce2 Ultra 400 IDE Controller", 122 via_chip_map 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 125 0, 126 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 127 via_sata_chip_map_6 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 130 0, 131 "NVIDIA nForce3 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 135 0, 136 "NVIDIA nForce3 250 IDE Controller", 137 via_chip_map 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 145 0, 146 "NVIDIA nForce3 250 Serial ATA Controller", 147 via_sata_chip_map_6 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 150 0, 151 "NVIDIA nForce4 IDE Controller", 152 via_chip_map 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 160 0, 161 "NVIDIA nForce4 Serial ATA Controller", 162 via_sata_chip_map_6 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 165 0, 166 "NVIDIA nForce430 IDE Controller", 167 via_chip_map 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 175 0, 176 "NVIDIA nForce430 Serial ATA Controller", 177 via_sata_chip_map_6 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 180 0, 181 "NVIDIA MCP04 IDE Controller", 182 via_chip_map 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 190 0, 191 "NVIDIA MCP04 Serial ATA Controller", 192 via_sata_chip_map_6 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 195 0, 196 "NVIDIA MCP55 IDE Controller", 197 via_chip_map 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 205 0, 206 "NVIDIA MCP55 Serial ATA Controller", 207 via_sata_chip_map_6 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 210 0, 211 "NVIDIA MCP61 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 215 0, 216 "NVIDIA MCP65 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 220 0, 221 "NVIDIA MCP73 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 225 0, 226 "NVIDIA MCP77 IDE Controller", 227 via_chip_map 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 240 0, 241 "NVIDIA MCP61 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 260 0, 261 "NVIDIA MCP65 Serial ATA Controller", 262 via_sata_chip_map_6 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 265 0, 266 "NVIDIA MCP67 IDE Controller", 267 via_chip_map, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 285 0, 286 "NVIDIA MCP67 Serial ATA Controller", 287 via_sata_chip_map_6, 288 }, 289 { 0, 290 0, 291 NULL, 292 NULL 293 } 294 }; 295 296 static const struct pciide_product_desc pciide_via_products[] = { 297 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 303 0, 304 NULL, 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 313 0, 314 NULL, 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VT6421_RAID, 318 0, 319 "VIA Technologies VT6421 Serial RAID Controller", 320 via_sata_chip_map_new, 321 }, 322 { PCI_PRODUCT_VIATECH_VT8237_SATA, 323 0, 324 "VIA Technologies VT8237 SATA Controller", 325 via_sata_chip_map_7, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 328 0, 329 "VIA Technologies VT8237A SATA Controller", 330 via_sata_chip_map_7, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 333 0, 334 "VIA Technologies VT8237A (5337) SATA Controller", 335 via_sata_chip_map_7, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 338 0, 339 "VIA Technologies VT8237R SATA Controller", 340 via_sata_chip_map_0, 341 }, 342 { 0, 343 0, 344 NULL, 345 NULL 346 } 347 }; 348 349 static const struct pciide_product_desc * 350 viaide_lookup(pcireg_t id) 351 { 352 353 switch (PCI_VENDOR(id)) { 354 case PCI_VENDOR_VIATECH: 355 return (pciide_lookup_product(id, pciide_via_products)); 356 357 case PCI_VENDOR_AMD: 358 return (pciide_lookup_product(id, pciide_amd_products)); 359 360 case PCI_VENDOR_NVIDIA: 361 return (pciide_lookup_product(id, pciide_nvidia_products)); 362 } 363 return (NULL); 364 } 365 366 static int 367 viaide_match(device_t parent, cfdata_t match, void *aux) 368 { 369 struct pci_attach_args *pa = aux; 370 371 if (viaide_lookup(pa->pa_id) != NULL) 372 return (2); 373 return (0); 374 } 375 376 static void 377 viaide_attach(device_t parent, device_t self, void *aux) 378 { 379 struct pci_attach_args *pa = aux; 380 struct pciide_softc *sc = device_private(self); 381 const struct pciide_product_desc *pp; 382 383 sc->sc_wdcdev.sc_atac.atac_dev = self; 384 385 pp = viaide_lookup(pa->pa_id); 386 if (pp == NULL) 387 panic("viaide_attach"); 388 pciide_common_attach(sc, pa, pp); 389 390 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 391 aprint_error_dev(self, "couldn't establish power handler\n"); 392 } 393 394 static int 395 via_pcib_match(struct pci_attach_args *pa) 396 { 397 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 398 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 399 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 400 return (1); 401 return 0; 402 } 403 404 static bool 405 viaide_suspend(device_t dv PMF_FN_ARGS) 406 { 407 struct pciide_softc *sc = device_private(dv); 408 409 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 410 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 411 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 412 /* This two are VIA-only, but should be ignored by other devices. */ 413 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 414 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 415 416 return true; 417 } 418 419 static bool 420 viaide_resume(device_t dv PMF_FN_ARGS) 421 { 422 struct pciide_softc *sc = device_private(dv); 423 424 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 425 sc->sc_pm_reg[0]); 426 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 427 sc->sc_pm_reg[1]); 428 /* This two are VIA-only, but should be ignored by other devices. */ 429 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 430 sc->sc_pm_reg[2]); 431 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 432 sc->sc_pm_reg[3]); 433 434 return true; 435 } 436 437 static void 438 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 439 { 440 struct pciide_channel *cp; 441 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 442 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 443 int channel; 444 u_int32_t ideconf; 445 bus_size_t cmdsize, ctlsize; 446 pcireg_t pcib_id, pcib_class; 447 struct pci_attach_args pcib_pa; 448 449 if (pciide_chipen(sc, pa) == 0) 450 return; 451 452 switch (vendor) { 453 case PCI_VENDOR_VIATECH: 454 /* 455 * get a PCI tag for the ISA bridge. 456 */ 457 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 458 goto unknown; 459 pcib_id = pcib_pa.pa_id; 460 pcib_class = pcib_pa.pa_class; 461 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 462 "VIA Technologies "); 463 switch (PCI_PRODUCT(pcib_id)) { 464 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 465 aprint_normal("VT82C586 (Apollo VP) "); 466 if(PCI_REVISION(pcib_class) >= 0x02) { 467 aprint_normal("ATA33 controller\n"); 468 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 469 } else { 470 aprint_normal("controller\n"); 471 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 472 } 473 break; 474 case PCI_PRODUCT_VIATECH_VT82C596A: 475 aprint_normal("VT82C596A (Apollo Pro) "); 476 if (PCI_REVISION(pcib_class) >= 0x12) { 477 aprint_normal("ATA66 controller\n"); 478 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 479 } else { 480 aprint_normal("ATA33 controller\n"); 481 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 482 } 483 break; 484 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 485 aprint_normal("VT82C686A (Apollo KX133) "); 486 if (PCI_REVISION(pcib_class) >= 0x40) { 487 aprint_normal("ATA100 controller\n"); 488 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 489 } else { 490 aprint_normal("ATA66 controller\n"); 491 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 492 } 493 break; 494 case PCI_PRODUCT_VIATECH_VT8231: 495 aprint_normal("VT8231 ATA100 controller\n"); 496 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 497 break; 498 case PCI_PRODUCT_VIATECH_VT8233: 499 aprint_normal("VT8233 ATA100 controller\n"); 500 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 501 break; 502 case PCI_PRODUCT_VIATECH_VT8233A: 503 aprint_normal("VT8233A ATA133 controller\n"); 504 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 505 break; 506 case PCI_PRODUCT_VIATECH_VT8235: 507 aprint_normal("VT8235 ATA133 controller\n"); 508 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 509 break; 510 case PCI_PRODUCT_VIATECH_VT8237: 511 aprint_normal("VT8237 ATA133 controller\n"); 512 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 513 break; 514 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 515 aprint_normal("VT8237A ATA133 controller\n"); 516 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 517 break; 518 case PCI_PRODUCT_VIATECH_CX700_IDE: 519 aprint_normal("CX700 ATA133 controller\n"); 520 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 521 break; 522 case PCI_PRODUCT_VIATECH_CX700M2_IDE: 523 aprint_normal("CX700M2/VX700 ATA133 controller\n"); 524 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 525 break; 526 default: 527 unknown: 528 aprint_normal("unknown VIA ATA controller\n"); 529 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 530 } 531 sc->sc_apo_regbase = APO_VIA_REGBASE; 532 break; 533 case PCI_VENDOR_AMD: 534 switch (sc->sc_pp->ide_product) { 535 case PCI_PRODUCT_AMD_PBC8111_IDE: 536 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 537 break; 538 case PCI_PRODUCT_AMD_CS5536_IDE: 539 case PCI_PRODUCT_AMD_PBC766_IDE: 540 case PCI_PRODUCT_AMD_PBC768_IDE: 541 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 542 break; 543 default: 544 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 545 } 546 sc->sc_apo_regbase = APO_AMD_REGBASE; 547 break; 548 case PCI_VENDOR_NVIDIA: 549 switch (sc->sc_pp->ide_product) { 550 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 551 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 552 break; 553 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 554 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 555 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 556 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 557 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 558 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 559 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 560 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 561 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 562 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 563 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 564 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 565 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 566 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 567 break; 568 } 569 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 570 break; 571 default: 572 panic("via_chip_map: unknown vendor"); 573 } 574 575 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 576 "bus-master DMA support present"); 577 pciide_mapreg_dma(sc, pa); 578 aprint_verbose("\n"); 579 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 580 if (sc->sc_dma_ok) { 581 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 582 sc->sc_wdcdev.irqack = pciide_irqack; 583 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 584 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 585 } 586 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 587 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 588 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 589 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 590 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 591 592 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 593 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 594 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 595 596 wdc_allocate_regs(&sc->sc_wdcdev); 597 598 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 599 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 600 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 601 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 602 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 603 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 604 DEBUG_PROBE); 605 606 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 607 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 608 channel++) { 609 cp = &sc->pciide_channels[channel]; 610 if (pciide_chansetup(sc, channel, interface) == 0) 611 continue; 612 613 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 614 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 615 "%s channel ignored (disabled)\n", cp->name); 616 cp->ata_channel.ch_flags |= ATACH_DISABLED; 617 continue; 618 } 619 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 620 pciide_pci_intr); 621 } 622 } 623 624 static void 625 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 626 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 627 int (*pci_intr)(void *)) 628 { 629 struct ata_channel *wdc_cp; 630 struct pciide_softc *sc; 631 prop_bool_t compat_nat_enable; 632 633 wdc_cp = &cp->ata_channel; 634 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 635 compat_nat_enable = prop_dictionary_get( 636 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 637 "use-compat-native-irq"); 638 639 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 640 /* native mode with irq 14/15 requested? */ 641 if (compat_nat_enable != NULL && 642 prop_bool_true(compat_nat_enable)) 643 via_mapregs_compat_native(pa, cp, cmdsizep, ctlsizep); 644 else 645 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 646 pci_intr); 647 } else { 648 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 649 ctlsizep); 650 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 651 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 652 } 653 wdcattach(wdc_cp); 654 } 655 656 /* 657 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 658 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 659 * programmed to use a single native PCI irq alone. So we install an interrupt 660 * handler for each channel, as in compatibility mode. 661 */ 662 static void 663 via_mapregs_compat_native(struct pci_attach_args *pa, 664 struct pciide_channel *cp, bus_size_t *cmdsizep, bus_size_t *ctlsizep) 665 { 666 struct ata_channel *wdc_cp; 667 struct pciide_softc *sc; 668 669 wdc_cp = &cp->ata_channel; 670 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 671 672 /* XXX prevent pciide_mapregs_native from installing a handler */ 673 if (sc->sc_pci_ih == NULL) 674 sc->sc_pci_ih = (void *)~0; 675 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL); 676 677 /* interrupts are fixed to 14/15, as in compatibility mode */ 678 cp->compat = 1; 679 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 680 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 681 cp->ih = pciide_machdep_compat_intr_establish( 682 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 683 pciide_compat_intr, cp); 684 if (cp->ih == NULL) { 685 #endif 686 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 687 "no compatibility interrupt for " 688 "use by %s channel\n", cp->name); 689 wdc_cp->ch_flags |= ATACH_DISABLED; 690 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 691 } 692 sc->sc_pci_ih = cp->ih; /* XXX */ 693 #endif 694 } 695 } 696 697 static void 698 via_setup_channel(struct ata_channel *chp) 699 { 700 u_int32_t udmatim_reg, datatim_reg; 701 u_int8_t idedma_ctl; 702 int mode, drive, s; 703 struct ata_drive_datas *drvp; 704 struct atac_softc *atac = chp->ch_atac; 705 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 706 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 707 #ifndef PCIIDE_AMD756_ENABLEDMA 708 int rev = PCI_REVISION( 709 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 710 #endif 711 712 idedma_ctl = 0; 713 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 714 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 715 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 716 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 717 718 /* setup DMA if needed */ 719 pciide_channel_dma_setup(cp); 720 721 for (drive = 0; drive < 2; drive++) { 722 drvp = &chp->ch_drive[drive]; 723 /* If no drive, skip */ 724 if ((drvp->drive_flags & DRIVE) == 0) 725 continue; 726 /* add timing values, setup DMA if needed */ 727 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 728 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 729 mode = drvp->PIO_mode; 730 goto pio; 731 } 732 if ((atac->atac_cap & ATAC_CAP_UDMA) && 733 (drvp->drive_flags & DRIVE_UDMA)) { 734 /* use Ultra/DMA */ 735 s = splbio(); 736 drvp->drive_flags &= ~DRIVE_DMA; 737 splx(s); 738 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 739 APO_UDMA_EN_MTH(chp->ch_channel, drive); 740 switch (PCI_VENDOR(sc->sc_pci_id)) { 741 case PCI_VENDOR_VIATECH: 742 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 743 /* 8233a */ 744 udmatim_reg |= APO_UDMA_TIME( 745 chp->ch_channel, 746 drive, 747 via_udma133_tim[drvp->UDMA_mode]); 748 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 749 /* 686b */ 750 udmatim_reg |= APO_UDMA_TIME( 751 chp->ch_channel, 752 drive, 753 via_udma100_tim[drvp->UDMA_mode]); 754 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 755 /* 596b or 686a */ 756 udmatim_reg |= APO_UDMA_CLK66( 757 chp->ch_channel); 758 udmatim_reg |= APO_UDMA_TIME( 759 chp->ch_channel, 760 drive, 761 via_udma66_tim[drvp->UDMA_mode]); 762 } else { 763 /* 596a or 586b */ 764 udmatim_reg |= APO_UDMA_TIME( 765 chp->ch_channel, 766 drive, 767 via_udma33_tim[drvp->UDMA_mode]); 768 } 769 break; 770 case PCI_VENDOR_AMD: 771 case PCI_VENDOR_NVIDIA: 772 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 773 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 774 break; 775 } 776 /* can use PIO timings, MW DMA unused */ 777 mode = drvp->PIO_mode; 778 } else { 779 /* use Multiword DMA, but only if revision is OK */ 780 s = splbio(); 781 drvp->drive_flags &= ~DRIVE_UDMA; 782 splx(s); 783 #ifndef PCIIDE_AMD756_ENABLEDMA 784 /* 785 * The workaround doesn't seem to be necessary 786 * with all drives, so it can be disabled by 787 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 788 * triggered. 789 */ 790 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 791 sc->sc_pp->ide_product == 792 PCI_PRODUCT_AMD_PBC756_IDE && 793 AMD756_CHIPREV_DISABLEDMA(rev)) { 794 aprint_normal( 795 "%s:%d:%d: multi-word DMA disabled due " 796 "to chip revision\n", 797 device_xname( 798 sc->sc_wdcdev.sc_atac.atac_dev), 799 chp->ch_channel, drive); 800 mode = drvp->PIO_mode; 801 s = splbio(); 802 drvp->drive_flags &= ~DRIVE_DMA; 803 splx(s); 804 goto pio; 805 } 806 #endif 807 /* mode = min(pio, dma+2) */ 808 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 809 mode = drvp->PIO_mode; 810 else 811 mode = drvp->DMA_mode + 2; 812 } 813 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 814 815 pio: /* setup PIO mode */ 816 if (mode <= 2) { 817 drvp->DMA_mode = 0; 818 drvp->PIO_mode = 0; 819 mode = 0; 820 } else { 821 drvp->PIO_mode = mode; 822 drvp->DMA_mode = mode - 2; 823 } 824 datatim_reg |= 825 APO_DATATIM_PULSE(chp->ch_channel, drive, 826 apollo_pio_set[mode]) | 827 APO_DATATIM_RECOV(chp->ch_channel, drive, 828 apollo_pio_rec[mode]); 829 } 830 if (idedma_ctl != 0) { 831 /* Add software bits in status register */ 832 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 833 idedma_ctl); 834 } 835 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 836 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 837 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 838 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 839 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 840 } 841 842 static int 843 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 844 { 845 bus_size_t satasize; 846 int maptype, ret; 847 848 if (pciide_chipen(sc, pa) == 0) 849 return 0; 850 851 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 852 "bus-master DMA support present"); 853 pciide_mapreg_dma(sc, pa); 854 aprint_verbose("\n"); 855 856 /* 857 * Enable memory-space access if it isn't already there. 858 */ 859 if (pa->pa_memt && (pa->pa_flags & PCI_FLAGS_MEM_ENABLED) == 0) { 860 pcireg_t csr; 861 862 pa->pa_flags |= PCI_FLAGS_MEM_ENABLED; 863 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 864 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 865 csr | PCI_COMMAND_MEM_ENABLE); 866 } 867 868 if (sc->sc_dma_ok) { 869 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 870 sc->sc_wdcdev.irqack = pciide_irqack; 871 } 872 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 873 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 874 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 875 876 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 877 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 878 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 879 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 880 881 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 882 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 883 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 884 885 wdc_allocate_regs(&sc->sc_wdcdev); 886 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 887 PCI_MAPREG_START + 0x14); 888 switch(maptype) { 889 case PCI_MAPREG_TYPE_IO: 890 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 891 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 892 NULL, &satasize); 893 break; 894 case PCI_MAPREG_MEM_TYPE_32BIT: 895 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 896 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 897 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 898 NULL, &satasize); 899 break; 900 default: 901 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 902 "couldn't map sata regs, unsupported maptype (0x%x)\n", 903 maptype); 904 return 0; 905 } 906 if (ret != 0) { 907 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 908 "couldn't map sata regs\n"); 909 return 0; 910 } 911 return 1; 912 } 913 914 static void 915 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 916 int satareg_shift) 917 { 918 struct pciide_channel *cp; 919 struct ata_channel *wdc_cp; 920 struct wdc_regs *wdr; 921 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 922 int channel; 923 bus_size_t cmdsize, ctlsize; 924 925 if (via_sata_chip_map_common(sc, pa) == 0) 926 return; 927 928 if (interface == 0) { 929 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 930 DEBUG_PROBE); 931 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 932 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 933 } 934 935 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 936 channel++) { 937 cp = &sc->pciide_channels[channel]; 938 if (pciide_chansetup(sc, channel, interface) == 0) 939 continue; 940 wdc_cp = &cp->ata_channel; 941 wdr = CHAN_TO_WDC_REGS(wdc_cp); 942 wdr->sata_iot = sc->sc_ba5_st; 943 wdr->sata_baseioh = sc->sc_ba5_sh; 944 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 945 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 946 &wdr->sata_status) != 0) { 947 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 948 "couldn't map channel %d sata_status regs\n", 949 wdc_cp->ch_channel); 950 continue; 951 } 952 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 953 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 954 &wdr->sata_error) != 0) { 955 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 956 "couldn't map channel %d sata_error regs\n", 957 wdc_cp->ch_channel); 958 continue; 959 } 960 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 961 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 962 &wdr->sata_control) != 0) { 963 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 964 "couldn't map channel %d sata_control regs\n", 965 wdc_cp->ch_channel); 966 continue; 967 } 968 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 969 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 970 pciide_pci_intr); 971 } 972 } 973 974 static void 975 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 976 { 977 via_sata_chip_map(sc, pa, 0); 978 } 979 980 static void 981 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 982 { 983 via_sata_chip_map(sc, pa, 6); 984 } 985 986 static void 987 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 988 { 989 via_sata_chip_map(sc, pa, 7); 990 } 991 992 static void 993 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 994 { 995 struct pciide_channel *cp; 996 struct ata_channel *wdc_cp; 997 struct wdc_regs *wdr; 998 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 999 int channel; 1000 bus_size_t cmdsize; 1001 pci_intr_handle_t intrhandle; 1002 const char *intrstr; 1003 int i; 1004 1005 if (via_sata_chip_map_common(sc, pa) == 0) 1006 return; 1007 1008 if (interface == 0) { 1009 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 1010 DEBUG_PROBE); 1011 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 1012 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 1013 } 1014 1015 if (pci_intr_map(pa, &intrhandle) != 0) { 1016 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1017 "couldn't map native-PCI interrupt\n"); 1018 return; 1019 } 1020 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1021 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1022 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1023 if (sc->sc_pci_ih == NULL) { 1024 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1025 "couldn't establish native-PCI interrupt"); 1026 if (intrstr != NULL) 1027 aprint_error(" at %s", intrstr); 1028 aprint_error("\n"); 1029 return; 1030 } 1031 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1032 "using %s for native-PCI interrupt\n", 1033 intrstr ? intrstr : "unknown interrupt"); 1034 1035 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1036 channel++) { 1037 cp = &sc->pciide_channels[channel]; 1038 if (pciide_chansetup(sc, channel, interface) == 0) 1039 continue; 1040 cp->ata_channel.ch_ndrive = 1; 1041 wdc_cp = &cp->ata_channel; 1042 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1043 1044 wdr->sata_iot = sc->sc_ba5_st; 1045 wdr->sata_baseioh = sc->sc_ba5_sh; 1046 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1047 (wdc_cp->ch_channel << 6) + 0x0, 1, 1048 &wdr->sata_status) != 0) { 1049 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1050 "couldn't map channel %d sata_status regs\n", 1051 wdc_cp->ch_channel); 1052 continue; 1053 } 1054 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1055 (wdc_cp->ch_channel << 6) + 0x4, 1, 1056 &wdr->sata_error) != 0) { 1057 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1058 "couldn't map channel %d sata_error regs\n", 1059 wdc_cp->ch_channel); 1060 continue; 1061 } 1062 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1063 (wdc_cp->ch_channel << 6) + 0x8, 1, 1064 &wdr->sata_control) != 0) { 1065 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1066 "couldn't map channel %d sata_control regs\n", 1067 wdc_cp->ch_channel); 1068 continue; 1069 } 1070 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1071 1072 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 1073 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1074 NULL, &cmdsize) != 0) { 1075 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1076 "couldn't map %s channel regs\n", cp->name); 1077 } 1078 wdr->ctl_iot = wdr->cmd_iot; 1079 for (i = 0; i < WDC_NREG; i++) { 1080 if (bus_space_subregion(wdr->cmd_iot, 1081 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1082 &wdr->cmd_iohs[i]) != 0) { 1083 aprint_error_dev( 1084 sc->sc_wdcdev.sc_atac.atac_dev, 1085 "couldn't subregion %s " 1086 "channel cmd regs\n", cp->name); 1087 return; 1088 } 1089 } 1090 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1091 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1092 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1093 "couldn't map channel %d ctl regs\n", channel); 1094 return; 1095 } 1096 wdc_init_shadow_regs(wdc_cp); 1097 wdr->data32iot = wdr->cmd_iot; 1098 wdr->data32ioh = wdr->cmd_iohs[wd_data]; 1099 wdcattach(wdc_cp); 1100 } 1101 } 1102
Indexes created Sun Oct 19 16:10:00 GMT 2025