viaide.c revision 1.60
1 /* $NetBSD: viaide.c,v 1.60 2009/09/26 18:15:52 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.60 2009/09/26 18:15:52 jmcneill Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_apollo_reg.h> 44 45 static int via_pcib_match(struct pci_attach_args *); 46 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *); 47 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *, 48 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *)); 49 static void via_mapregs_compat_native(struct pci_attach_args *, 50 struct pciide_channel *, bus_size_t *, bus_size_t *); 51 static int via_sata_chip_map_common(struct pciide_softc *, 52 struct pci_attach_args *); 53 static void via_sata_chip_map(struct pciide_softc *, 54 struct pci_attach_args *, int); 55 static void via_sata_chip_map_0(struct pciide_softc *, 56 struct pci_attach_args *); 57 static void via_sata_chip_map_6(struct pciide_softc *, 58 struct pci_attach_args *); 59 static void via_sata_chip_map_7(struct pciide_softc *, 60 struct pci_attach_args *); 61 static void via_sata_chip_map_new(struct pciide_softc *, 62 struct pci_attach_args *); 63 static void via_setup_channel(struct ata_channel *); 64 65 static int viaide_match(device_t, cfdata_t, void *); 66 static void viaide_attach(device_t, device_t, void *); 67 static const struct pciide_product_desc * 68 viaide_lookup(pcireg_t); 69 static bool viaide_suspend(device_t PMF_FN_PROTO); 70 static bool viaide_resume(device_t PMF_FN_PROTO); 71 72 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc), 73 viaide_match, viaide_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_amd_products[] = { 76 { PCI_PRODUCT_AMD_PBC756_IDE, 77 0, 78 "AMD AMD756 IDE Controller", 79 via_chip_map 80 }, 81 { PCI_PRODUCT_AMD_PBC766_IDE, 82 0, 83 "AMD AMD766 IDE Controller", 84 via_chip_map 85 }, 86 { PCI_PRODUCT_AMD_PBC768_IDE, 87 0, 88 "AMD AMD768 IDE Controller", 89 via_chip_map 90 }, 91 { PCI_PRODUCT_AMD_PBC8111_IDE, 92 0, 93 "AMD AMD8111 IDE Controller", 94 via_chip_map 95 }, 96 { PCI_PRODUCT_AMD_CS5536_IDE, 97 0, 98 "AMD CS5536 IDE Controller", 99 via_chip_map 100 }, 101 { 0, 102 0, 103 NULL, 104 NULL 105 } 106 }; 107 108 static const struct pciide_product_desc pciide_nvidia_products[] = { 109 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 110 0, 111 "NVIDIA nForce IDE Controller", 112 via_chip_map 113 }, 114 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 115 0, 116 "NVIDIA nForce2 IDE Controller", 117 via_chip_map 118 }, 119 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133, 120 0, 121 "NVIDIA nForce2 Ultra 400 IDE Controller", 122 via_chip_map 123 }, 124 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA, 125 0, 126 "NVIDIA nForce2 Ultra 400 Serial ATA Controller", 127 via_sata_chip_map_6 128 }, 129 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133, 130 0, 131 "NVIDIA nForce3 IDE Controller", 132 via_chip_map 133 }, 134 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133, 135 0, 136 "NVIDIA nForce3 250 IDE Controller", 137 via_chip_map 138 }, 139 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA, 140 0, 141 "NVIDIA nForce3 250 Serial ATA Controller", 142 via_sata_chip_map_6 143 }, 144 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2, 145 0, 146 "NVIDIA nForce3 250 Serial ATA Controller", 147 via_sata_chip_map_6 148 }, 149 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133, 150 0, 151 "NVIDIA nForce4 IDE Controller", 152 via_chip_map 153 }, 154 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1, 155 0, 156 "NVIDIA nForce4 Serial ATA Controller", 157 via_sata_chip_map_6 158 }, 159 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2, 160 0, 161 "NVIDIA nForce4 Serial ATA Controller", 162 via_sata_chip_map_6 163 }, 164 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133, 165 0, 166 "NVIDIA nForce430 IDE Controller", 167 via_chip_map 168 }, 169 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1, 170 0, 171 "NVIDIA nForce430 Serial ATA Controller", 172 via_sata_chip_map_6 173 }, 174 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2, 175 0, 176 "NVIDIA nForce430 Serial ATA Controller", 177 via_sata_chip_map_6 178 }, 179 { PCI_PRODUCT_NVIDIA_MCP04_IDE, 180 0, 181 "NVIDIA MCP04 IDE Controller", 182 via_chip_map 183 }, 184 { PCI_PRODUCT_NVIDIA_MCP04_SATA, 185 0, 186 "NVIDIA MCP04 Serial ATA Controller", 187 via_sata_chip_map_6 188 }, 189 { PCI_PRODUCT_NVIDIA_MCP04_SATA2, 190 0, 191 "NVIDIA MCP04 Serial ATA Controller", 192 via_sata_chip_map_6 193 }, 194 { PCI_PRODUCT_NVIDIA_MCP55_IDE, 195 0, 196 "NVIDIA MCP55 IDE Controller", 197 via_chip_map 198 }, 199 { PCI_PRODUCT_NVIDIA_MCP55_SATA, 200 0, 201 "NVIDIA MCP55 Serial ATA Controller", 202 via_sata_chip_map_6 203 }, 204 { PCI_PRODUCT_NVIDIA_MCP55_SATA2, 205 0, 206 "NVIDIA MCP55 Serial ATA Controller", 207 via_sata_chip_map_6 208 }, 209 { PCI_PRODUCT_NVIDIA_MCP61_IDE, 210 0, 211 "NVIDIA MCP61 IDE Controller", 212 via_chip_map 213 }, 214 { PCI_PRODUCT_NVIDIA_MCP65_IDE, 215 0, 216 "NVIDIA MCP65 IDE Controller", 217 via_chip_map 218 }, 219 { PCI_PRODUCT_NVIDIA_MCP73_IDE, 220 0, 221 "NVIDIA MCP73 IDE Controller", 222 via_chip_map 223 }, 224 { PCI_PRODUCT_NVIDIA_MCP77_IDE, 225 0, 226 "NVIDIA MCP77 IDE Controller", 227 via_chip_map 228 }, 229 { PCI_PRODUCT_NVIDIA_MCP61_SATA, 230 0, 231 "NVIDIA MCP61 Serial ATA Controller", 232 via_sata_chip_map_6 233 }, 234 { PCI_PRODUCT_NVIDIA_MCP61_SATA2, 235 0, 236 "NVIDIA MCP61 Serial ATA Controller", 237 via_sata_chip_map_6 238 }, 239 { PCI_PRODUCT_NVIDIA_MCP61_SATA3, 240 0, 241 "NVIDIA MCP61 Serial ATA Controller", 242 via_sata_chip_map_6 243 }, 244 { PCI_PRODUCT_NVIDIA_MCP65_SATA, 245 0, 246 "NVIDIA MCP65 Serial ATA Controller", 247 via_sata_chip_map_6 248 }, 249 { PCI_PRODUCT_NVIDIA_MCP65_SATA2, 250 0, 251 "NVIDIA MCP65 Serial ATA Controller", 252 via_sata_chip_map_6 253 }, 254 { PCI_PRODUCT_NVIDIA_MCP65_SATA3, 255 0, 256 "NVIDIA MCP65 Serial ATA Controller", 257 via_sata_chip_map_6 258 }, 259 { PCI_PRODUCT_NVIDIA_MCP65_SATA4, 260 0, 261 "NVIDIA MCP65 Serial ATA Controller", 262 via_sata_chip_map_6 263 }, 264 { PCI_PRODUCT_NVIDIA_MCP67_IDE, 265 0, 266 "NVIDIA MCP67 IDE Controller", 267 via_chip_map, 268 }, 269 { PCI_PRODUCT_NVIDIA_MCP67_SATA, 270 0, 271 "NVIDIA MCP67 Serial ATA Controller", 272 via_sata_chip_map_6, 273 }, 274 { PCI_PRODUCT_NVIDIA_MCP67_SATA2, 275 0, 276 "NVIDIA MCP67 Serial ATA Controller", 277 via_sata_chip_map_6, 278 }, 279 { PCI_PRODUCT_NVIDIA_MCP67_SATA3, 280 0, 281 "NVIDIA MCP67 Serial ATA Controller", 282 via_sata_chip_map_6, 283 }, 284 { PCI_PRODUCT_NVIDIA_MCP67_SATA4, 285 0, 286 "NVIDIA MCP67 Serial ATA Controller", 287 via_sata_chip_map_6, 288 }, 289 { 0, 290 0, 291 NULL, 292 NULL 293 } 294 }; 295 296 static const struct pciide_product_desc pciide_via_products[] = { 297 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 298 0, 299 NULL, 300 via_chip_map, 301 }, 302 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 303 0, 304 NULL, 305 via_chip_map, 306 }, 307 { PCI_PRODUCT_VIATECH_CX700_IDE, 308 0, 309 NULL, 310 via_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_CX700M2_IDE, 313 0, 314 NULL, 315 via_chip_map, 316 }, 317 { PCI_PRODUCT_VIATECH_VT6421_RAID, 318 0, 319 "VIA Technologies VT6421 Serial RAID Controller", 320 via_sata_chip_map_new, 321 }, 322 { PCI_PRODUCT_VIATECH_VT8237_SATA, 323 0, 324 "VIA Technologies VT8237 SATA Controller", 325 via_sata_chip_map_7, 326 }, 327 { PCI_PRODUCT_VIATECH_VT8237A_SATA, 328 0, 329 "VIA Technologies VT8237A SATA Controller", 330 via_sata_chip_map_7, 331 }, 332 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2, 333 0, 334 "VIA Technologies VT8237A (5337) SATA Controller", 335 via_sata_chip_map_7, 336 }, 337 { PCI_PRODUCT_VIATECH_VT8237R_SATA, 338 0, 339 "VIA Technologies VT8237R SATA Controller", 340 via_sata_chip_map_0, 341 }, 342 { PCI_PRODUCT_VIATECH_VT8237S_SATA, 343 0, 344 "VIA Technologies VT8237S SATA Controller", 345 via_sata_chip_map_7, 346 }, 347 { 0, 348 0, 349 NULL, 350 NULL 351 } 352 }; 353 354 static const struct pciide_product_desc * 355 viaide_lookup(pcireg_t id) 356 { 357 358 switch (PCI_VENDOR(id)) { 359 case PCI_VENDOR_VIATECH: 360 return (pciide_lookup_product(id, pciide_via_products)); 361 362 case PCI_VENDOR_AMD: 363 return (pciide_lookup_product(id, pciide_amd_products)); 364 365 case PCI_VENDOR_NVIDIA: 366 return (pciide_lookup_product(id, pciide_nvidia_products)); 367 } 368 return (NULL); 369 } 370 371 static int 372 viaide_match(device_t parent, cfdata_t match, void *aux) 373 { 374 struct pci_attach_args *pa = aux; 375 376 if (viaide_lookup(pa->pa_id) != NULL) 377 return (2); 378 return (0); 379 } 380 381 static void 382 viaide_attach(device_t parent, device_t self, void *aux) 383 { 384 struct pci_attach_args *pa = aux; 385 struct pciide_softc *sc = device_private(self); 386 const struct pciide_product_desc *pp; 387 388 sc->sc_wdcdev.sc_atac.atac_dev = self; 389 390 pp = viaide_lookup(pa->pa_id); 391 if (pp == NULL) 392 panic("viaide_attach"); 393 pciide_common_attach(sc, pa, pp); 394 395 if (!pmf_device_register(self, viaide_suspend, viaide_resume)) 396 aprint_error_dev(self, "couldn't establish power handler\n"); 397 } 398 399 static int 400 via_pcib_match(struct pci_attach_args *pa) 401 { 402 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 403 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA && 404 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH) 405 return (1); 406 return 0; 407 } 408 409 static bool 410 viaide_suspend(device_t dv PMF_FN_ARGS) 411 { 412 struct pciide_softc *sc = device_private(dv); 413 414 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 415 /* APO_DATATIM(sc) includes APO_UDMA(sc) */ 416 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 417 /* This two are VIA-only, but should be ignored by other devices. */ 418 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)); 419 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc)); 420 421 return true; 422 } 423 424 static bool 425 viaide_resume(device_t dv PMF_FN_ARGS) 426 { 427 struct pciide_softc *sc = device_private(dv); 428 429 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc), 430 sc->sc_pm_reg[0]); 431 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), 432 sc->sc_pm_reg[1]); 433 /* This two are VIA-only, but should be ignored by other devices. */ 434 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc), 435 sc->sc_pm_reg[2]); 436 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc), 437 sc->sc_pm_reg[3]); 438 439 return true; 440 } 441 442 static void 443 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 444 { 445 struct pciide_channel *cp; 446 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 447 pcireg_t vendor = PCI_VENDOR(pa->pa_id); 448 int channel; 449 u_int32_t ideconf; 450 bus_size_t cmdsize, ctlsize; 451 pcireg_t pcib_id, pcib_class; 452 struct pci_attach_args pcib_pa; 453 454 if (pciide_chipen(sc, pa) == 0) 455 return; 456 457 switch (vendor) { 458 case PCI_VENDOR_VIATECH: 459 /* 460 * get a PCI tag for the ISA bridge. 461 */ 462 if (pci_find_device(&pcib_pa, via_pcib_match) == 0) 463 goto unknown; 464 pcib_id = pcib_pa.pa_id; 465 pcib_class = pcib_pa.pa_class; 466 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 467 "VIA Technologies "); 468 switch (PCI_PRODUCT(pcib_id)) { 469 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 470 aprint_normal("VT82C586 (Apollo VP) "); 471 if(PCI_REVISION(pcib_class) >= 0x02) { 472 aprint_normal("ATA33 controller\n"); 473 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 474 } else { 475 aprint_normal("controller\n"); 476 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 477 } 478 break; 479 case PCI_PRODUCT_VIATECH_VT82C596A: 480 aprint_normal("VT82C596A (Apollo Pro) "); 481 if (PCI_REVISION(pcib_class) >= 0x12) { 482 aprint_normal("ATA66 controller\n"); 483 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 484 } else { 485 aprint_normal("ATA33 controller\n"); 486 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 487 } 488 break; 489 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 490 aprint_normal("VT82C686A (Apollo KX133) "); 491 if (PCI_REVISION(pcib_class) >= 0x40) { 492 aprint_normal("ATA100 controller\n"); 493 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 494 } else { 495 aprint_normal("ATA66 controller\n"); 496 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 497 } 498 break; 499 case PCI_PRODUCT_VIATECH_VT8231: 500 aprint_normal("VT8231 ATA100 controller\n"); 501 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 502 break; 503 case PCI_PRODUCT_VIATECH_VT8233: 504 aprint_normal("VT8233 ATA100 controller\n"); 505 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 506 break; 507 case PCI_PRODUCT_VIATECH_VT8233A: 508 aprint_normal("VT8233A ATA133 controller\n"); 509 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 510 break; 511 case PCI_PRODUCT_VIATECH_VT8235: 512 aprint_normal("VT8235 ATA133 controller\n"); 513 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 514 break; 515 case PCI_PRODUCT_VIATECH_VT8237: 516 aprint_normal("VT8237 ATA133 controller\n"); 517 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 518 break; 519 case PCI_PRODUCT_VIATECH_VT8237A_ISA: 520 aprint_normal("VT8237A ATA133 controller\n"); 521 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 522 break; 523 case PCI_PRODUCT_VIATECH_CX700_IDE: 524 aprint_normal("CX700 ATA133 controller\n"); 525 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 526 break; 527 case PCI_PRODUCT_VIATECH_CX700M2_IDE: 528 aprint_normal("CX700M2/VX700 ATA133 controller\n"); 529 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 530 break; 531 default: 532 unknown: 533 aprint_normal("unknown VIA ATA controller\n"); 534 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 535 } 536 sc->sc_apo_regbase = APO_VIA_REGBASE; 537 break; 538 case PCI_VENDOR_AMD: 539 switch (sc->sc_pp->ide_product) { 540 case PCI_PRODUCT_AMD_PBC8111_IDE: 541 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 542 break; 543 case PCI_PRODUCT_AMD_CS5536_IDE: 544 case PCI_PRODUCT_AMD_PBC766_IDE: 545 case PCI_PRODUCT_AMD_PBC768_IDE: 546 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 547 break; 548 default: 549 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 550 } 551 sc->sc_apo_regbase = APO_AMD_REGBASE; 552 break; 553 case PCI_VENDOR_NVIDIA: 554 switch (sc->sc_pp->ide_product) { 555 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 556 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 557 break; 558 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 559 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133: 560 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133: 561 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133: 562 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133: 563 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133: 564 case PCI_PRODUCT_NVIDIA_MCP04_IDE: 565 case PCI_PRODUCT_NVIDIA_MCP55_IDE: 566 case PCI_PRODUCT_NVIDIA_MCP61_IDE: 567 case PCI_PRODUCT_NVIDIA_MCP65_IDE: 568 case PCI_PRODUCT_NVIDIA_MCP67_IDE: 569 case PCI_PRODUCT_NVIDIA_MCP73_IDE: 570 case PCI_PRODUCT_NVIDIA_MCP77_IDE: 571 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 572 break; 573 } 574 sc->sc_apo_regbase = APO_NVIDIA_REGBASE; 575 break; 576 default: 577 panic("via_chip_map: unknown vendor"); 578 } 579 580 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 581 "bus-master DMA support present"); 582 pciide_mapreg_dma(sc, pa); 583 aprint_verbose("\n"); 584 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 585 if (sc->sc_dma_ok) { 586 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 587 sc->sc_wdcdev.irqack = pciide_irqack; 588 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0) 589 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 590 } 591 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 592 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 593 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel; 594 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 595 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 596 597 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 598 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 599 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 600 601 wdc_allocate_regs(&sc->sc_wdcdev); 602 603 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, " 604 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 605 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)), 606 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)), 607 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 608 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), 609 DEBUG_PROBE); 610 611 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)); 612 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 613 channel++) { 614 cp = &sc->pciide_channels[channel]; 615 if (pciide_chansetup(sc, channel, interface) == 0) 616 continue; 617 618 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 619 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 620 "%s channel ignored (disabled)\n", cp->name); 621 cp->ata_channel.ch_flags |= ATACH_DISABLED; 622 continue; 623 } 624 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 625 pciide_pci_intr); 626 } 627 } 628 629 static void 630 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp, 631 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep, 632 int (*pci_intr)(void *)) 633 { 634 struct ata_channel *wdc_cp; 635 struct pciide_softc *sc; 636 prop_bool_t compat_nat_enable; 637 638 wdc_cp = &cp->ata_channel; 639 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 640 compat_nat_enable = prop_dictionary_get( 641 device_properties(sc->sc_wdcdev.sc_atac.atac_dev), 642 "use-compat-native-irq"); 643 644 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { 645 /* native mode with irq 14/15 requested? */ 646 if (compat_nat_enable != NULL && 647 prop_bool_true(compat_nat_enable)) 648 via_mapregs_compat_native(pa, cp, cmdsizep, ctlsizep); 649 else 650 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 651 pci_intr); 652 } else { 653 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 654 ctlsizep); 655 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 656 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 657 } 658 wdcattach(wdc_cp); 659 } 660 661 /* 662 * At least under certain (mis)configurations (e.g. on the "Pegasos" board) 663 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be 664 * programmed to use a single native PCI irq alone. So we install an interrupt 665 * handler for each channel, as in compatibility mode. 666 */ 667 static void 668 via_mapregs_compat_native(struct pci_attach_args *pa, 669 struct pciide_channel *cp, bus_size_t *cmdsizep, bus_size_t *ctlsizep) 670 { 671 struct ata_channel *wdc_cp; 672 struct pciide_softc *sc; 673 674 wdc_cp = &cp->ata_channel; 675 sc = CHAN_TO_PCIIDE(&cp->ata_channel); 676 677 /* XXX prevent pciide_mapregs_native from installing a handler */ 678 if (sc->sc_pci_ih == NULL) 679 sc->sc_pci_ih = (void *)~0; 680 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL); 681 682 /* interrupts are fixed to 14/15, as in compatibility mode */ 683 cp->compat = 1; 684 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) { 685 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 686 cp->ih = pciide_machdep_compat_intr_establish( 687 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel, 688 pciide_compat_intr, cp); 689 if (cp->ih == NULL) { 690 #endif 691 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 692 "no compatibility interrupt for " 693 "use by %s channel\n", cp->name); 694 wdc_cp->ch_flags |= ATACH_DISABLED; 695 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 696 } 697 sc->sc_pci_ih = cp->ih; /* XXX */ 698 #endif 699 } 700 } 701 702 static void 703 via_setup_channel(struct ata_channel *chp) 704 { 705 u_int32_t udmatim_reg, datatim_reg; 706 u_int8_t idedma_ctl; 707 int mode, drive, s; 708 struct ata_drive_datas *drvp; 709 struct atac_softc *atac = chp->ch_atac; 710 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 711 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 712 #ifndef PCIIDE_AMD756_ENABLEDMA 713 int rev = PCI_REVISION( 714 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 715 #endif 716 717 idedma_ctl = 0; 718 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)); 719 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc)); 720 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel); 721 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel); 722 723 /* setup DMA if needed */ 724 pciide_channel_dma_setup(cp); 725 726 for (drive = 0; drive < 2; drive++) { 727 drvp = &chp->ch_drive[drive]; 728 /* If no drive, skip */ 729 if ((drvp->drive_flags & DRIVE) == 0) 730 continue; 731 /* add timing values, setup DMA if needed */ 732 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 733 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 734 mode = drvp->PIO_mode; 735 goto pio; 736 } 737 if ((atac->atac_cap & ATAC_CAP_UDMA) && 738 (drvp->drive_flags & DRIVE_UDMA)) { 739 /* use Ultra/DMA */ 740 s = splbio(); 741 drvp->drive_flags &= ~DRIVE_DMA; 742 splx(s); 743 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) | 744 APO_UDMA_EN_MTH(chp->ch_channel, drive); 745 switch (PCI_VENDOR(sc->sc_pci_id)) { 746 case PCI_VENDOR_VIATECH: 747 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) { 748 /* 8233a */ 749 udmatim_reg |= APO_UDMA_TIME( 750 chp->ch_channel, 751 drive, 752 via_udma133_tim[drvp->UDMA_mode]); 753 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) { 754 /* 686b */ 755 udmatim_reg |= APO_UDMA_TIME( 756 chp->ch_channel, 757 drive, 758 via_udma100_tim[drvp->UDMA_mode]); 759 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) { 760 /* 596b or 686a */ 761 udmatim_reg |= APO_UDMA_CLK66( 762 chp->ch_channel); 763 udmatim_reg |= APO_UDMA_TIME( 764 chp->ch_channel, 765 drive, 766 via_udma66_tim[drvp->UDMA_mode]); 767 } else { 768 /* 596a or 586b */ 769 udmatim_reg |= APO_UDMA_TIME( 770 chp->ch_channel, 771 drive, 772 via_udma33_tim[drvp->UDMA_mode]); 773 } 774 break; 775 case PCI_VENDOR_AMD: 776 case PCI_VENDOR_NVIDIA: 777 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel, 778 drive, amd7x6_udma_tim[drvp->UDMA_mode]); 779 break; 780 } 781 /* can use PIO timings, MW DMA unused */ 782 mode = drvp->PIO_mode; 783 } else { 784 /* use Multiword DMA, but only if revision is OK */ 785 s = splbio(); 786 drvp->drive_flags &= ~DRIVE_UDMA; 787 splx(s); 788 #ifndef PCIIDE_AMD756_ENABLEDMA 789 /* 790 * The workaround doesn't seem to be necessary 791 * with all drives, so it can be disabled by 792 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 793 * triggered. 794 */ 795 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD && 796 sc->sc_pp->ide_product == 797 PCI_PRODUCT_AMD_PBC756_IDE && 798 AMD756_CHIPREV_DISABLEDMA(rev)) { 799 aprint_normal( 800 "%s:%d:%d: multi-word DMA disabled due " 801 "to chip revision\n", 802 device_xname( 803 sc->sc_wdcdev.sc_atac.atac_dev), 804 chp->ch_channel, drive); 805 mode = drvp->PIO_mode; 806 s = splbio(); 807 drvp->drive_flags &= ~DRIVE_DMA; 808 splx(s); 809 goto pio; 810 } 811 #endif 812 /* mode = min(pio, dma+2) */ 813 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 814 mode = drvp->PIO_mode; 815 else 816 mode = drvp->DMA_mode + 2; 817 } 818 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 819 820 pio: /* setup PIO mode */ 821 if (mode <= 2) { 822 drvp->DMA_mode = 0; 823 drvp->PIO_mode = 0; 824 mode = 0; 825 } else { 826 drvp->PIO_mode = mode; 827 drvp->DMA_mode = mode - 2; 828 } 829 datatim_reg |= 830 APO_DATATIM_PULSE(chp->ch_channel, drive, 831 apollo_pio_set[mode]) | 832 APO_DATATIM_RECOV(chp->ch_channel, drive, 833 apollo_pio_rec[mode]); 834 } 835 if (idedma_ctl != 0) { 836 /* Add software bits in status register */ 837 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 838 idedma_ctl); 839 } 840 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg); 841 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg); 842 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 843 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)), 844 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE); 845 } 846 847 static int 848 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa) 849 { 850 bus_size_t satasize; 851 int maptype, ret; 852 853 if (pciide_chipen(sc, pa) == 0) 854 return 0; 855 856 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 857 "bus-master DMA support present"); 858 pciide_mapreg_dma(sc, pa); 859 aprint_verbose("\n"); 860 861 if (sc->sc_dma_ok) { 862 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 863 sc->sc_wdcdev.irqack = pciide_irqack; 864 } 865 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 866 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 867 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 868 869 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 870 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 871 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 872 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 873 874 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 875 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 876 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 877 878 wdc_allocate_regs(&sc->sc_wdcdev); 879 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 880 PCI_MAPREG_START + 0x14); 881 switch(maptype) { 882 case PCI_MAPREG_TYPE_IO: 883 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 884 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 885 NULL, &satasize); 886 break; 887 case PCI_MAPREG_MEM_TYPE_32BIT: 888 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 889 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 890 0, &sc->sc_ba5_st, &sc->sc_ba5_sh, 891 NULL, &satasize); 892 break; 893 default: 894 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 895 "couldn't map sata regs, unsupported maptype (0x%x)\n", 896 maptype); 897 return 0; 898 } 899 if (ret != 0) { 900 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 901 "couldn't map sata regs\n"); 902 return 0; 903 } 904 return 1; 905 } 906 907 static void 908 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa, 909 int satareg_shift) 910 { 911 struct pciide_channel *cp; 912 struct ata_channel *wdc_cp; 913 struct wdc_regs *wdr; 914 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 915 int channel; 916 bus_size_t cmdsize, ctlsize; 917 918 if (via_sata_chip_map_common(sc, pa) == 0) 919 return; 920 921 if (interface == 0) { 922 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 923 DEBUG_PROBE); 924 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 925 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 926 } 927 928 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 929 channel++) { 930 cp = &sc->pciide_channels[channel]; 931 if (pciide_chansetup(sc, channel, interface) == 0) 932 continue; 933 wdc_cp = &cp->ata_channel; 934 wdr = CHAN_TO_WDC_REGS(wdc_cp); 935 wdr->sata_iot = sc->sc_ba5_st; 936 wdr->sata_baseioh = sc->sc_ba5_sh; 937 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 938 (wdc_cp->ch_channel << satareg_shift) + 0x0, 1, 939 &wdr->sata_status) != 0) { 940 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 941 "couldn't map channel %d sata_status regs\n", 942 wdc_cp->ch_channel); 943 continue; 944 } 945 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 946 (wdc_cp->ch_channel << satareg_shift) + 0x4, 1, 947 &wdr->sata_error) != 0) { 948 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 949 "couldn't map channel %d sata_error regs\n", 950 wdc_cp->ch_channel); 951 continue; 952 } 953 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 954 (wdc_cp->ch_channel << satareg_shift) + 0x8, 1, 955 &wdr->sata_control) != 0) { 956 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 957 "couldn't map channel %d sata_control regs\n", 958 wdc_cp->ch_channel); 959 continue; 960 } 961 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 962 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 963 pciide_pci_intr); 964 } 965 } 966 967 static void 968 via_sata_chip_map_0(struct pciide_softc *sc, struct pci_attach_args *pa) 969 { 970 via_sata_chip_map(sc, pa, 0); 971 } 972 973 static void 974 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa) 975 { 976 via_sata_chip_map(sc, pa, 6); 977 } 978 979 static void 980 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa) 981 { 982 via_sata_chip_map(sc, pa, 7); 983 } 984 985 static void 986 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa) 987 { 988 struct pciide_channel *cp; 989 struct ata_channel *wdc_cp; 990 struct wdc_regs *wdr; 991 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 992 int channel; 993 bus_size_t cmdsize; 994 pci_intr_handle_t intrhandle; 995 const char *intrstr; 996 int i; 997 998 if (via_sata_chip_map_common(sc, pa) == 0) 999 return; 1000 1001 if (interface == 0) { 1002 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"), 1003 DEBUG_PROBE); 1004 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 1005 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 1006 } 1007 1008 if (pci_intr_map(pa, &intrhandle) != 0) { 1009 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1010 "couldn't map native-PCI interrupt\n"); 1011 return; 1012 } 1013 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1014 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 1015 intrhandle, IPL_BIO, pciide_pci_intr, sc); 1016 if (sc->sc_pci_ih == NULL) { 1017 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1018 "couldn't establish native-PCI interrupt"); 1019 if (intrstr != NULL) 1020 aprint_error(" at %s", intrstr); 1021 aprint_error("\n"); 1022 return; 1023 } 1024 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1025 "using %s for native-PCI interrupt\n", 1026 intrstr ? intrstr : "unknown interrupt"); 1027 1028 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1029 channel++) { 1030 cp = &sc->pciide_channels[channel]; 1031 if (pciide_chansetup(sc, channel, interface) == 0) 1032 continue; 1033 cp->ata_channel.ch_ndrive = 1; 1034 wdc_cp = &cp->ata_channel; 1035 wdr = CHAN_TO_WDC_REGS(wdc_cp); 1036 1037 wdr->sata_iot = sc->sc_ba5_st; 1038 wdr->sata_baseioh = sc->sc_ba5_sh; 1039 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1040 (wdc_cp->ch_channel << 6) + 0x0, 1, 1041 &wdr->sata_status) != 0) { 1042 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1043 "couldn't map channel %d sata_status regs\n", 1044 wdc_cp->ch_channel); 1045 continue; 1046 } 1047 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1048 (wdc_cp->ch_channel << 6) + 0x4, 1, 1049 &wdr->sata_error) != 0) { 1050 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1051 "couldn't map channel %d sata_error regs\n", 1052 wdc_cp->ch_channel); 1053 continue; 1054 } 1055 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 1056 (wdc_cp->ch_channel << 6) + 0x8, 1, 1057 &wdr->sata_control) != 0) { 1058 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1059 "couldn't map channel %d sata_control regs\n", 1060 wdc_cp->ch_channel); 1061 continue; 1062 } 1063 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 1064 1065 if (pci_mapreg_map(pa, (0x10 + (4 * (channel))), 1066 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh, 1067 NULL, &cmdsize) != 0) { 1068 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1069 "couldn't map %s channel regs\n", cp->name); 1070 } 1071 wdr->ctl_iot = wdr->cmd_iot; 1072 for (i = 0; i < WDC_NREG; i++) { 1073 if (bus_space_subregion(wdr->cmd_iot, 1074 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 1075 &wdr->cmd_iohs[i]) != 0) { 1076 aprint_error_dev( 1077 sc->sc_wdcdev.sc_atac.atac_dev, 1078 "couldn't subregion %s " 1079 "channel cmd regs\n", cp->name); 1080 return; 1081 } 1082 } 1083 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 1084 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) { 1085 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1086 "couldn't map channel %d ctl regs\n", channel); 1087 return; 1088 } 1089 wdc_init_shadow_regs(wdc_cp); 1090 wdcattach(wdc_cp); 1091 } 1092 } 1093
Indexes created Sun Oct 19 02:09:48 GMT 2025